71 results about "Cell delay" patented technology

An integrated circuit (IC) including at least one combinational logic path. The combinational logic path includes two types of logic blocks cells that compensate each other for fabrication parameter effects on cell transistors. The two types may be dense cells with field effect transistor (FET) gates on contacted pitch and isolated cells with FET gates on wider than contacted pitch. Dense cell delay changes from the FET gates being printed out of focus are offset by isolated cell delay changes.

In high speed cell switching networks, a Call Admission Control (CAC) procedure is performed on each connection according to a specified Traffic Descriptor. A mandatory parameter of the Traffic Descriptor is the Peak Cell Rate (PCR), associated with a Cell Delay Variation Tolerance (CDVT). Connections which specify a high CDVT value may potentially send into the network bursts of cells at a rate much higher than the declared Peak Cell Rate, which may lead to congestion in cell buffers of intermediate network nodes. Guaranteeing the Quality of Service (QoS) for such connections may require the reservation of a high amount of resources in the network, leading to poor utilization of those resources. A Call Admission Control procedure, associated with an Usage Parameter Control/Network Parameter Control mechanism, provides: accepting not bursty connections and guaranteeing the Quality of Service requested at connection setup, accepting very bursty connections and guaranteeing a minimal Quality of Service rather than simply rejecting them, protecting the network from potentially too bursty traffic, determining a bandwidth reservation method based on a Mean Burst Length, for every connection, minimizing the bandwidth reservation while satisfying the required Quality of Service.

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

A mixed signal system includes a digital circuit (17) clocked by a digital clock signal, an analog circuit (18) clocked by an analog clock signal, and clock generation circuitry (15) including a delay locked loop (20) including a N-cell delay line (21) having an input for receiving a reference clock signal and a plurality of delay outputs (22), and a multiplexer (30) having a plurality of inputs coupled to the plurality of delay outputs (22), respectively. A selection signal (34) causes the multiplexer (30) to couple a selected one of the delay outputs (22) to an output (32) of the multiplexer (30) so as to cause the analog clock signal and the digital clock signal to be sufficiently skewed from each other to minimize an inaccuracy in the analog circuit (18) caused by a noise glitch associated with the digital clock signal.

In a communication system comprising a link layer device connectable to one or more physical layer devices, the link layer device is configured using an efficient shared architecture for processing data associated with a plurality of links including at least one ingress link and at least one egress link. The link layer device comprises an ingress data clock processor configured to generate an ingress clock signal for processing data associated with said at least one ingress link, an egress data clock processor configured to generate an egress clock signal for processing data associated with said at least one egress link, and a control and configuration unit shared by the ingress data clock processor and the egress data clock processor. Another aspect of the invention relates to a buffer adaptive processor that in an illustrative embodiment limits clock variability in the presence of cell delay variation or cell loss.

Methods and apparatus for increasing the accuracy of timing characterization of a circuit including one or more cells in a cell library are provided. One method includes the steps of: performing cell library timing characterization for each of the cells in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to first and second PVT corners, respectively, in the cell library; calculating respective cell delays for the one or more cells in the circuit, the cell delay calculation being a function of temperature for each instance of the one or more cells; and incorporating the cell delay calculation into the timing characterization for each of the cells in the circuit to thereby increase the accuracy of the timing characterization.

An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage V_SC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

A method of calculating delay for a process variation includes finding a value for each of exactly two independent variables that results in a maximum or minimum variation of estimated cell delay plus net delay, calculating a variation of resistance from the value found for each of the exactly two independent variables, calculating a variation of capacitance from the value found for each of the exactly two independent variables, adding the calculated variation of resistance to a net resistance to generate a modified net resistance for a selected net, adding the calculated variation of capacitance to a net capacitance to generate a modified net capacitance for the selected net, and calculating the cell delay plus net delay from the modified net resistance and the modified net capacitance.

In a circuit simulation step, a cell transistor level net list is input, the slew of an input signal waveform and the magnitude of a load capacitance connected to a cell output terminal are varied for each cell, to perform a circuit simulation of each cell for obtaining an output signal waveform. Next, in a dependence table generation step, the dependence of the output signal waveform slew upon the input slew rate and the load capacitance is calculated for each cell, the dependence thus calculated is compared with a predetermined threshold level, and according to the dependence level, a delay calculation expression with consideration taken to the delay of signal propagation between the cell input and output terminals and another without such consideration are selectively used. Accordingly, the delay times of the cells forming a semiconductor integrated circuit can be calculated at high accuracy and at high processing speed.

A method and apparatus are disclosed for ATM Adaptation Layer (AAL) staggered constant bit rate cell scheduling. Cells from a plurality of virtual circuits are scheduled. Each of the virtual circuits have a transmission characteristic and each of the plurality of virtual circuits are classified into one of a plurality of stagger groups based on similar transmission characteristics. For each frame synchronization, a cell is transmitted from a given virtual circuit until a predefined cell threshold is exceeded for the stagger group containing the given virtual circuit. A Cell Delay Variation of each of the virtual circuits will not exceed a given time interval. A scheduler can be allocated for each connection or for each period.

The invention discloses a unit delay prediction method based on a neural network, comprising the following steps: S1, selecting characteristic quantities required by SPICE simulation and neural network training; 2, randomly selecting that characteristic value, adopting SPICE to simulate and measure the delay of the unit, and establishing a sample set of the delay of the unit; S3, dividing the unitdelay sample set obtained by SPICE simulation into training sample set and test sample set, training the neural network model by a training sample set, and verifying the accuracy of neural network bytesting sample set, comparing the error between the unit delay predicted by testing sample set and the unit delay measured by SPICE simulation, and optimizing repeatedly the neural network parametersto reduce the error. The neural network model is a prediction model of unit delay. The invention also discloses a cell delay sensitivity calculation method. The invention has the advantages of high precision, low modeling cost and fast prediction speed.

A system and method for clock optimization to achieve timing signoff in an electronic circuit and an EDA tool that embodies the system or the method. In one embodiment, the system includes: (1) a clock cell identifier/sorter configured to identify at least some clock cells in a clock network associated with an electronic circuit design and sort the cells according to breadth, (2) a slack analyzer associated with the clock cell identifier/sorter and configured to identify flops that are downstream of the cells and determine a worst setup and hold timing slack thereof and (3) a clock cell delay adjuster associated with the slack analyzer and configured to adjust delays of the cells subject to the worst setup and hold timing slack.

Method and apparatus for analyzing intra-cell delay times. The delay time between cells is measured and the number of times the measured delay times equals each of a plurality of predefined values is calculated. A graph is displayed indicating the count for each of the plurality of predefined values.

The invention discloses a method for detecting a biological ultra-weak photon radiation spectrum. The method includes the steps firstly, delayed luminescence curve data of a living biological sample on different wave lengths are collected accurately, and then fitting is performed on measurement data under the wave lengths by the utilization of the least square method according to the kinetic equation of cell delayed luminescence. Kinetic equation parameters obtained in fitting comprise parameters ISL for describing spontaneous luminescence of the sample, and the parameters are the spontaneous luminescence intensity under the wave lengths. Through the method, the spontaneous photon radiation spectrum of the sample can be measured indirectly. The problem that due to the fact that the spontaneous photon radiation intensity of the sample is too low, the spectrum of the sample cannot be detected directly is avoided.

The invention discloses a multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint. The multi-threshold-value unit replacing method based on hierarchical processing and cluster constraint comprises the following steps: in parameter extracting stage, reading a parallel algorithm and a design constraint, counting combinational logic circuit nodes, and acquiring cell delay of the circuit nodes, static power consumption and a sequential path number; in a parameter analyzing and computing stage, computing cell delay variable quantity of the circuit nodes,static power consumption variable quantity and the ratio of the static power consumption variable quantity to the cell delay variable quantity; and in a to-be-replaced circuit node selecting stage, layering the circuit nodes on the basis of layering parameters, visiting the circuit nodes from the top layer to the bottom layer, tracing the worst timing sequence path of the circuit nodes, counting same-cluster circuit nodes in the time sequence path, setting a same-cluster circuit node priority and successively visiting the same-cluster circuit nodes, judging whether the circuit nodes meet design requirements or not, and outputting to-be-replaced circuit nodes. Selection of ASIC design to-be-replaced circuit nodes can be finished automatically, complexity caused by a traditional method is reduced, and the working efficiency is improved.

An ATM network traffic shaper is implemented in hardware. The traffic shaper shapes transmit data on one or more virtual circuits (VCs) according to the specified quality of service (QoS) parameters. Thus, the traffic shaper provides for the delivery of associated data cells in accordance with the specified QoS parameters. The traffic shaper is scalable in that the number of supported VCs can be increased with a relatively small increase in the size of the device and associated logic gates. The traffic shaper supports constant bit rate (CBR), variable bit rate (VBR), and unknown bit rate (UBR) service types and generates cell transmit requests with zero cell delay variation (CDVT). The traffic shaper also provides very high resolution in terms of bit rate specification. Varying shaping resolutions are achieved by varying a shaping interval time (SIT) generated by a SIT counter.

In one embodiment of the present invention, the performance of an electronic circuit having a clock path between a clock source cell and a clock leaf cell is characterized over a simulation duration, where the clock path has one or more intermediate cells. Variations in the effective power supply voltage level at at least one intermediate cell over the simulation duration are determined using a system-level power-grid simulation tool. Static timing analysis (STA) software is used to determine cell delays for at least one of the intermediate cells for different clock-signal transitions at different times during the simulation duration. The cell delays are then used to generate one or more metrics characterizing the performance of the electronic circuit, such as maximum and minimum pulse widths, maximum cycle-to-cycle jitter, and maximum periodic jitter.

An apparatus for interfacing with a cell delay variation buffer and a re-assembly memory buffer includes a header and sequence number processing module that can interface with the cell delay variation buffer and a re-assembly processing module that can interface with the re-assembly memory buffer. The header and sequence number processing module causes payloads from the cells to be stored in annotated form in the cell delay variation buffer and then extracted. Payload information from the extracted annotated payload can be passed to the re-assembly processing module which causes it to be stored in the re-assembly memory buffer and extracted therefrom as needed. By splitting the cell delay variation and re-assembly buffer functions, less expensive commodity memory can be used for the cell delay variation buffer function.