71 results about "Cell delay" patented technology

A loop carrier system includes a home local area network having plural telephone modules and a hub coupled to in-home telephone wiring. The telephone modules and the hub communicate voice signals over the in-home wiring in a dedicated frequency band above baseband POTS. The hub converts between voice signals and voice packets and is connected to a network access device for transferring the voice packets from the home local area network to a telecommunications network which routes the voice packets to a gateway. The gateway converts between the voice packets and a circuit format compatible with a local digital voice switch. The home local area network includes a timing recovery mechanism which in the absence of a clock that is traceable to the Primary Reference Clock on the public network is robust to clock drift, cell delay variation and cell impairments.

In an asynchronous transfer mode (ATM) system, an apparatus is used to improve the transmission and reception of encoded ATM information over a wireless link having an encoder for encoding the information, assembling the information into a frame format and interleaving of the information for transmission over the wireless link. In addition, the apparatus also has a decoder for decoding information received via the wireless link which was encoded by a similar apparatus transmitting the information over the wireless link. Further, methods utilized by the encoder and decoder to improve transmission include increasing the bandwidth efficiency by dropping a header byte from every ATM cell; assembling separate header and payload frames; utilizing and rearranging idle / unassigned cells in the payload frame for storing and, thereby, increasing error correction code in the frame; dynamically changing the coding of frame in real time from one payload frame to optimize utilization of the mumber of available idle / unassigned cells occurring in each frame; restoring the positions of all idle / unassigned cells to their original position at a receiving end in order to leave the Cell Delay Variation unaffected; interleaving the frames to reduce burst errors during transmission; preservation of overhead parity bits present in the original frames received from a wireline link; cell Header error detection and correction through the use of a generated syndrome; and a synchronization pattern detection method during decoding.

Methods and apparatus for increasing the accuracy of timing characterization of a circuit including one or more cells in a cell library are provided. One method includes the steps of: performing cell library timing characterization for each of the cells in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to first and second PVT corners, respectively, in the cell library; calculating respective cell delays for the one or more cells in the circuit, the cell delay calculation being a function of temperature for each instance of the one or more cells; and incorporating the cell delay calculation into the timing characterization for each of the cells in the circuit to thereby increase the accuracy of the timing characterization.

A design method for an LSI includes: generating a delay library for use in a statistical STA, wherein the delay library provides a delay function that expresses a cell delay value as a function of model parameters of a transistor; generating a layout data; and calculating a delay value of a target cell based on the delay library and the layout data. The calculating includes: referring to the layout data to extract a parameter specifying a layout pattern around a target transistor; modulating model parameters of the target transistor such that the characteristics corresponding to the extracted parameter is obtained in a circuit simulation; calculating, by using the delay function, a reference delay value of the target cell; and calculating, by using the delay function and the modulation amount of the model parameter, a delay variation from the reference delay value depending on the modulation amount.

The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online / offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

An integrated circuit design optimization procedure to modify a cell feature, such as gate length, models changes in delay as a result of the modification. In the delay change calculation, a characteristic of an event in cell switching behavior, such as the output short-circuit voltage VSC, is determined for the modified cell, where changes in the determined characteristic correlate with changes in delay of the cell due to the modification. Next, a value for delay of the modified cell is determined as a function of the determined characteristic of the event. The procedure can be applied after placement and routing. A timing-constrained, leakage power reduction is described using the delay change model.

A method of forming an integrated circuit includes providing a first design of the integrated circuit; analyzing the first design to identify a first flip-flop having setup / hold violations and a second flip-flop not having setup / hold violations; and replacing the first flip-flop with a third flip-flop having a substantially same cell delay as the first flip-flop to form a second design of the integrated circuit. The first flip-flop and the third flip-flop have different setup and hold windows.