10 results about "Unit delay" patented technology

The invention relates to the technical field of chip design, and provides a critical path screening method based on a chip time sequence report, which comprises the following steps: collecting chip time sequence report data, screening out first N critical paths from the data based on time sequence index data, and establishing a path ID-delay type-scene three-dimensional data model; and calculating the delay ratio of the unit delay to the interconnection line delay in each critical path. Performing single-type delay, type relevance and RC condition influence comparison on different scenes to obtain delay characteristic data. The invention discloses a system for executing the method, which can avoid full data redundancy and improve the analysis efficiency by screening the first N critical paths. And the delay change rule in different scenes is quantified. The delay characteristic data reflects the actual influence of the key path delay on the time sequence, so that a designer can quickly position the delay bottleneck of the key path, and a basis and a reference are provided for the targeted optimization of the total delay of the chip in the later period.

The invention discloses a selector unit for dynamic switching of a standard unit, a ring oscillator and a test structure. Wherein the selector unit is connected in parallel with standard units with different threshold voltages, driving capabilities and logic functions, and is matched with the first switch control circuit, so that flexible switching of the differentiated standard units is realized, and the static architecture limitation of a traditional test circuit is broken through; according to the ring oscillator, a selector unit is embedded into a closed oscillation loop of a standard unit chain, a time sequence path of multiple unit combinations is formed through dynamic configuration, and the delay superposition effect between mixing units in an actual circuit is effectively simulated; the test structure is based on the configurable characteristic of the ring oscillator, combines a pin sharing mechanism of the first control signal multiplexing module, realizes parallel test of multiple unit combinations in a single chip, and eliminates multi-chip separate test requirements, so that a high-efficiency and high-coverage standard unit delay detection system is realized under the constraint of hardware resources, and the test efficiency is improved. And a verification basis is provided for deviation analysis of the process simulation model.

This application discloses a delay prediction method, apparatus, device, and storage medium. The delay prediction method includes: acquiring the unit characteristic information of each unit in a circuit and the characteristic sequence of each unit's interconnection; calculating the equivalent capacitance value of the interconnection path between units based on the capacitance and resistance values ​​of each unit's interconnection, and determining the target interconnection delay characteristics between units based on the equivalent capacitance values; determining the unit delay characteristics of each unit based on the equivalent capacitance values ​​and unit characteristic information; inputting the interconnection delay characteristics and unit delay characteristics into a preset delay prediction model; and performing prediction processing on the interconnection delay characteristics and unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit. This application equates the capacitance and resistance values ​​of each unit's interconnection to equivalent capacitance values, overcoming the deficiency in related technologies where the load capacitance ignores the resistance shielding effect, thereby reducing the error of the load capacitance and improving the accuracy of timing prediction.

The invention discloses an Ethernet clock phase synchronization method and a related device, and the method comprises the steps: obtaining a sending timestamp and a receiving timestamp through a time synchronization protocol, and calculating the time offset between a master clock and a slave clock according to the sending timestamp and the receiving timestamp; a delay configuration signal including the transmit and receive path delay control value is then generated. Control values are respectively input to programmable delay arrays on a sending path and a receiving path, and the number of unit delay units through which clock signals pass is dynamically controlled, so that the phases of a sending clock and a receiving sampling clock are accurately adjusted. According to the method, a circuit structure with unit delay time is utilized, refined dynamic compensation of the clock phase is achieved, and Ethernet clock synchronization precision and system data transmission reliability are effectively improved.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The invention relates to the field of signal processing, in particular to a high-speed signal compensation method, which comprises the following steps: enabling a high-speed signal to pass through a linear equalizer to obtain a first signal; comprising the following steps: enabling a first signal to pass through a first delay unit, and delaying a first specified number of unit delays to obtain a second signal; the duration of the unit delay is the duration of 1 bit of the high-speed signal; the second signal is output to the central processing unit; the central processing unit outputs a third signal according to the environment temperature during the operation of the high-speed signal, the plate condition of the circuit board and the waveform state of the second signal; and compensating the first signal by using the combination of the third signal and the second signal to obtain a compensated fourth signal. According to the method and the device, interference leaked to a plurality of adjacent time intervals is acquired by acquiring a plurality of continuous delayed data, and the noise coefficient is adjusted according to the real-time temperature and voltage value to act on the original signal of the receiving end, so that the signal-to-noise ratio of the received signal is improved.

The application provides an error calibration device, method, phase-locked loop and chip. The device comprises a phase offset controller configured to input a feedback clock output by a DCO at a second time and a preset reference clock into a TDC; and an output calibrator configured to compare an actual code output by the TDC with a preset check code, and output a comparison result to the digital loop filter; wherein the actual code = a phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the check code is obtained by offsetting the feedback clock output by the DCO at a first time and / or the preset reference clock by the phase offset controller to form a preset phase difference, and inputting the reference clock and the feedback clock with the preset phase difference into the TDC; and the check code = the preset phase difference / the unit delay. By comparing the actual code with the check code, the unit delay contained in both the actual code and the check code can be eliminated, so as to alleviate the jitter of the clock output by the DCO.

The present application relates to the technical field of integrated circuit design, more particularly, to a memory and computing unit circuit based on edge transmission delay, and a multi-bit time-domain multiply-accumulate calculation circuit constructed by using the unit circuit. The memory and computing unit circuit comprises two SRAM storage units, a delay calculation unit and a bit line connection switch. The two SRAM storage units are used for storing the weights required in calculation and providing 2-bit weights as multipliers. The delay calculation unit adopts four local delay units, each of which can calculate 2-bit weight multiplied by 2-bit input, so that the delay calculation unit can calculate 2-bit weight multiplied by 8-bit input, so as to improve the calculation efficiency. In addition, an inverter for regulating the edge signal is added in the local delay unit, so as to improve the accuracy of unit delay and time-domain accumulation.

The invention relates to the technical field of integrated circuits, in particular to a waveform compression method, a unit delay training method and a storage medium. The waveform compression method comprises the following steps: providing a simulation circuit, and obtaining voltage waveform data based on the simulation circuit; performing normalization processing on the voltage waveform data to obtain standard voltage waveform data; establishing a plurality of initial auto-encoders, wherein the number of coding parameters of the intermediate layer of each initial auto-encoder is different; performing compression training on the initial auto-encoder based on the standard voltage waveform data to obtain an auto-encoder; and an auto-encoder is used to encode an input waveform into a small number of parameters to participate in the training of the deep learning network. The problem that existing unit delay estimation is low in precision is solved.

The present disclosure provides implementations of a filter suitable for use in quantum computing systems and other low-power, high-speed applications. In some aspects, a filter circuit includes a series-connected arrangement of unit delays and summers in an alternating pattern. The filter circuit further includes a plurality of coefficient multipliers, each having a respective output connected with one or more of the summers, and each including a multiplexing stage including one or more multiplexers addressed using one or more bits of a respective input coefficient vector. A first coefficient multiplier of the plurality of coefficient multipliers includes a partial product stage configured to provide a plurality of integer partial products of an input data vector to the multiplexing stages of the plurality of coefficient multipliers.