4 results about "Unit delay" patented technology

This application discloses a delay prediction method, apparatus, device, and storage medium. The delay prediction method includes: acquiring the unit characteristic information of each unit in a circuit and the characteristic sequence of each unit's interconnection; calculating the equivalent capacitance value of the interconnection path between units based on the capacitance and resistance values ​​of each unit's interconnection, and determining the target interconnection delay characteristics between units based on the equivalent capacitance values; determining the unit delay characteristics of each unit based on the equivalent capacitance values ​​and unit characteristic information; inputting the interconnection delay characteristics and unit delay characteristics into a preset delay prediction model; and performing prediction processing on the interconnection delay characteristics and unit delay characteristics based on the delay prediction model to obtain the delay result of the circuit. This application equates the capacitance and resistance values ​​of each unit's interconnection to equivalent capacitance values, overcoming the deficiency in related technologies where the load capacitance ignores the resistance shielding effect, thereby reducing the error of the load capacitance and improving the accuracy of timing prediction.

The present application belongs to the technical field of low power consumption of integrated circuit design, and discloses a multi-threshold voltage unit distribution method, comprising the following steps: step 1: data preparation: obtaining a simplified path set according to a full high threshold circuit, and obtaining unit delay, timing increase / decrease factor and static power consumption value of the full high / low threshold circuit; step 2: distributing threshold according to the path set: distributing threshold point by point in the full high threshold circuit according to path weight and unit weight until the paths in the path set all meet timing requirements; and step 3: updating the path set: applying the threshold distribution result and performing static timing analysis, if the static timing analysis result does not meet timing, updating the path set and performing the threshold distribution operation according to the path set again until the static timing analysis result meets timing. The present application effectively reduces the method running time through the simplified path set, and ensures threshold distribution accuracy and timing convergence through updating the path set.

The invention relates to the field of signal processing, in particular to a high-speed signal compensation method, which comprises the following steps: enabling a high-speed signal to pass through a linear equalizer to obtain a first signal; comprising the following steps: enabling a first signal to pass through a first delay unit, and delaying a first specified number of unit delays to obtain a second signal; the duration of the unit delay is the duration of 1 bit of the high-speed signal; the second signal is output to the central processing unit; the central processing unit outputs a third signal according to the environment temperature during the operation of the high-speed signal, the plate condition of the circuit board and the waveform state of the second signal; and compensating the first signal by using the combination of the third signal and the second signal to obtain a compensated fourth signal. According to the method and the device, interference leaked to a plurality of adjacent time intervals is acquired by acquiring a plurality of continuous delayed data, and the noise coefficient is adjusted according to the real-time temperature and voltage value to act on the original signal of the receiving end, so that the signal-to-noise ratio of the received signal is improved.

The application provides an error calibration device, method, phase-locked loop and chip. The device comprises a phase offset controller configured to input a feedback clock output by a DCO at a second time and a preset reference clock into a TDC; and an output calibrator configured to compare an actual code output by the TDC with a preset check code, and output a comparison result to the digital loop filter; wherein the actual code = a phase difference between the feedback clock output by the DCO at the second time and the preset reference clock / the unit delay of the TDC; the check code is obtained by offsetting the feedback clock output by the DCO at a first time and / or the preset reference clock by the phase offset controller to form a preset phase difference, and inputting the reference clock and the feedback clock with the preset phase difference into the TDC; and the check code = the preset phase difference / the unit delay. By comparing the actual code with the check code, the unit delay contained in both the actual code and the check code can be eliminated, so as to alleviate the jitter of the clock output by the DCO.