Digital delay locked loop and control method thereof

Abstract

A digital delay locked loop(DLL) and a method for controlling the same are provided to improve the reliability of the DLL circuit by minimizing jitter. A digital delay locked loop(DLL) includes a clock generation unit, a delay line, a delay model, a phase comparison unit, a jitter detection unit and a delay control unit. The clock generation unit generates a source clock and a reference clock. The delay line is provided with a plurality of unit delays to delay the source clock by a predetermined time. The delay model reflects the delay time of the practical inner circuit on the output of the delay line. The phase comparison unit compares the reference clock with the phase of the feedback clock outputted from the delay model. The jitter detection unit detects the maximum jitter time in response to the phase comparison signal outputted from the phase comparison unit to output the multi-delay enable signal. And, the delay control unit controls the delay amount of the delay line to the unit delay or the multi-delay unit in response to the phase comparison signal and the multi-delay enable signal.

Description

technical field [0001] The present invention relates to a delay locked loop (DLL) used in a semiconductor storage device such as a double data rate (DDR) synchronous dynamic random access memory (SDRAM) or a single data rate (SDR) SDRAM, and more particularly to a Improved DLL in (jitter) feature. Background technique [0002] A Delay Locked Loop (DLL) is a circuit for controlling data timing, which is output to the outside of a semiconductor memory device (such as SDRAM) according to an external clock. Here, the external clock is a clock input from outside the semiconductor memory device. In order to transfer data to the chipset without any errors, the clock of the SDRAM should be synchronized with the clock of the chipset. [0003] The reason for using DLL in SDRAM is that when the external clock passes through the input clock buffer, line load, data output buffer and other logic circuits, the phase will be delayed, so that the phase of the external clock and the interna...

AI Technical Summary

Problems solved by technology

[0054] If the power supply voltage VDD decreases, the delay of the delay line and the delay model have an opposite delay change. This delay change will affect the phase comparator after a predetermined time

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