77 results about "Double data rate" patented technology

A method for memory system initialization to bootstrap error correction code (ECC) regions during system boot is described. The method includes partitioning a memory sub-system into sub-system memory segments. The method also includes using a last level cache coprocessor (LCP) to initialize a first of the sub-system memory segments to provide a first ECC region. The method also includes booting a system through the first ECC region of the memory sub-system. The method also includes using the LCP to initialize remaining ones of the sub-system memory segments during the boot to enable a second ECC region of the memory sub-system.

Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command intended for a first memory rank (RNK1) from the plurality of memory ranks (RNK1 - RNKM), wherein the write command corresponds to an LPDDR5 standard and is not intended for a second memory rank (RNK2) from the plurality of memory ranks (RNK1 - RNKM); Activating a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in the second memory rank (RNK2); Receiving a data strobe signal pair (WCK_T, WCK_C); Activating (S200) on-die terminal, ODT, circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; Receiving data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the activation of the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2); Receiving a read instruction intended for the first memory rank (RNK1), where the read instruction conforms to the LPDDR5 standard and is not intended for the second memory rank (RNK2); Enabling the transfer driver (710, DR1) in the first memory rank (RNK1); Disable the receive buffer (720, BF1) in the first memory rank (RNK1); Disable the receive buffer (720, BF2) and the transmit driver (710, DR2) in the second memory rank (RNK2); Disable (S300) the ODT circuit (300) of the first memory rank (RNK1) and enable the ODT circuit (300) of the second memory rank (RNK2) in response to the read command; and Sending data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the disabling of the ODT circuit of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2).

To provide a double data rate circuit that implements precise duty cycle control, and a data generation method.SOLUTION: A data generation method is performed by a double data rate circuit including a clock generator, a clock divider, and a multiplexer. The clock generator receives a source clock signal for generating a pair of complementary clock signals, and the clock divider is coupled to the clock generator and generates four multi-phase clock signals that are sequentially out of phase by 90° using only single edge transitions of the pair of complementary clock signals. The multiplexer is coupled to the clock divider and multiplexes multiple data bits into an output data stream by sequentially selecting each data bit of the multiple data bits at each of first and second edge transitions of two of the four multi-phase clock signals, cancelling the selection, and making each selected data bit into the output data stream.SELECTED DRAWING: Figure 8

Approaches presented herein provide for the reduction of workload bottlenecks during processing by offloading workload data to available data processing unit (DPU) memory, such as from graphics processing unit (GPU) memory or central processing unit (CPU) memory. Interfaces may be used to store the workload data to the pool of DPU memory, such as double data rate (DDR) memory, on-board non-volatile memory express (NVMe) devices, or NVMe devices over fabric. Interfaces may also be used to retrieve identified workload data required to complete a workload. The retrieved workload data may be provided to the GPU where the workload is completed. The pool of DPU memory may orchestrate transfers of the workload data. The workload data may be offloaded to the pool of DPU memory for training of a machine learning model. The workload data offloaded to the pool of DPU memory for training of a machine learning model may include model states, activation functions, or model checkpoints.

The invention relates to a cache unit error replacement optimization method and storage equipment, and belongs to the technical field of storage. The method comprises the steps that if it is detected that SBE occurs in a cache unit of the storage device, an SBE address is obtained; responding to the condition that the SBE address is in the FTL interval, and calculating an error FTL address according to the SBE address and the FTL initial address; according to the error FTL address, moving data of the SBE address to a reserved area; wherein the cache unit comprises an FTL table storage area and a reserved area. According to the embodiment of the invention, the DDR can be prevented from being further developed into the DBE (Double Bit Error) after the SBE appears.

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

An information handling system, comprising of a BMC, an I / O device, and a BIOS. The BIOS is configured to perform an I / O health check of the I / O device of the information handling system, gather I / O health check data from the I / O health check performed, and determine a health status of the information handling system according to a set of criteria and based on the I / O health check data.

A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

Content transparency control implemented on a central processing unit, or a graphics processing unit to post-process live video content requires direct access to double data rate memory and can demand significant amounts of power. A solution addresses this issue by exploiting temporal noise reduction hardware and software already included in an image signal processor. The temporal noise reduction hardware and software are modified to support content transparency control in tandem with temporal noise reduction. Specifically, the feedback weight map and the output weight map used in temporal noise reduction to blend an input image and a retrieved reference image can be controlled based on a semantic map to effectuate content transparency control.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

To provide a memory device and a system that provide high speed access to a memory in higher temperature applications.SOLUTION: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; and for each received command, determining if the command is an express read (NVR) command, determining if a next consecutive command is a NVR command, in which consecutive NVR commands form a NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock.SELECTED DRAWING: Figure 16

Systems and methods for low-power double data rate (LPDDR) compatible High Bandwidth NAND (HBN) include receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via a memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via a memory controller to fulfill the request.

The embodiment of the invention provides a low-power-consumption double-data-rate random access memory power supply circuit and a personal computer, relates to the technical field of power supply circuits, and can reduce the power consumption of a computer, relieve the heat accumulation problem and prolong the endurance time. And meanwhile, miniaturization and light weight of a computer are facilitated. The low-power-consumption double-data-rate random access memory power supply circuit comprises a step-down chip, wherein the step-down chip comprises a power input pin, a power output pin, a power bias pin and a feedback pin. And the first end of the bootstrap capacitor is connected to the power supply bias pin, and the second end of the bootstrap capacitor is connected to the power supply output pin. The first end of the energy storage inductor is connected to the power output pin, and the second end of the energy storage inductor is connected with the power input end of the at least one low-power-consumption double-data-rate random access memory and supplies power to the low-power-consumption double-data-rate random access memory. And the feedback voltage acquisition sub-circuit is used for providing feedback voltage for the feedback pin according to the voltage of the second end of the energy storage inductor.

A computing system including: a processing device; a main memory; a memory bus (e.g., a double date rate (DDR) bus) coupled between the processing device and the main memory; a random access memory; and a compute express link (CXL) fabric coupled between the processing device and the random access memory. The system is configured to identify a ratio, using a reinforcement learning technique, to manage distribution of memory usage across the main memory and the random access memory. For example, the system can measure performance metrics of the computing system as a result of the managing according to the ratio, and update, based on the performance metrics, a reward model configured to identify a ratio for a given state of the computing system to manage memory for maximized reward.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The invention discloses an improved circuit design method for DDR type dynamic memory write training, and relates to the technical field of semiconductor memories. The method comprises the following steps: integrating a counter and a data comparison module in a dynamic memory particle to realize real-time comparison and correct frequency statistics of training data. The writing training score is comprehensively calculated by dynamically setting the length of a writing training sequence and based on the success rate of multiple times of training and the time consumption of single time of training in a historical statistical window. And carrying out iterative optimization on the write training sequence length by adopting a directional search strategy so as to obtain the optimal sequence length for balancing the training precision and speed. And finally, solidifying the optimal sequence length into a counting final value of a counter, and generating a write training circuit with self-adaptive capability in combination with a continuous comparison data comparison module. According to the circuit design method, the optimal training performance can be automatically maintained under different working conditions, and the initialization speed and the operation stability of a memory system are effectively improved.

The described technology provides a multi-level error correction method including encoding data received from a dual data rate (DDR) memory by performing primary encoding to generate transition symbols, where the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction dual error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including a Code 1 parity generated from the transition symbol and a Code 2 parity generated from the transition symbol and metadata stored on the DDR memory, where the secondary encoding includes Reed-Solomon (RS) encoding, and saving the inner code on a parity storage location on a die of the DDR memory.

The invention provides a CSI (Channel State Information) abnormal overflow method and system automatically controlled by hardware, the method is applied to a CSI subsystem, and the method comprises the following steps: receiving input image data; the input image data comprises a frame start signal; packaging the image data according to a preset format, and caching the packaged image data to a line storage unit built in the CSI subsystem; under the control of a pre-configured state machine in the CSI subsystem, transmitting the packaged image data in the row storage unit through a bus and writing the image data into a DDR (Double Data Rate) of a host; when the bus is blocked, the state machine enters and maintains a waiting state within a preset tolerance duration, and stops reading the packaged image data from the built-in row storage unit; therefore, the storage overflow exception processing of the CSI subsystem at a hardware level is realized, the burden of system software is reduced, the recovery time is controlled, and the image transmission effect is ensured.

Embodiments disclosed herein include an apparatus that includes a package substrate, with a core. In an embodiment, a first die is on the package substrate, and the first die includes a first double data rate (DDR) physical layer and a second DDR physical layer. In an embodiment, a second die is on the package substrate, and a bridge is in a cavity of the core of the package substrate. In an embodiment, the first DDR physical layer is coupled to the second die by a first trace within the bridge, and the second DDR physical layer is coupled to the second die by a second trace within a buildup layer over the core.

A device, system, and method are disclosed for processing-in-memory (PIM) compression. In an embodiment, a method includes obtaining, by an input / output sense amplifier (IOSA) from an associated RAM bank, compressed data; sending, by the IOSA, the compressed data divided into a plurality of portions; receiving, by a respective decompressor of a plurality of decompressors of a PIM block associated with the RAM bank, a respective portion of the compressed data; decompressing, by the respective decompressor, the respective portion of the compressed data to obtain a respective portion of decompressed data; and sending, by the respective decompressor, the respective portion of the decompressed data to a respective Arithmetic Logic Unit (ALU) of a plurality of ALUs of the PIM block for processing.

Embodiments of the present application provide a method and apparatus for correcting a block of a solid-state drive, an electronic device, and a storage medium. The method includes: after powering up the SSD, obtaining a first physical address in a latest mapping relationship recorded by a super block of a double data rate (DDR); querying a second physical address corresponding to an open block in a single layer cell (SLC) block info table of the DDR; and replacing the second physical address of the open block in the SLC block info table with the first physical address. The open block in the SLC block info table is corrected; correctness of the open block in the SLC block info table of the DDR after the SSD is powered up is ensured; and stability of operation of an SSD system is improved.

The invention provides a method and a device for detecting the reliability of an FPGA (Field Programmable Gate Array) memory. The method comprises the following steps: in an equipment starting stage, controlling the memory of each DDR (Double Data Rate) controller of an FPGA (Field Programmable Gate Array) to be subjected to multiple random address read-write tests; and after the starting of the equipment is completed, a simulation service message is sent to the FPGA in the front stage of running the service, and functional verification is carried out on a memory block to be used by the service through the simulation service message. Through the staged and randomized detection strategy, the problems that in the prior art, test coverage is incomplete, efficiency is low, and the reliability of the memory before service operation cannot be guaranteed are solved, and the accuracy and practicability of FPGA memory detection are remarkably improved.

A decision feedback equalizer for double data rate memory is shown, which uses a sampling circuit and an adder circuit with parallel-to-serial conversion. The sampling circuit separates the sampling of a sampling object into even bits and odd bits, to output even-bit data on an even-bit channel, and to output odd-bit data on an odd-bit channel. The adder circuit with parallel-to-serial conversion is coupled to the sampling circuit to receive the even-bit data and the odd-bit data, and to combine the even-bit data with the odd-bit data to generate full-rate data.

The application discloses a printed circuit board quality inspection method, device, equipment, medium and product, relates to the double data rate hardware design technical field, and comprises the following steps: automatically analyzing a design file to replace manual sampling inspection, realizing batch and rapid signal line and target connecting piece identification, and improving detection efficiency; after extracting signal line information and identifying the target connecting piece, obtaining design parameters thereof and performing full-parameter verification based on a reference rule, so that key parameters are ensured not to be missed; automatically performing design file analysis, parameter extraction and rule judgment throughout the whole process, so that missing problems caused by fatigue and negligence during manual one-by-one auditing can be avoided; and through automatic comparison of the target connecting piece design parameters and the reference rule, efficient and accurate comparison is realized, manual comparison is replaced, and the result accuracy is ensured.

The invention relates to the technical field of data transmission mechanisms, in particular to an ISAR (inverse synthetic aperture radar) imaging multi-channel data high-bandwidth dual-mode transmission system based on an FPGA (field programmable gate array). The ISAR imaging multi-channel data high-bandwidth dual-mode transmission system is oriented to a plurality of independently configured data transmission channels, and each data transmission channel works cooperatively with a DDR (double data rate) data processing module A and a DDR data processing module B through a data channel selection module. A multi-channel data transmission function is realized on an FPGA platform, and the requirements of high-real-time signal processing applications such as ISAR imaging and the like on continuous high-bandwidth data transmission are met; two groups of independent DDR data processing modules A and B are adopted, the DDR data processing modules A and B correspond to independent data paths and control logics, one of the DDR data processing modules A and B executes data writing or original sequence reading operation, and the other one of the DDR data processing modules A and B executes transposition reading or other read-write operation in a clock period, so that the data processing efficiency is improved. Therefore, double-channel concurrent access is achieved, and read-write conflicts and pipeline blocking in a traditional single-channel architecture are eliminated.

The application provides a data processing method and device, electronic equipment and storage medium, and belongs to the technical field of data storage security. The method comprises the following steps: receiving key information, including a first key and a second key; receiving a key update instruction, and sending the key information to a cipher core of a data encryption and decryption unit based on the key update instruction; obtaining address channel information and data information; determining to-be-encrypted data or to-be-decrypted data according to the address channel information; generating an adjustment value based on the first key, and encrypting or decrypting the to-be-encrypted data or the to-be-decrypted data based on the second key and the adjustment value; transmitting the data information after encryption processing to an advanced extensible interface (AXI) of a double data rate (DDR) memory and writing the data information into the DDR memory; or transmitting the data information read from the DDR memory to the cipher core for decryption processing. The application realizes efficient encryption and decryption of data in the process of interaction with the DDR memory, and improves the system scalability.

The invention discloses a five-layer DDR (Double Data Rate) chip stacking and packaging method, which comprises the following steps of S1, selecting six layers of substrates, and stacking five chips in a staggered manner; s2, connecting each chip to a substrate L1 through a bonding wire in a left-right routing manner, arranging inter-board wires between the substrates, and connecting the inter-board wires with solder balls to form a fan-out path of a signal; s3, a terminating resistor is arranged on the substrate L1, and the terminating resistor is connected with the inter-board wiring; the chips on the upper three layers are subjected to address signal interconnection through left side routing, the chips on the lower two layers are subjected to corresponding address signal interconnection through right side routing, and a solder ball-terminating resistor-five-chip topological structure is formed; and S4, carrying out plastic packaging, and completing stacking packaging. Interconnection and fan-out of a signal and a power supply are realized through staggered stacking of multiple layers of chips, fixed stacking of the adhesive and connection of the bonding wires; and a terminating resistor is also added for optimizing signal quality and improving signal transmission quality.

A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a discrete nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; for each received command, determining if the command is an express read (NVR) command, if a command is determined to be an NVR command, determining if a next consecutive command is an NVR command, wherein consecutive NVR commands form an NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells of the NVM device; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock; wherein the CA bus input includes a plurality of parallel CA signal inputs. Related memory devices and systems are also disclosed.

The invention provides a system for realizing high-speed data acquisition and a high-precision signal source based on FPGA (Field Programmable Gate Array) integration. The invention aims to integrate a plurality of functional modules such as a high-speed ADC interface, real-time data processing, high-precision DAC control and complex waveform generation into a single chip through the high programmability and parallel processing capability of the FPGA, so that the miniaturization of the system is realized, and the real-time performance of data processing, the multi-channel synchronization precision and the flexibility of signal generation are remarkably improved. The core of the embodiment of the invention is that an FPGA (Field Programmable Gate Array) chip is used as a master control and data processing center, and a high-speed ADC (Analog to Digital Converter) chip, a high-precision DAC (Digital to Analog Converter) chip, a clock circuit, an external memory (such as DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory)) and necessary interface circuits (such as gigabit Ethernet, SFP (Small Form-factor Pluggable) + optical ports and the like) are peripherally connected to form a highly integrated hardware platform.

The application relates to a temperature difference compensation-based detector training method and relates to the technical field of CMOS detector training application, and solves the problems that, in the prior art, a long time is needed from the start of power-on of a detector to the temperature of a camera detector reaching thermal equilibrium and remaining unchanged, the camera efficiency is seriously affected, and the detected jump edge position in the bit correction process does not conform to the actual state, so that the sampling position is not the optimal position, and the like. Firstly, the temperature difference value at the working steady state and the initial working time and the detected jump edge corresponding delay tap value difference are measured, and then the corresponding tap value difference is compensated into the correction formula in the measurement process. In addition, for the application based on a double data rate input register IDDR, the sampling clock edge switching and the judgment of the number of detected jump edges are optimized.