171 results about "Double data rate" patented technology

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

A memory module has pads on the top and bottom surfaces of a module printed circuit board (PCB). The pads match the pin layout of one or more memory devices to be mounted on the memory module. The pads on one surface of the PCB electrically interconnect to the memory device(s), and the pads on the other surface electrically interconnect to pads on a system board, such as a motherboard. With the pad layout on the memory module, the pad layout of the system board can be the same for a memory-down implementation and for a removable memory module. The pad layout provides good signal-to-noise performance and can enable a memory module for low power double data rate (LPDDR) memory, double data rate (DDR) memory, and graphics double data rate (GDDR) memory.

The invention relates to memory error correction, in particular to an ECC check single-bit error correction system in a DDR (Double Data Rate), which comprises a DRAM (Dynamic Random Access Memory) scanner, periodically performs address read traversal operation on a DDR particle DRAM, timely finds a single-bit error of data in the DDR particle DRAM by inquiring an ECC check state in a DDR controller DDRC, and performs correction processing on the single-bit error, so that the error correction efficiency is improved. The error is prevented from being evolved into an uncorrectable multi-bit error; the DDR controller DDRC is used for converting the AXI interface signal into a corresponding DFI interface signal, outputting the DFI interface signal to a DDR physical layer DDR PHY, carrying out ECC verification on read-write data, and storing an ECC verification result to a register, so that a DRAM scanner inquires an ECC verification state; according to the technical scheme, the defects that in the prior art, the processing speed is low, data errors are not found in time, and more CPU resources are occupied can be effectively overcome.

The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input / output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.

Embodiments of the present application provide a memory system, a method and apparatus for adjusting memory resources, an electronic device, and a non-transitory readable storage medium. The memory system includes a first motherboard, and a processor and a high-speed interconnection channel interface that are integrated on the first motherboard; a first adapter board, and a high-speed interconnection channel interface, a chip and a memory module that are integrated on the first adapter board; and at least one connecting cable; the at least one connecting cable is used to establish a physical link between the high-speed interconnection channel interface of the first motherboard and the high-speed interconnection channel interface of the first adapter board, and used to convert the high-speed channel interconnection signal into a processor internal dedicated bus signal transmitted by a physical link based on a peripheral component interconnect express; and the chip of the first adapter board is used to acquire the converted processor internal dedicated bus signal, and convert the processor internal dedicated bus signal into a double data rate memory signal. By the connecting cable, the high-speed channel interconnection signals are converted into IPB resources to expand DRAM resources.

Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

A memory controller includes a first storage circuit which stores trained center eyes for a dual data rate (DDR) interface, each trained center eye including a corresponding trained delay value, and a second storage circuit which stores boundary points for the DDR interface. The memory controller includes test circuitry which halts normal operation and uses a corresponding trained delay value of a trained center eye for a first bit lane of the DDR interface as a starting delay value in performing a search for a first boundary point of a data eye margin by repeatedly adjusting a delay between a data signal (DQS) of the first bit lane and a corresponding data strobe signal (DQS) and performing a test with each adjusted delay. The test circuity stores the first boundary point in the second storage circuit, restores the delay back to the corresponding trained delay value, and resumes normal operation.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

A memory module includes a printed circuit board and a Low-Power Double Data Rate (LPDDR) memory device. The printed circuit board includes surface contact connections on a first surface of the printed circuit board and located at a first portion of the printed circuit board. The LPDDR memory device is on a second surface of the printed circuit board and located at a second portion of the printed circuit board. The LPDDR memory device is configured to be coupled to an information handling system via the surface contact connections. The second portion of the printed circuit board is adjacent to the first portion of the printed circuit board.

The application discloses a kind of static current control systems of double data rate linear voltage regulator, including reference generating circuit and by feedback control circuit, error amplifier circuit and power output circuit constitute idle power consumption control circuit, reference voltage VREF generated by reference generating circuit is exported to feedback control circuit, after feedback control circuit compares the control signal output by error amplifier circuit, exports to error amplifier circuit to make the control signal output by error amplifier circuit also change, the control signal in turn controls upper and lower power tube in power output circuit, by adjusting VREF generated by reference generating circuit, to flexibly adjust system idle power consumption, while considering low power consumption and the fast transient response of load switching.

A method for memory system initialization to bootstrap error correction code (ECC) regions during system boot is described. The method includes partitioning a memory sub-system into sub-system memory segments. The method also includes using a last level cache coprocessor (LCP) to initialize a first of the sub-system memory segments to provide a first ECC region. The method also includes booting a system through the first ECC region of the memory sub-system. The method also includes using the LCP to initialize remaining ones of the sub-system memory segments during the boot to enable a second ECC region of the memory sub-system.

Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command intended for a first memory rank (RNK1) from the plurality of memory ranks (RNK1 - RNKM), wherein the write command corresponds to an LPDDR5 standard and is not intended for a second memory rank (RNK2) from the plurality of memory ranks (RNK1 - RNKM); Activating a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in the second memory rank (RNK2); Receiving a data strobe signal pair (WCK_T, WCK_C); Activating (S200) on-die terminal, ODT, circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; Receiving data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the activation of the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2); Receiving a read instruction intended for the first memory rank (RNK1), where the read instruction conforms to the LPDDR5 standard and is not intended for the second memory rank (RNK2); Enabling the transfer driver (710, DR1) in the first memory rank (RNK1); Disable the receive buffer (720, BF1) in the first memory rank (RNK1); Disable the receive buffer (720, BF2) and the transmit driver (710, DR2) in the second memory rank (RNK2); Disable (S300) the ODT circuit (300) of the first memory rank (RNK1) and enable the ODT circuit (300) of the second memory rank (RNK2) in response to the read command; and Sending data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the disabling of the ODT circuit of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2).

To provide a double data rate circuit that implements precise duty cycle control, and a data generation method.SOLUTION: A data generation method is performed by a double data rate circuit including a clock generator, a clock divider, and a multiplexer. The clock generator receives a source clock signal for generating a pair of complementary clock signals, and the clock divider is coupled to the clock generator and generates four multi-phase clock signals that are sequentially out of phase by 90° using only single edge transitions of the pair of complementary clock signals. The multiplexer is coupled to the clock divider and multiplexes multiple data bits into an output data stream by sequentially selecting each data bit of the multiple data bits at each of first and second edge transitions of two of the four multi-phase clock signals, cancelling the selection, and making each selected data bit into the output data stream.SELECTED DRAWING: Figure 8

Approaches presented herein provide for the reduction of workload bottlenecks during processing by offloading workload data to available data processing unit (DPU) memory, such as from graphics processing unit (GPU) memory or central processing unit (CPU) memory. Interfaces may be used to store the workload data to the pool of DPU memory, such as double data rate (DDR) memory, on-board non-volatile memory express (NVMe) devices, or NVMe devices over fabric. Interfaces may also be used to retrieve identified workload data required to complete a workload. The retrieved workload data may be provided to the GPU where the workload is completed. The pool of DPU memory may orchestrate transfers of the workload data. The workload data may be offloaded to the pool of DPU memory for training of a machine learning model. The workload data offloaded to the pool of DPU memory for training of a machine learning model may include model states, activation functions, or model checkpoints.

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

The invention relates to a cache unit error replacement optimization method and storage equipment, and belongs to the technical field of storage. The method comprises the steps that if it is detected that SBE occurs in a cache unit of the storage device, an SBE address is obtained; responding to the condition that the SBE address is in the FTL interval, and calculating an error FTL address according to the SBE address and the FTL initial address; according to the error FTL address, moving data of the SBE address to a reserved area; wherein the cache unit comprises an FTL table storage area and a reserved area. According to the embodiment of the invention, the DDR can be prevented from being further developed into the DBE (Double Bit Error) after the SBE appears.

The invention provides a mobile equipment resource scheduling method for optimizing I / O (Input / Output) performance, which comprises the following steps of: executing CPU (Central Processing Unit) and DDR (Double Data Rate) frequency scheduling actions by adopting an original strategy gradient algorithm through a reinforcement learning model for executing a mobile equipment resource scheduling decision; the mobile equipment system state monitoring and resource scheduling control framework is used for starting a reinforcement learning model to schedule resources when the system I / O load pressure is high; according to the online training framework of the reinforcement learning model on the mobile equipment, the reinforcement learning model is trained online, so that the reinforcement learning model can quickly cope with a new load scene. According to the mobile equipment resource scheduling method, resource scheduling decision making is carried out based on a data-driven reinforcement learning model, and sampling and exploration overhead of a traditional resource scheduling strategy is eliminated; accurate resource scheduling decisions can be made according to system states and application resource requirements, and the problems of low flexibility and low accuracy of previous work are avoided.

The invention relates to the technical field of power transmission line defect detection, in particular to a power transmission line defect detection method and system based on a storage and calculation integrated framework and a chip. The system comprises a CPU (Central Processing Unit), a reasoning unit containing an SRAM (Static Random Access Memory) memory array, a DDR (Double Data Rate), an input interface and an The SRAM storage and calculation array comprises a plurality of SRAM storage and calculation units, each SRAM storage and calculation unit comprises an SRAM storage unit, a data conversion unit and an exclusive or addition calculation unit, and the DDR stores weight data of the pre-training neural network model. The CPU obtains a power transmission line monitoring image based on the input interface, obtains sparse data through gradient entropy-based adaptive sparse coding, and transmits the sparse data to the reasoning unit. And the reasoning unit performs image feature recognition on sparse data by using the model to obtain a multi-dimensional feature map, and then judges defect types by using Euclidean distance classification. During feature recognition, neuron calculation is realized through exclusive or addition calculation based on an SRAM memory array. Therefore, the data processing complexity and power consumption are reduced, and the accuracy and real-time performance of defect detection of the power transmission line are improved.

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

The invention provides a memory access control chip, a data memory access method and a data memory access system, and relates to the technical field of computers, in particular to the technical field of chips. The memory access control chip comprises m first controllers and k second controllers, the m first controllers and the k second controllers are connected through an interconnection bus, and m and k are respectively positive integers; wherein the first controller is used for converting a received data access request into an access request conforming to a double data rate (DDR) interface protocol, and sending the access request to a connected DDR through a first interface; and the second controller is used for receiving a data access request sent by the CXL chip through the second interface, determining a target controller according to the configuration information and a target access address in the data access request, and sending the data access request to the target controller through the interconnection bus. The data access method can be realized through an access control chip, and the data access system comprises the access control chip.

A reconfigurable driver in an I / O circuit has a first transistor provided in a first pullup structure, a second transistor provided in a second pullup structure, and a control circuit that generates a control signal provided to a gate of the second transistor. A gate of the first transistor receives a data signal. The control signal is an inverted, delayed version of the data signal in a first mode. The control signal turns off the second transistor in a second mode. The control circuit generates the control signal using a version of the data signal when operated in a third mode. The second pullup structure may be used to provide one-shot equalization to an output of the reconfigurable driver when the second pullup structure is operated in the first mode. The second transistor may be a thin-oxide PMOS transistor. The first transistor may be a thin-oxide NMOS transistor.

An information handling system, comprising of a BMC, an I / O device, and a BIOS. The BIOS is configured to perform an I / O health check of the I / O device of the information handling system, gather I / O health check data from the I / O health check performed, and determine a health status of the information handling system according to a set of criteria and based on the I / O health check data.

A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

Content transparency control implemented on a central processing unit, or a graphics processing unit to post-process live video content requires direct access to double data rate memory and can demand significant amounts of power. A solution addresses this issue by exploiting temporal noise reduction hardware and software already included in an image signal processor. The temporal noise reduction hardware and software are modified to support content transparency control in tandem with temporal noise reduction. Specifically, the feedback weight map and the output weight map used in temporal noise reduction to blend an input image and a retrieved reference image can be controlled based on a semantic map to effectuate content transparency control.

Apparatuses, systems, and methods for access operations during a voltage transition. A memory may receive a system voltage and a clock signal from a controller. The controller may be used to time operations such as write operations however, an internal clock signal of the memory may be dependent on the voltage. The memory operates at a double data rate relative to the clock signal. During a transition period while the voltage changes between levels, the memory may switch to a transition mode where the memory operates at a single data rate.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.

To provide a memory device and a system that provide high speed access to a memory in higher temperature applications.SOLUTION: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; and for each received command, determining if the command is an express read (NVR) command, determining if a next consecutive command is a NVR command, in which consecutive NVR commands form a NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock.SELECTED DRAWING: Figure 16

The invention discloses a DDR (Double Data Rate) subsystem read-write self-checking method and a DDR subsystem read-write self-checking device based on an AXI4-Lite protocol. The method comprises the steps of starting; configuring a write address configuration register group, a write data configuration register group and a read address configuration register group; sending a write-in address; writing data; sending a read address; reading out data; the read-out data and the write-in data are compared, and function verification of the DDR subsystem is completed through a comparison result; and ending. On the basis of verifying the correctness of the read-write function of the DDR subsystem, the verification of the correctness of the interface protocol is realized, so that the comprehensive verification of the correctness of the function of the DDR subsystem is realized.

Systems and methods for low-power double data rate (LPDDR) compatible High Bandwidth NAND (HBN) include receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via a memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via a memory controller to fulfill the request.