133 results about "Double data rate" patented technology

The invention discloses a cluster model acceleration method and device based on an FPGA, and relates to the technical field of model acceleration, and the method comprises the steps: converting a cluster simulation model into a digital circuit structure file, and burning the digital circuit structure file into an FPGA board card; splitting the digital circuit structure file into a plurality of independent calculation modules according to functions; packaging the calculation module into a plurality of IP cores based on the requirements of different individuals in the cluster; in response to input data received in the DDR of the FPGA board card, the hardware state machine triggers all the IP cores to execute corresponding tasks in parallel, and the calculation process of each IP core is controlled by taking a main clock of the FPGA board card as a reference; and each IP core writes the task processing result into a DDR (Double Data Rate) of the FPGA board card, and reads the DDR to obtain a simulation result of the cluster simulation model. The technical problems that an existing model acceleration method is poor in real-time performance and high in economic cost in a large-scale cluster simulation scene are solved, and therefore in the large-scale cluster simulation scene, high real-time performance of simulation can be guaranteed, and the economic cost can be effectively reduced.

The present disclosure belongs to the technical field of storage chip designs. Disclosed are a memory module and an electronic device. The memory module includes at least two memory expander controller (MXC) chips, a peripheral component Interconnect express (PCIe) golden finger, a multichannel input / output (MCIO) connector, and a dual inline memory module (DIMM), wherein the MXC chips are connected to the DIMM through a double data rate 5 (DDR5) synchronous dynamic random access memory (DRAM) interface controller port, a compute express link (CXL) port of at least one of the MXC chips interacts with an external device through the PCIe golden finger, and the CXL port of at least one of the MXC chips interacts with the external device through the MCIO connector. The present disclosure may improve the memory capacity of the memory module.

A memory controller includes a first storage circuit which stores trained center eyes for a dual data rate (DDR) interface, each trained center eye including a corresponding trained delay value, and a second storage circuit which stores boundary points for the DDR interface. The memory controller includes test circuitry which halts normal operation and uses a corresponding trained delay value of a trained center eye for a first bit lane of the DDR interface as a starting delay value in performing a search for a first boundary point of a data eye margin by repeatedly adjusting a delay between a data signal (DQS) of the first bit lane and a corresponding data strobe signal (DQS) and performing a test with each adjusted delay. The test circuity stores the first boundary point in the second storage circuit, restores the delay back to the corresponding trained delay value, and resumes normal operation.

A dual-mode transmitter for a low-power double-data rate (LPDDR) interface can be operated in one of a non-return to zero (NRZ) mode and a pulse amplitude modulation (PAM)-4 mode. The dual-mode transmitter includes: a pseudorandom binary sequence (PRBS) generator configured to generate a transmission signal to be transmitted to a dual-mode receiver; at least one serializer configured to serialize the transmission signal; a single-ended to differential (S2D) configured to convert the serialized transmission signal in a form of a single-ended signal into a differential signal; a ZQ calibration configured to generate a result code for matching an impedance value at an output terminal of the dual-mode transmitter with a terminating resistance value of the dual-mode receiver; and a pre-driver configured to combine the differential signal obtained by the converting and the result code.

A memory module includes a printed circuit board and a Low-Power Double Data Rate (LPDDR) memory device. The printed circuit board includes surface contact connections on a first surface of the printed circuit board and located at a first portion of the printed circuit board. The LPDDR memory device is on a second surface of the printed circuit board and located at a second portion of the printed circuit board. The LPDDR memory device is configured to be coupled to an information handling system via the surface contact connections. The second portion of the printed circuit board is adjacent to the first portion of the printed circuit board.

The application discloses a kind of static current control systems of double data rate linear voltage regulator, including reference generating circuit and by feedback control circuit, error amplifier circuit and power output circuit constitute idle power consumption control circuit, reference voltage VREF generated by reference generating circuit is exported to feedback control circuit, after feedback control circuit compares the control signal output by error amplifier circuit, exports to error amplifier circuit to make the control signal output by error amplifier circuit also change, the control signal in turn controls upper and lower power tube in power output circuit, by adjusting VREF generated by reference generating circuit, to flexibly adjust system idle power consumption, while considering low power consumption and the fast transient response of load switching.

A method for memory system initialization to bootstrap error correction code (ECC) regions during system boot is described. The method includes partitioning a memory sub-system into sub-system memory segments. The method also includes using a last level cache coprocessor (LCP) to initialize a first of the sub-system memory segments to provide a first ECC region. The method also includes booting a system through the first ECC region of the memory sub-system. The method also includes using the LCP to initialize remaining ones of the sub-system memory segments during the boot to enable a second ECC region of the memory sub-system.

Method for operating a dynamic low-power double data rate 5 direct access memory, LPDDR5 DRAM, in a multi-rank memory system (10) which includes a plurality of memory ranks (RNK1 - RNKM), wherein the method includes the following steps: Receiving a write command intended for a first memory rank (RNK1) from the plurality of memory ranks (RNK1 - RNKM), wherein the write command corresponds to an LPDDR5 standard and is not intended for a second memory rank (RNK2) from the plurality of memory ranks (RNK1 - RNKM); Activating a receive buffer (720, BF1) in the first memory rank (RNK1); Disabling a transfer driver (710, DR1) in the first memory rank (RNK1); Disabling a receive buffer (720, BF2) and a transmit driver (710, DR2) in the second memory rank (RNK2); Receiving a data strobe signal pair (WCK_T, WCK_C); Activating (S200) on-die terminal, ODT, circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2) in response to the write command; Receiving data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the activation of the ODT circuits (300) of the first memory rank (RNK1) and the second memory rank (RNK2); Receiving a read instruction intended for the first memory rank (RNK1), where the read instruction conforms to the LPDDR5 standard and is not intended for the second memory rank (RNK2); Enabling the transfer driver (710, DR1) in the first memory rank (RNK1); Disable the receive buffer (720, BF1) in the first memory rank (RNK1); Disable the receive buffer (720, BF2) and the transmit driver (710, DR2) in the second memory rank (RNK2); Disable (S300) the ODT circuit (300) of the first memory rank (RNK1) and enable the ODT circuit (300) of the second memory rank (RNK2) in response to the read command; and Sending data signals while the data strobe signal pair (WCK_T, WCK_C) is toggled during the disabling of the ODT circuit of the first memory rank (RNK1) and the enabling of the ODT circuit (300) of the second memory rank (RNK2).

To provide a double data rate circuit that implements precise duty cycle control, and a data generation method.SOLUTION: A data generation method is performed by a double data rate circuit including a clock generator, a clock divider, and a multiplexer. The clock generator receives a source clock signal for generating a pair of complementary clock signals, and the clock divider is coupled to the clock generator and generates four multi-phase clock signals that are sequentially out of phase by 90° using only single edge transitions of the pair of complementary clock signals. The multiplexer is coupled to the clock divider and multiplexes multiple data bits into an output data stream by sequentially selecting each data bit of the multiple data bits at each of first and second edge transitions of two of the four multi-phase clock signals, cancelling the selection, and making each selected data bit into the output data stream.SELECTED DRAWING: Figure 8

Approaches presented herein provide for the reduction of workload bottlenecks during processing by offloading workload data to available data processing unit (DPU) memory, such as from graphics processing unit (GPU) memory or central processing unit (CPU) memory. Interfaces may be used to store the workload data to the pool of DPU memory, such as double data rate (DDR) memory, on-board non-volatile memory express (NVMe) devices, or NVMe devices over fabric. Interfaces may also be used to retrieve identified workload data required to complete a workload. The retrieved workload data may be provided to the GPU where the workload is completed. The pool of DPU memory may orchestrate transfers of the workload data. The workload data may be offloaded to the pool of DPU memory for training of a machine learning model. The workload data offloaded to the pool of DPU memory for training of a machine learning model may include model states, activation functions, or model checkpoints.

The application discloses a FIFO interface multi-channel DMA controller based on FPGA, which comprises an input data distribution module, an input data cache module, an output data distribution module, an output data cache module, a DMA scheduling module, a DDR output module and a DDR interface module; is used for caching multi-channel high-speed data of multiple data sources in a memory, does not occupy on-chip RAM resources of the FPGA, realizes parallel, independent and efficient storage and storage of multi-channel data, a data interaction interface is a standard FIFO interface, a user does not need to care about complex DDR3 / 4 (Double Data Rate) interface timing and multi-channel data scheduling, programming is realized by using a hardware description language, parameterization configuration is adopted, other FPGA platforms are compatible, the application can be called in FPGA design as an IP, a development cycle is shortened, and development efficiency is improved.

The invention relates to a cache unit error replacement optimization method and storage equipment, and belongs to the technical field of storage. The method comprises the steps that if it is detected that SBE occurs in a cache unit of the storage device, an SBE address is obtained; responding to the condition that the SBE address is in the FTL interval, and calculating an error FTL address according to the SBE address and the FTL initial address; according to the error FTL address, moving data of the SBE address to a reserved area; wherein the cache unit comprises an FTL table storage area and a reserved area. According to the embodiment of the invention, the DDR can be prevented from being further developed into the DBE (Double Bit Error) after the SBE appears.

The invention relates to the technical field of power transmission line defect detection, in particular to a power transmission line defect detection method and system based on a storage and calculation integrated framework and a chip. The system comprises a CPU (Central Processing Unit), a reasoning unit containing an SRAM (Static Random Access Memory) memory array, a DDR (Double Data Rate), an input interface and an The SRAM storage and calculation array comprises a plurality of SRAM storage and calculation units, each SRAM storage and calculation unit comprises an SRAM storage unit, a data conversion unit and an exclusive or addition calculation unit, and the DDR stores weight data of the pre-training neural network model. The CPU obtains a power transmission line monitoring image based on the input interface, obtains sparse data through gradient entropy-based adaptive sparse coding, and transmits the sparse data to the reasoning unit. And the reasoning unit performs image feature recognition on sparse data by using the model to obtain a multi-dimensional feature map, and then judges defect types by using Euclidean distance classification. During feature recognition, neuron calculation is realized through exclusive or addition calculation based on an SRAM memory array. Therefore, the data processing complexity and power consumption are reduced, and the accuracy and real-time performance of defect detection of the power transmission line are improved.

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

An information handling system, comprising of a BMC, an I / O device, and a BIOS. The BIOS is configured to perform an I / O health check of the I / O device of the information handling system, gather I / O health check data from the I / O health check performed, and determine a health status of the information handling system according to a set of criteria and based on the I / O health check data.

A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

Content transparency control implemented on a central processing unit, or a graphics processing unit to post-process live video content requires direct access to double data rate memory and can demand significant amounts of power. A solution addresses this issue by exploiting temporal noise reduction hardware and software already included in an image signal processor. The temporal noise reduction hardware and software are modified to support content transparency control in tandem with temporal noise reduction. Specifically, the feedback weight map and the output weight map used in temporal noise reduction to blend an input image and a retrieved reference image can be controlled based on a semantic map to effectuate content transparency control.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The described technology provides a multi-level error correction method, including encoding data received from a double data rate (DDR) memory by performing primary coding to generate transitional symbols, wherein the primary coding comprising at least one of cyclical redundancy check (CRC) encoding and single error correction double error detection (SECDED) encoding, performing a secondary coding on the transitional symbols to generate inner codes, the inner codes comprising code 1 parities generated from the transitional symbols and code 2 parities generated from the transitional symbols and metadata stored on the DDR memory, wherein the secondary coding comprising Reed Solomon (RS) encoding, and saving the inner codes on parity bit storage locations on a die of the DDR memory.

To provide a memory device and a system that provide high speed access to a memory in higher temperature applications.SOLUTION: A method can include: receiving a plurality of consecutive commands on a unidirectional command-address (CA) bus input of a nonvolatile memory (NVM) device, the commands being synchronous with a timing clock; and for each received command, determining if the command is an express read (NVR) command, determining if a next consecutive command is a NVR command, in which consecutive NVR commands form a NVR command sequence; in response to the no more than the NVR command sequence, accessing read data stored in NVM cells; and driving the read data on parallel data input / outputs (I / Os) of the NVM device in a burst of data values, the data values of the burst being output in synchronism with rising and falling edges of the timing clock.SELECTED DRAWING: Figure 16

Systems and methods for low-power double data rate (LPDDR) compatible High Bandwidth NAND (HBN) include receiving, from an application, a request associated with a memory device, the request being of a request type; issuing a first command to the memory device via a memory controller, the first command based on the request type; polling the memory device for a status of the memory device, the status associated with a readiness of the memory device for the request; determining that the memory device is ready based on the status; and issuing a second command to the memory device via a memory controller to fulfill the request.

Methods / structures for forming package structures are described. These methods / structures may include conductive pins, comprising: a cantilever beam portion physically coupled to a first side of the package substrate; a contact portion wherein terminal ends of the contact portion are physically and electrically coupled to the board; a housing structure including a housing cavity, wherein the contact portion is at least partially disposed within the housing cavity; and conductive material disposed on the housing side and / or near the surface of the housing cavity. The placement of the conductive material is optimized to meet the requirements of Double Data Rate (DDR) and / or Fast Peripheral Component Interface (PCIe) interfaces.

The embodiments of the present disclosure relate to a double data rate quad switching multi-bit digital to analog converter and a continuous time modulator. N -1 bit thermometer coded signal generates four 2 N -1 bit control signal. The DAC circuit has 2 N -1 unit DAC element, each unit DAC element consists of four 2 N - Four switching circuits controlled by the corresponding bit of the 1-bit control signal. N -1 unit DAC element output summed to generate the analog output signal. The four-element signal generator circuit generates four 2 N -1-bit control signal controls relative to 2 N - The time delay of the 1-bit thermometer coded signal applied to the clock signal and the time delay relative to the delayed clock signal applied to the 2 N The analog output signal is the feedback signal in the sigma-delta analog-to-digital converter circuit, which includes a multi-bit quantization circuit that operates to quantize the filter loop signal to generate a 2 N - 1-bit thermometer coded signal.

The invention discloses an impedance calibration circuit and calibration method applied to an HBM memory, and relates to the technical field of double data rate memory chips. According to the calibration method, on one hand, two times of calibration with opposite polarities are carried out on the PU resistor and the PD resistor, the offset voltage of the comparator circuit is eliminated, and the calibration accuracy is improved; on the other hand, the output result of the comparator circuit is voted, and the number of times that the comparator circuit outputs 0 and 1 in the voting period is judged, so that the final result output by the comparator circuit in the period is judged, the influence of signal noise and power supply fluctuation on the calibration result is eliminated, and the calibration accuracy is further improved. And the calibration accuracy can meet the rapid and high-precision calibration requirement of the HBM PHY.

The embodiment of the invention provides a low-power-consumption double-data-rate random access memory power supply circuit and a personal computer, relates to the technical field of power supply circuits, and can reduce the power consumption of a computer, relieve the heat accumulation problem and prolong the endurance time. And meanwhile, miniaturization and light weight of a computer are facilitated. The low-power-consumption double-data-rate random access memory power supply circuit comprises a step-down chip, wherein the step-down chip comprises a power input pin, a power output pin, a power bias pin and a feedback pin. And the first end of the bootstrap capacitor is connected to the power supply bias pin, and the second end of the bootstrap capacitor is connected to the power supply output pin. The first end of the energy storage inductor is connected to the power output pin, and the second end of the energy storage inductor is connected with the power input end of the at least one low-power-consumption double-data-rate random access memory and supplies power to the low-power-consumption double-data-rate random access memory. And the feedback voltage acquisition sub-circuit is used for providing feedback voltage for the feedback pin according to the voltage of the second end of the energy storage inductor.

The invention discloses a multi-type data high-speed interaction method based on Feiteng D2000 and an FPGA (Field Programmable Gate Array), which comprises the following steps of: acquiring the total number of FPGA chips on a PCI (Peripheral Component Interconnect) bus under an operating system directory, traversing all the FPGA chips to finish initialization, performing partition processing on DDR (Double Data Rate) mounted on each FPGA, performing address mapping on a Bar space, storing flag bit information related to uplink and downlink data, and storing the flag bit information related to the uplink and downlink data. The application program creates a thread polling Bar space flag bit to obtain a data updating state, the number and the position of unread data are obtained through calculation, and a driving function is called to read the data and forward the data. The data sending step comprises the steps of mapping according to a destination chip name to obtain an equipment descriptor, packaging a message header, judging whether to carry out zero filling operation or not to obtain final sending data, and subpackaging and calling a driving function to send the data according to an agreed fixed byte. Therefore, the purpose of multi-type data high-speed interaction between the Feiteng D2000 and the FPGA is achieved.

A computing system including: a processing device; a main memory; a memory bus (e.g., a double date rate (DDR) bus) coupled between the processing device and the main memory; a random access memory; and a compute express link (CXL) fabric coupled between the processing device and the random access memory. The system is configured to identify a ratio, using a reinforcement learning technique, to manage distribution of memory usage across the main memory and the random access memory. For example, the system can measure performance metrics of the computing system as a result of the managing according to the ratio, and update, based on the performance metrics, a reward model configured to identify a ratio for a given state of the computing system to manage memory for maximized reward.

A memory apparatus includes two independent subchannels of double data rate (DDR) memory. Each subchannel includes a number of memory banks, and an input / output (I / O) block having a number of meta data registers. The memory apparatus also includes a processing unit. The processing unit includes an arithmetic logic unit (ALU), an accumulator coupled to an output of the ALU, a controller coupled to the ALU, two multiplexers, each multiplexer coupling one subchannel to an ALU input, and coupling the accumulator to the ALU input, and two multiplexers / demultiplexers. Each multiplexer / demultiplexer is coupled between a memory bank, a corresponding I / O block, one of the two multiplexers, and the accumulator.

The invention discloses an improved circuit design method for DDR type dynamic memory write training, and relates to the technical field of semiconductor memories. The method comprises the following steps: integrating a counter and a data comparison module in a dynamic memory particle to realize real-time comparison and correct frequency statistics of training data. The writing training score is comprehensively calculated by dynamically setting the length of a writing training sequence and based on the success rate of multiple times of training and the time consumption of single time of training in a historical statistical window. And carrying out iterative optimization on the write training sequence length by adopting a directional search strategy so as to obtain the optimal sequence length for balancing the training precision and speed. And finally, solidifying the optimal sequence length into a counting final value of a counter, and generating a write training circuit with self-adaptive capability in combination with a continuous comparison data comparison module. According to the circuit design method, the optimal training performance can be automatically maintained under different working conditions, and the initialization speed and the operation stability of a memory system are effectively improved.

The described technology provides a multi-level error correction method including encoding data received from a dual data rate (DDR) memory by performing primary encoding to generate transition symbols, where the primary encoding includes at least one of cyclic redundancy check (CRC) encoding and single error correction dual error detection (SECDED) encoding; performing secondary encoding on the transition symbol to generate an inner code, the inner code including a Code 1 parity generated from the transition symbol and a Code 2 parity generated from the transition symbol and metadata stored on the DDR memory, where the secondary encoding includes Reed-Solomon (RS) encoding, and saving the inner code on a parity storage location on a die of the DDR memory.