13 results about "Universal asynchronous receiver/transmitter" patented technology

The invention relates to the technical field of Internet of Things, in particular to a circuit for simultaneously converting UART (Universal Asynchronous Receiver / Transmitter) to multi-path different level communication, which comprises a double-USB input module, a power supply processing module, a USB-UART core conversion module and a multi-path level conversion module, the double-USB input module comprises an MINI-USB interface J6 and a USB-B interface J8, VBUS pins of the two interfaces are connected in parallel through a Schottky diode and then output to the power supply processing module, and data differential pair pins are connected in parallel and then connected to the USB-UART core conversion module; and the power supply processing module comprises an LDO (Low Dropout Regulator) voltage stabilizing chip and a filter capacitor, and is used for converting 5V voltage output by the double-USB input module into 3.3 V stable voltage. The circuit design that the UART is connected with various different levels for communication is adopted, the tool integration technology is achieved, the design that the two USB ports are connected in parallel is adopted, the compatibility of the USB data line can be effectively improved, the demands of customers are met, and the technical difficulty that one UART bus is connected with multiple USB ports is broken through.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

A connected-vehicle interface module is provided that includes a connected-vehicle controller, a connected-vehicle radio for receiving an activation signal from a first vehicle warning system controller indicating a road condition, and a connected-vehicle interface controller. The connected-vehicle interface controller further includes a microcontroller and a plurality of universal asynchronous receiver transmitters for receiving and transmitting data communicated to the microcontroller through one or more wired connections to at least one of the connected-vehicle controller and the connected-vehicle radio, a memory device in communication with the microcontroller, and a transceiver and one or more communication ports, coupled to the microcontroller, for connection and communication with a connected vehicle road side unit, wherein the activation signal from the first vehicle warning system controller is communicated to the connected vehicle road side unit via the one or more communication ports.

The invention provides a serial port selection method, device and equipment and a readable storage medium, and is applied to a CPLD (Complex Programmable Logic Device) in UART (Universal Asynchronous Receiver / Transmitter). The method comprises the following steps: receiving a serial port selection instruction issued by an upper computer; the serial port selection instruction carries a baud rate corresponding to a target serial port, and a mapping relation between serial port numbers of optional serial ports and the baud rate is pre-stored in the CPLD; identifying a target serial port according to a serial port selection instruction issued by the upper computer, and connecting the target serial port with the UART path; and generating a corresponding sampling clock and sampling time according to the baud rate corresponding to the target serial port, and completing communication connection with the target serial port by using the sampling clock and the sampling time. According to the technical scheme, the flexibility of serial port switching and the debugging convenience are improved.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

The application relates to the technical field of communication, in particular to a device debugging method, a terminal device and an upper computer, the method is applied to a terminal device, the terminal device comprises an AP subsystem and an SP subsystem, the method comprises the following steps: when the SP subsystem detects that the AP subsystem is hung, switching a universal asynchronous receiver transmitter (UART) interface to a USB channel; the SP subsystem performs handshaking with the upper computer through the USB channel; the SP subsystem performs command interaction with the upper computer through the USB channel, so as to perform transmission of system data between the SP subsystem and the upper computer. The embodiment of the application realizes efficient and complete transmission of system data in the hung state.

A circuit can enable communication between a primary device and one or more secondary devices. This communication can use a Universal Asynchronous Receiver Transmitter (UART) protocol. During operation, the primary device may require information about the baud rate of the secondary device. The UART can operate in reverse polarity mode, and this reverse polarity can be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using reverse polarity mode to enter auto-baud detection mode can prevent excessive delays in UART communication and avoid the need for additional pins to implement the auto-baud detection mode.

The invention discloses a universal asynchronous receiver / transmitter (UART) digital logic simulation architecture system based on VerilogHDL. The system comprises a demand module, a test case TESTCASE module, an instruction model CMDMOD module and an asynchronous serial port model UARTMOD module. The UART digital logic simulation architecture based on VerilogHDL is established, the problems that an existing UART simulation architecture is single in application scene and needs to be continuously modified to be suitable for various application scenes of various items are solved, the UART simulation architecture is suitable for various application scenes of various items through parameter transmission and analysis, and the simulation verification efficiency of various application scenes of UART of various items is improved.

A first electronic device of an electronic system of includes a temperature sensor, a first universal asynchronous receiver / transmitter (UART) and a first processor. The temperature sensor is configured to sense a measured temperature value. The first processor is electrically connected to the first UART and the temperature sensor and is configured to set a first baud rate of the first UART as a baud rate setting value corresponding to the next-1-level temperature point based on the measured temperature value changing from a current temperature point to the next-1-level temperature point, and generate an adjustment signal. The second electronic device of the electronic system includes a second UART and a second processor. The second processor is electrically connected to the second UART and is configured to set a second baud rate of the second UART as the baud rate setting value according to the adjustment signal.

The invention belongs to the technical field of electronic communication and interfaces, and particularly discloses a multi-protocol interface switching device and method of an FPGA (Field Programmable Gate Array), and the FPGA is used for disconnecting all other interface channels from a first UART (Universal Asynchronous Receiver / Transmitter) signal receiving end when detecting that any interface channel in a serial communication interface circuit has a data start bit; activating an interface channel where a data start bit arrives, and setting the first GPIO as a high level; if the movable interface channel is a TTL interface channel in the serial communication interface circuit and the MCU needs to send reply data, when the MCU pulls up the second GPIO, the receiving end of the first UART signal is disconnected from the TTL interface channel, and the sending end of the first UART signal is connected to the TTL interface channel. According to the application, bus conflict and data loss possibly caused when data arrives at multiple interfaces at the same time are fundamentally avoided, and the reliability is greatly improved.

The utility model relates to a USB (Universal Serial Bus) to serial port isolation circuit, which comprises a PC (Personal Computer) USB interface circuit, a USB to serial port interface circuit, an isolation chip circuit and a target board UART (Universal Asynchronous Receiver / Transmitter) interface circuit, the isolation chip circuit at least comprises an isolation chip and is used for realizing electrical isolation between the computer and the target board; the input end of the PC USB interface circuit is connected with a computer, and the output end of the PC USB interface circuit is connected with the USB to serial port interface circuit; the output end of the USB to serial port interface circuit is connected with the isolation chip circuit; the output end of the isolation chip circuit is connected with the input end of the target board UART interface circuit; and the output end of the target board URAT interface circuit is connected with the target board. Through the UART interface used for assisting simulation debugging, data input and output channels are increased, the computer and the target board are electrically isolated through the isolation chip, damage of target equipment is effectively prevented from being transmitted to the computer, and the target equipment and the computer are protected.

The invention discloses an existing all-standard intercommunication system based on covered wire remote transmission and an application method, the system comprises an FPGA and analog front-end units matched with the FPGA, each analog front-end unit is provided with an independent covered wire, a power supply unit is composed of a DC / DC power supply chip and provides needed power supply voltage for the FPGA and the analog front-end units, a debugging module is also connected between the FPGA and the TDM; the SOC subsystem is configured to adopt an embedded kernel, and the embedded kernel is provided with a UART (Universal Asynchronous Receiver / Transmitter) serial port. The invention supports the covered wire remote transmission function of two paths of general TDM interfaces and supports the transmission capability of synchronous data.

The invention relates to a method for transmitting light setpoint data implemented in a control module comprising at least one Serial Peripheral Interface (SPI) capable of transmitting an SPI frame via a transmission port connected to a light module comprising a pixelated light source. The method comprises obtaining (601) a first set of light setpoint data and adapting (602) an SPI data frame. The adapted SPI data frame comprises a number of bits conforming to the SPI protocol, includes the first set of data, and is capable of being received and decoded by a receive port of a Universal Asynchronous Receiver Transmitter (UART). The adapted SPI data frame is transmitted (603) via the transmission port connected to the light module (FIG. 6).