97 results about "Universal asynchronous receiver/transmitter" patented technology

The invention relates to the technical field of real-time kernel performance testing of special chips, in particular to a special chip real-time performance evaluation method based on an FPGA (Field Programmable Gate Array), which comprises the following steps: (1) aiming at a real-time system on an ASIC (Application Specific Integrated Circuit) chip, setting an external interrupt source and an interrupt service program through a hardware interrupt controller; (2) two tasks with the same priority are created, scheduling of the tasks is achieved through time slice rotation, and a real dynamic load scene is simulated; (3) configuring an external FPGA (Field Programmable Gate Array) to generate a square wave signal to trigger external interruption of the ASIC chip, receiving a feedback signal, and connecting the FPGA and the GPIO through an external physical connecting line to form a hardware interruption triggering-response closed loop; and (4) realizing nanosecond timestamp capture through a counter built in the FPGA, acquiring time delay data, calculating interrupt response time, and transmitting the time delay data to a PC (Personal Computer) through a UART (Universal Asynchronous Receiver / Transmitter) to calculate a maximum value, a minimum value, an average value and a data jitter range of test data. The method can effectively solve the problem that the traditional internal closed-loop test cannot reflect the real interruption randomness and the dynamic load.

The invention discloses a communication method and device based on a UART (Universal Asynchronous Receiver / Transmitter) and a 1-WI RE bus, a UART end is provided with a TX pin and is butted with a connecting end of a 1-WI RE end, and the communication method comprises the following steps: starting a 1-WI RE host mode of the UART end; after the UART end sends a reset pulse to the 1-WI RE end, a response pulse is obtained; the UART end judges whether to execute data transceiving or not according to a comparison result of the response pulse and the reset pulse; and when it is judged that data receiving and transmitting need to be executed, the UART end sends data to the 1-WI RE end or receives data from the 1-WI RE end. After the scheme of the invention is used, a corresponding 1-WI RE bus interface does not need to be configured on the host, the increase of cost is avoided, and the bus communication based on the 1-WI RE protocol is realized under the condition that the 1-WI RE bus interface is not configured.

The invention relates to a debugging method and device of embedded equipment, an electronic device and a storage medium, and the debugging method of the embedded equipment comprises the steps: obtaining instruction set information of the embedded equipment through a UART (Universal Asynchronous Receiver / Transmitter) interface; configuring a corresponding cross compiling component based on the instruction set information; compiling a preset probe source code into an executable file by utilizing a cross compiling component; extracting a minimum code subset in the executable file, and determining a code probe according to the minimum code subset; and injecting the code probe into the free memory space on the embedded device through the UART interface, and debugging the embedded device. According to the method and the device, the problem of low debugging flexibility of the embedded equipment is solved.

The invention relates to the field of wireless product testing, and provides a multi-device cooperative closed-loop testing method based on state machine driving, and the method comprises the steps: monitoring the data output of a universal asynchronous receiver / transmitter (UART) interface of a tested device in real time; analyzing the data output by the UART interface of the tested equipment to identify the current running state of the tested equipment; dynamically generating at least one control instruction according to a preset state transition rule set and the identified current operation state; distributing the at least one control instruction to corresponding external test equipment to drive the external test equipment to execute corresponding test operation on the tested equipment; and repeatedly executing the steps of monitoring, analyzing, generating the control instruction and distributing, and automatically and continuously propelling the test process based on the response state of the tested equipment until all test items are completed. According to the technical scheme, multi-device closed-loop testing is driven through the state machine, and the testing automation degree and the process continuity are remarkably improved.

The invention provides a development board based on a secure real-time bus SRB chip, and relates to the technical field of power electronics. The development board comprises any one or more of an SRB real-time single-twisted pair 100M Ethernet interface, an SRB real-time standard gigabit Ethernet interface, an SRB external memory interface EMIF parallel interface, an SRB serial peripheral interface SPI serial interface, an SRB configuration universal asynchronous receiver / transmitter UART serial port, an ARM RS422 serial port, an RS232 serial port, a CAN interface, an ARM UART serial port, an ARM 100M network port, an ARM JTAG interface and a power supply interface. According to the method, not only is the security bus characteristic test of the SRB chip concerned, but also other key function modules (such as an Ethernet interface, a memory interface, a serial peripheral interface and the like) are covered, so that a developer can more comprehensively evaluate the overall performance and reliability of the SRB chip, not just the security bus part.

The invention relates to the technical field of Internet of Things, in particular to a circuit for simultaneously converting UART (Universal Asynchronous Receiver / Transmitter) to multi-path different level communication, which comprises a double-USB input module, a power supply processing module, a USB-UART core conversion module and a multi-path level conversion module, the double-USB input module comprises an MINI-USB interface J6 and a USB-B interface J8, VBUS pins of the two interfaces are connected in parallel through a Schottky diode and then output to the power supply processing module, and data differential pair pins are connected in parallel and then connected to the USB-UART core conversion module; and the power supply processing module comprises an LDO (Low Dropout Regulator) voltage stabilizing chip and a filter capacitor, and is used for converting 5V voltage output by the double-USB input module into 3.3 V stable voltage. The circuit design that the UART is connected with various different levels for communication is adopted, the tool integration technology is achieved, the design that the two USB ports are connected in parallel is adopted, the compatibility of the USB data line can be effectively improved, the demands of customers are met, and the technical difficulty that one UART bus is connected with multiple USB ports is broken through.

The embodiment of the invention discloses a module upgrading method and system based on UART (Universal Asynchronous Receiver / Transmitter) equipment and related equipment, and the method comprises the steps: receiving module firmware upgrading data sent by a main control computer through a first DMA (Direct Memory Access) transmission channel in a firmware upgrading mode of a module, the first DMA transmission channel is a DMA transmission channel established by the MCU based on a receiving pin of the first UART equipment, and the transmission direction is from the main control computer to the MCU; module firmware upgrading data is sent to the module through a second DMA transmission channel so that the module can conduct firmware upgrading according to the module firmware upgrading data, the second DMA transmission channel is a DMA transmission channel established by the MCU based on a sending pin of second UART equipment, and the transmission direction is from the MCU to the module; in the firmware upgrading process, the first UART device and the second UART device are multiplexed, the DMA transmission channel is established for data transmission, the CPU does not need to participate in the transmission process, and the burden of the CPU is relieved.

The invention provides a UART (Universal Asynchronous Receiver / Transmitter) expansion application method and system based on an MTK (Media Tek) platform and a storage medium, and the method comprises the steps: firstly, judging whether peripheral equipment is accessed or not according to first level information; when the access of the peripheral equipment exists, acquiring first serial number information of the accessed UART interface, and then sending a first handshake instruction according to the first serial number information; then, if a first handshake feedback instruction is received, determining first peripheral coding information according to the first handshake feedback instruction; and finally, according to the first serial number information and the first peripheral coding information, configuring UART communication configuration of the MTK platform, so as to establish communication connection with the peripheral. Through a mode of automatically identifying and configuring the UART interface, the number of the UART peripherals accessed to the MTK platform is increased, the problem that communication cannot be carried out due to the fact that the peripherals are accessed to wrong channels is avoided, and the error-tolerant rate of production work is improved.

A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver / transmitter (UART) interface.

A universal asynchronous receiver / transmitter includes a transmit register including information to be transmitted, a receive register including received information, a frame error check circuit that evaluates contents of the receive register for a frame error, and a control logic. The control logic routes contents of the transmit register to the receive register. During transmission of the contents of the transmit register to the receive register through a reprogrammable pin, the control logic modifies a bit inversion register to produce modified contents to be provided to the receive register. The modified contents cause a frame error. The control logic determines whether the frame error check circuit detects the frame error.

The invention relates to the technical field of data transmission, in particular to a filtering control method and device for air conditioner communication software and a storage medium, and aims to solve the problem of how to ensure that a receiver can reliably receive data when UART (Universal Asynchronous Receiver / Transmitter) communication is used. The invention provides a filtering control method for communication software of an air conditioner, which comprises the following steps that: when a data sending demand is detected, a main control party sends first data to a receiving party according to a target baud rate; according to the target baud rate and the data length of the first data, the tolerance duration of the receiver for receiving the first data is determined; after the receiver receives the first data, bit number verification is carried out on each bit in each frame of data according to the tolerance duration; and storing each frame of data after verification into an array, and judging the analysis condition of the first data according to a digit verification result after the first data is completely received.

The invention relates to the technical field of communication debugging, in particular to a long-distance UART (Universal Asynchronous Receiver / Transmitter) serial port communication device and a long-distance UART serial port communication system. The device sends a serial port communication waveform to a switch pin of a transmitting end switch device by utilizing a UART serial port module; the transmitting end switching device is connected with the optical fiber transmitter, and the optical fiber transmitter transmits an optical signal to other devices through an optical fiber; the optical fiber receiver receives an optical signal through an optical fiber, the optical fiber receiver is connected with the receiving end switching device, and the receiving end switching device is connected with the UART serial port module. It can be understood that according to the technical scheme, through the characteristics of the optical fiber, the communication distance is increased, the anti-interference capacity of the communication line is greatly improved, physical electrical isolation between the two UART serial ports is achieved, and the anti-damage capacity is improved.

The invention relates to the technical field of field bus control, in particular to a system module for analyzing ModBus RTU (remote terminal unit) messages and UART (universal asynchronous receiver / transmitter) settings sent by a host, which can quickly and accurately analyze the settings so as to achieve quick online, reduce the trial and error cost and improve the debugging efficiency, and comprises an acquisition circuit and a single chip microcomputer, the acquisition circuit comprises a front-end protection circuit, a communication circuit, an isolation optocoupler circuit, a sampling hold circuit and a square wave oscillation circuit, the square wave oscillation circuit is used for generating a synchronizing signal, intercepting a communication data frame sent by a host, synchronously sampling the communication data frame by the sampling hold circuit and then outputting the communication data frame to an input port of the single chip microcomputer, the single chip microcomputer firstly analyzes UART parameters and then analyzes Modbus Rtu parameters, and the communication data frame is transmitted to the host. And finally, a ModBus RTU message and UART setting sent by the host are obtained.

The invention provides a device and a method for converting a CameraLink interface and a WiFi (Wireless Fidelity) interface in a satellite, belongs to the technical field of wireless communication, and aims to solve the problems of insufficient transmission rate, high power consumption of communication equipment, large size and opaque protocol conversion in the existing satellite wireless communication technology. The device comprises a core controller, a wired module, a wireless module, a power supply module, a DDR (Double Data Rate) module, a clock module, a Flash module, a JTAG (Joint Test Action Group) module, a USB-UART (Universal Asynchronous Receiver / Transmitter) interface, an M.2 interface and an SD (Secure Digital) card, and the method comprises the following steps of: sending wired data to a PL end after level conversion and isolation, transmitting the wired data to the wireless module through a PCIe (Peripheral Component Interconnect Express) interface after protocol analysis and format unification, and sending the wired data in a wireless mode; and a receiving end executes an inverse process and recovers to an original wired signal, thereby realizing transparent transmission.

The utility model relates to a quadruped robot-based battery transmit-receive bus structure convenient to disassemble, which comprises a concentrator I and a concentrator II, the concentrator I is connected with a PC terminal, a battery, a motor and an IMU module, the battery is transmitted to the concentrator I through an RS protocol at a bps rate, the motor is transmitted to the concentrator I through a CANFD protocol at an M rate, and the IMU module is connected with the PC terminal. The IMU module transmits bps to the concentrator I through a UART (Universal Asynchronous Receiver / Transmitter) protocol; the concentrator 2 is connected with a UWB positioning module 1, a UWB positioning module 2 and a UWB positioning module 3. The concentrator 2 is connected to a PC terminal through a USBHID + CDC. The system can be used for optimizing the bus structure of the quadruped robot, increasing the control information effect of the robot and improving the running quality of a long-time gait system of the robot.

The utility model provides a multipath UART (Universal Asynchronous Receiver / Transmitter) signal conversion circuit and a storage chip particle characteristic analysis circuit. The multipath UART signal conversion circuit comprises a singlechip and an SPI (Serial Peripheral Interface) four-channel asynchronous transceiver which are connected in sequence, the SPI interface four-channel asynchronous transceiver is connected with UART (Universal Asynchronous Receiver / Transmitter) signal interfaces of a plurality of external storage chip particle modules; the single chip microcomputer is used for providing SPI signals for the SPI interface four-channel asynchronous transceiver; and the SPI interface four-channel asynchronous transceiver is used for communicating with the UART signal interface of the storage chip particle module according to the SPI signal so as to receive the UART signal sent by the UART signal interface. According to the technology, after an SPI serial port of a single chip microcomputer is connected with an SPI interface four-channel asynchronous transceiver, the SPI interface four-channel asynchronous transceiver is connected with UART (Universal Asynchronous Receiver / Transmitter) signal interfaces of a plurality of external storage chip particle modules, so that a communication channel is provided for the storage chip particle modules.

A connected-vehicle interface module is provided that includes a connected-vehicle controller, a connected-vehicle radio for receiving an activation signal from a first vehicle warning system controller indicating a road condition, and a connected-vehicle interface controller. The connected-vehicle interface controller further includes a microcontroller and a plurality of universal asynchronous receiver transmitters for receiving and transmitting data communicated to the microcontroller through one or more wired connections to at least one of the connected-vehicle controller and the connected-vehicle radio, a memory device in communication with the microcontroller, and a transceiver and one or more communication ports, coupled to the microcontroller, for connection and communication with a connected vehicle road side unit, wherein the activation signal from the first vehicle warning system controller is communicated to the connected vehicle road side unit via the one or more communication ports.

The utility model provides a low-power-consumption frequency conversion washing machine control system, which is applied to the technical field of washing machine control systems and comprises a driving control board and a display board, and information is transmitted between the display board and the driving control board through UART (Universal Asynchronous Receiver / Transmitter) communication; a power supply circuit is configured on the driving control board and comprises an input module, a switch module and an output module, an alternating-current power supply is connected to the input module for filtering and rectifying to generate direct-current voltage and then input the direct-current voltage to the switch module, and the switch module generates corresponding alternating-current voltage according to the switching frequency of a switching tube; various direct-current voltages are output after being filtered and rectified by the output module; the direct-current voltage comprises a direct-current voltage I, a direct-current voltage II and a direct-current voltage III, and the direct-current voltage II is connected to the step-down converter U4 and then is subjected to step-down to form the direct-current voltage III. Basic functions of the washing machine are achieved through mutual cooperation of the driving control board and the display board, and power consumption can be reduced when the washing machine is in a sleep state through circuit design.

A system and method are provided that enables a processor to undergo a functional test of its circuits prior to attachment to a semiconductor package and prior to use in a computing platform. The method of testing chips includes attaching a non-packaged semiconductor circuit to a test bed, loading computer instructions into a memory of the non-packaged semiconductor circuit, and operating the non-packaged semiconductor circuit in a test boot mode and executing the computer instructions in that mode. The operation logs one or more events of the execution of the instructions in the test boot mode and transmits the logs of the one or more events from the non-packaged semiconductor circuit via a joint test action group (JTAG) interface or a universal asynchronous receiver / transmitter (UART) interface.

The invention provides a serial port selection method, device and equipment and a readable storage medium, and is applied to a CPLD (Complex Programmable Logic Device) in UART (Universal Asynchronous Receiver / Transmitter). The method comprises the following steps: receiving a serial port selection instruction issued by an upper computer; the serial port selection instruction carries a baud rate corresponding to a target serial port, and a mapping relation between serial port numbers of optional serial ports and the baud rate is pre-stored in the CPLD; identifying a target serial port according to a serial port selection instruction issued by the upper computer, and connecting the target serial port with the UART path; and generating a corresponding sampling clock and sampling time according to the baud rate corresponding to the target serial port, and completing communication connection with the target serial port by using the sampling clock and the sampling time. According to the technical scheme, the flexibility of serial port switching and the debugging convenience are improved.

The invention provides a chip BootLoader dual-mode configuration system, which belongs to the technical field of chip boot programs, is integrated in a chip ROM (Read Only Memory), and comprises an OTP (One Time Programmable) storage module, a dual-mode control module, a UART (Universal Asynchronous Receiver / Transmitter) communication module, a key generation module, a CRC32 verification module, a QSPI (Quantitative Serial Peripheral Interface) module and a command processing module, therefore, the multi-element scene is adapted, and the compatibility and the flexibility are greatly optimized. And a communication key and a program encryption key are generated by adopting a double-key differentiation mechanism based on the unique information of the chip, so that the security protection capability is remarkably improved, and illegal invasion and data leakage are completely eradicated. Therefore, safe, flexible and reliable chip guiding and configuration are realized, and the application requirements of the embedded chip in the fields of industrial control, automotive electronics, Internet of Things and the like are met.

A circuit may enable communication between a primary device and one or more secondary devices. The communication may utilize a Universal Asynchronous Receiver Transmitter (UART) protocol. In operation, the primary device may require information on the baud rate of the secondary device. The UART may operate in an inverted polarity mode, and this inverted polarity may be interpreted by the secondary device as a request to enter an auto-baud detection mode. Using the inverted polarity mode to enter the auto-baud detection mode may prevent excessive delays in the UART communication and may prevent the need for additional pins to implement the auto-baud detection mode.

A connected-vehicle interface module is provided that includes a connected-vehicle controller, a connected-vehicle radio for receiving an activation signal from a first vehicle warning system controller indicating a road condition, and a connected-vehicle interface controller. The connected-vehicle interface controller further includes a microcontroller and a plurality of universal asynchronous receiver transmitters for receiving and transmitting data communicated to the microcontroller through one or more wired connections to at least one of the connected-vehicle controller and the connected-vehicle radio, a memory device in communication with the microcontroller, and a transceiver and one or more communication ports, coupled to the microcontroller, for connection and communication with a connected vehicle road side unit, wherein the activation signal from the first vehicle warning system controller is communicated to the connected vehicle road side unit via the one or more communication ports.

The utility model belongs to the technical field of GNSS (Global Navigation Satellite System) inertial navigation, and particularly discloses a GNSS inertial navigation performance testing device which comprises a plurality of USB (Universal Serial Bus) interfaces connected with a computer and a plurality of GNSS modules corresponding to the USB interfaces, a linear voltage regulator and a USB-to-UART (Universal Asynchronous Receiver / Transmitter) circuit are connected between each USB interface and the GNSS module, and the USB-to-UART circuit is connected with the computer. According to the utility model, through cooperation of the plurality of USB interfaces, the logic level driving circuit, the CAN bus transceiver, the WHELLTICK level conversion circuit and the FWD level conversion circuit, a plurality of GNSS modules can be tested at the same time, and vehicle levels of the WHELLTICK and the FWD can be converted into TTL levels by using the WHELLTICK level conversion circuit and the FWD level conversion circuit so as to match the level of the GNSS; the logic level driving circuit divides a group of signals into a plurality of groups of same signals, and then the signals are connected to different GNSS module pins, so that the information received by the GNSS is ensured to be the same, the consistency of the GNSS can be tested, a comparison sample can be added, the test efficiency is improved, and a certain test cost is reduced.

The utility model relates to combined navigation equipment, belongs to the technical field of navigation, and solves the problems of high cost and high power consumption of a receiver for navigation in the prior art. The combined navigation equipment comprises a radio frequency chip, a baseband chip and a DSP (Digital Signal Processor) chip; the signal input end of the radio frequency chip is connected with a navigation antenna, and the signal output end of the radio frequency chip is connected with the signal input end of the baseband chip; the signal transmission end of the baseband chip is connected with the first UART interface of the DSP chip; a second UART (Universal Asynchronous Receiver / Transmitter) interface of the DSP chip is used as a first external interface of the combined navigation equipment and is connected with host equipment; and the radio frequency chip is connected to the DSP chip through an SPI (Serial Peripheral Interface) bus. The navigation equipment with low cost and low power consumption is realized.

The utility model discloses a testing device, belongs to the technical field of testing, and is used for improving the testing efficiency. The device comprises a substrate, a network port, a network switching element, a universal asynchronous receiver / transmitter (UART) serial port, a micro control unit (MCU) and a plurality of objects to be tested, the network port, the network switching element, the UART serial port, the MCU and the plurality of objects to be tested are arranged on the substrate; the network port is connected with the first end of the network switching element; the second end of the network switching element is connected with the plurality of to-be-tested objects; the UART serial port is connected with the first end of the MCU; and the second end of the MCU is connected with the plurality of to-be-tested objects.

The invention discloses a quick diagnosis method and device for startup faults of a domestic desktop computer platform, and relates to the technical field of domestic computer circuit design, a BIOS (Basic Input Output System) of the desktop computer platform is loaded and operated in the startup process, a processor outputs corresponding debugging information, and the debugging information comprises a startup process state flag bit set by the BIOS; serial port debugging information of the processor is opened to the outside through a mainboard debugging interface, and meanwhile, a UART (Universal Asynchronous Receiver / Transmitter) serial port of the processor is in signal interconnection with a single chip microcomputer in hardware design; after the single-chip microcomputer collects debugging information from the processor, a specific character string is searched and grabbed to correspond to the starting process, the nixie tube is controlled to display an agreed numerical value according to logic, and the state of the starting process is confirmed through the numerical value displayed by the nixie tube. According to the method, rapid visual diagnosis in the startup process of the desktop computer can be realized, and the BIOS running and loading stage can be judged without connecting an external debugging platform.

The utility model relates to the technical field of circuits, in particular to a motor self-adjusting control circuit and a stamper machine, and the motor self-adjusting control circuit comprises a single-chip microcomputer, an infrared geminate transistor, a stamper motor driving chip and a two-phase stepping motor. A first UART (Universal Asynchronous Receiver / Transmitter) interface of the singlechip is connected with an infrared geminate transistor, a first GPIO (General Purpose Input / Output) interface of the singlechip is connected with an input end of a seal motor driving chip, an output end of the seal motor driving chip is connected with a two-phase stepping motor, and the two-phase stepping motor is connected with one end of a seal; infrared photoelectric signals are detected through the infrared geminate transistors, pulse signals are output to the seal motor driving chip after the single-chip microcomputer receives the infrared photoelectric signals fed back by the infrared geminate transistors, and the rotation angle of the two-phase stepping motor is controlled through the seal motor driving chip, so that the number of rotation turns of the lead screw in the two-phase stepping motor is adjusted, and the seal is achieved. The purpose of controlling the height of the seal is achieved.

The invention mainly discloses a bridging device with a data monitoring function and a USB / UART (Universal Serial Bus / Universal Asynchronous Receiver / Transmitter) conversion device with the bridging device, the bridging device can be arranged on a circuit board in an integrated circuit (IC) chip mode, and the bridging device, a USB electric connector and a UART electric connector which are arranged on the circuit board form the USB / UART conversion device. When the bridging device is used, the USB electric connector is electrically connected to a main control computer, the UART electric connector is electrically connected to an external electronic device, and at the moment, the bridging device provides at least three groups of virtual COM ports for the main control computer, so that the main control computer can perform data transmission with the external electronic device by utilizing one group of virtual communication ports. In addition, when data transmission operation and data receiving operation are carried out, the main control computer can also utilize the other two groups of virtual communication ports to realize data distribution and monitor the distributed data.

The invention relates to the technical field of molecular pump control, and discloses a synchronous control method and device for a magnetic suspension molecular pump carrying an FPGA (Field Programmable Gate Array), and the method comprises the steps: receiving a message in response to a UART (Universal Asynchronous Receiver / Transmitter) signal output by a magnetic suspension molecular pump controller, and storing the message in a txd-FIFO (First In First Out) buffer area; system configuration is carried out according to an analysis result of the message, a transmission instruction is sent to a lower computer, and a TXD signal is output; a clock synchronization mechanism is used for controlling the system to operate under the condition of a synchronous clock CLK; in response to a message reading instruction of the magnetic suspension molecular pump controller, the message read through the RXD signal is stored to the rxd-FIFO buffer area, and the message is returned to the magnetic suspension molecular pump controller, the FPGA chip is introduced, the buffer area is added, clock synchronization is carried out, clock error accumulation caused by serial data transmission is reduced, and the reliability of the magnetic suspension molecular pump controller is improved. The requirement of high-speed Internet of Things communication development is met, and the stability of controller communication output signals is improved.