262 results about "Master processor" patented technology

The invention provides a mud tank liquid level height accurate measurement early warning system and method, the mud tank liquid level height accurate measurement early warning system comprises a measurement support and a control unit comprising a main processor, and the control unit is further connected with a plurality of liquid level detection assemblies, a temperature compensation module, a stirring assembly, an early warning device, a data storage unit and a calibration assembly. The multiple liquid level detection assemblies comprise laser and ultrasonic range finders, the main processor receives detection signals and then corrects the liquid level height in combination with temperature compensation, early warning is started when the liquid level height is abnormal, the detection precision can be calibrated periodically through the calibration assembly, and meanwhile remote data transmission and historical data storage are supported. The method solves the problems that traditional measurement is low in precision, depends on manpower and is delayed in early warning, and is suitable for monitoring the liquid level of the mud tank in various drilling operations.

The invention discloses an abnormal data real-time filtering method and system based on edge computing in a dynamic environment system, the method is executed by an edge computing gateway, sliding window weighted average preprocessing is equivalently realized by adopting integer shift operation, and the single computing overhead is controlled within 50 clock cycles; dynamically and adaptively adjusting dynamic reference model parameters based on the ratio of the network load to the sensor sampling frequency; performing multi-stage anomaly filtering of a hard threshold value, a mutation rate and a statistical interval on the data through a three-stage pipeline judgment structure executed by atomization; an FPGA hardware queue manager independent of a main processor bypasses a TCP stack to push abnormal data at the highest priority, and redundant data is stored in a zero-copy annular buffer area managed by DMA. According to the invention, the problems of intranet congestion, server I / O bottleneck and alarm delay under the centralized architecture of the traditional dynamic loop system are solved, and the fault, fault, fault, fault, fault and fault are realized on resource-limited platforms such as Cortex-M4 and the like; the average alarm delay is 8 milliseconds; and the data compression rate is more than 90%.

The invention discloses a cloud edge collaborative information interaction processing device, method and system with an endogenous security architecture. The equipment comprises a main processor, a hardware security chip, a programmable logic unit, a communication unit and an equipment management unit. A trusted execution environment is constructed in the hardware security chip and is in isolated communication with a common execution environment of the main processor through a security bus, a security computing engine, a remote attestation module and a trusted key warehouse are arranged in the trusted execution environment, and the programmable logic unit is directly controlled by the trusted execution environment to realize dynamic hardware acceleration. The communication unit is provided with independent interfaces which are connected with the two execution environments respectively, unification of hardware-level security isolation and efficient cooperative computing is achieved, and the problems of privacy disclosure and untrusted process in cloud edge collaboration are solved.

A scalable AI system includes a plurality of slots on a main board, at least one AI module mounted in the slots to perform AI operations, and a main processor that controls the entire system. A user can flexibly scale the overall AI computation performance of the system by adjusting the number of AI modules as needed. Each AI module is equipped with a low-power NPU specialized for AI operations and adopts standard form factors (e.g., M.2, E1.S) to improve economy and scalability. This can solve the problems of high-power consumption and cost, which are limitations of GPU-based systems, and can efficiently support various AI applications.

The invention discloses an intelligent box, intelligent glasses and split type intelligent glasses, and relates to the technical field of intelligent glasses, the intelligent box comprises a first connection module and a main processor, the first connection module is used for realizing communication connection between the intelligent box and the intelligent glasses; the main processor is electrically connected with the first connection module, and the main processor is used for receiving and processing a first signal output by the intelligent glasses and outputting a second signal to the intelligent glasses, so that the intelligent glasses respond to the second signal and execute a corresponding action. According to the technical scheme provided by the invention, the computing power center and part of functional modules of the intelligent glasses are moved outwards, so that the weight of the intelligent glasses is reduced, and the user experience is improved.

The invention belongs to the field of edge computing, and discloses an edge intelligent computing device and method supporting multi-level storage and computing integrated acceleration, and the device comprises a main processor system, a near memory computing module and a near flash memory computing module. The near memory calculation module integrates an NPU (Network Processing Unit) with a distributed SRAM (Static Random Access Memory) and an HBM DRAM (Dynamic Random Access Memory) with an MAC (Media Access Control) array, and realizes high-throughput reasoning acceleration And the near flash memory calculation module is used for tightly coupling the SSD controller and the retrieval acceleration engine to realize the nearest retrieval acceleration of mass data at the SSD level. All the modules are interconnected through a PCIe bus, a three-level storage and calculation integrated framework of SRAM-HBM DRAM-SSD is constructed, cross-level data migration is effectively reduced, and the bottleneck of the PCIe bus is avoided. According to the method, high-throughput video reasoning and TB-level data retrieval tasks on the edge side can be efficiently supported at the same time, and the calculation energy efficiency ratio and the system throughput rate are remarkably increased.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

The utility model relates to the technical field of die bonder detection circuits, in particular to a sensor detection circuit for a die bonder, which comprises a master control module, a sensor interface module, a display control module, a signal processing module and a power supply module. The power supply module is used for supplying power to the main control module, the sensor interface module and the display control module; the sensor interface module and the display control module are respectively connected with the main control module; the main control module comprises a main processor and an auxiliary processor, the signal processing module comprises an AD7730 chip, the input end of the AD7730 chip is connected with a low-pass filter, and the main processor is connected with the auxiliary processor through an SPI interface. According to the utility model, a plurality of sensor interface circuits are arranged and can be used for high-speed and high-precision data detection of the die bonder, so that high-speed, low-noise and rapid system response of the die bonder is met, the connection complexity of the die bonder sensor is reduced, and the requirements of high precision and high sampling rate of the die bonder sensor are met.

The invention discloses a screen-off display method and device, and relates to the technical field of terminals. The method is applied to the electronic equipment, the electronic equipment comprises a main processor and an auxiliary processor, and the method comprises the steps that when the electronic equipment is in a screen-off display state, the auxiliary processor obtains event information of a first event corresponding to a first application program; if the auxiliary processor determines that the first event needs to be responded by the main processor, the main processor is awakened, and the main processor is indicated to respond to the first event to generate display data; and after the auxiliary processor obtains display data obtained by the main processor in response to the first event, performing display control according to the display data.

A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

The application provides a three-level inverter fault diagnosis method based on an output voltage vector image, and relates to the technical field of power electronic equipment state monitoring and fault diagnosis, and the method comprises the following steps: collecting three-phase output voltage signals in real time by an inverter master control microcontroller, obtaining voltage vector sequences in a two-phase stationary coordinate system after filtering, normalization and Clarke transformation; setting a short-time analysis window, generating a two-dimensional gray image representing the instantaneous motion trajectory form of the voltage vector by coordinate mapping, bilinear interpolation and gray processing on the continuous vector sequences in the window; loading and executing a pre-quantized lightweight convolutional neural network model by using a special lightweight convolutional neural network model integrated in the microcontroller, performing real-time inference and fault mode matching on the trajectory image; and feeding back the microsecond-level diagnosis result to the main processor core by the model through a hardware interrupt, so as to trigger immediate protection or fault-tolerant control.

The application discloses a bottom-layer security defense architecture and method based on thermodynamic entropy and nanosecond physical short circuit, which comprises a thermodynamic chaotic true random number generator configured to collect physical thermal noise and generate a true random number; a time-space jump memory management configured to dynamically remap the physical storage address of a volatile memory based on the true random number; a programmable hardware logic unit configured to run independently of a host processor and perform out-of-band polling on a physical intrusion detection signal; and a physical short circuit module connected between the power supply rail and the ground of the volatile memory, wherein the programmable hardware logic unit sends a trigger signal to the physical short circuit module when detecting the physical intrusion signal, and the physical short circuit module responds to the trigger signal to short the power supply rail of the volatile memory to the ground within a preset transient time threshold, so that the physical level data destruction less than 5 nanoseconds and the dynamic address confusion driven by the true random number are realized.

The invention discloses a version upgrading method and a related device thereof, and the version upgrading method comprises the steps that a main processor receives request version information sent by a target sub-processor, and sends the version information of to-be-upgraded system version data corresponding to the target sub-processor to the target sub-processor, the main processor is used for controlling the upgrading of each sub-processor; in response to the received upgrade request information sent by the target sub-processor, the to-be-upgraded system version data is forwarded to the target sub-processor through the bridging channel, and the upgrade request information is generated after the target sub-processor receives the version information and confirms authorization. According to the scheme, the version upgrading efficiency of the processor can be improved.

The application discloses an abnormal power consumption processing method, an abnormal power consumption processing device, a terminal device and a storage medium, and relates to the technical field of power management. In the application, an abnormal power consumption processing method for balancing application running and device endurance is provided, and is applied to a terminal device including a main processor. In the use process of the intelligent device, if there is an abnormal power consumption problem caused by application running, a processing strategy is determined through a judgment rule of an abnormal power consumption type and an abnormal power consumption level and power consumption data when the application is running, and abnormal power consumption processing is performed, instead of directly ending or exiting the running application, so that the application can be run while ensuring the device endurance, and the application is suitable for the actual use scene of the intelligent device.

The invention belongs to the technical field of avionics, and particularly relates to an architecture design method of a TSN network end system with dual-processor collaboration. The system architecture comprises a main processor and a network card; a buffer A, a register A, a buffer B, a register B, a coprocessor and a protocol conversion module are arranged in the network card; the main processor performs data interaction with a buffer A and a register A in the network card; the coprocessor performs data interaction with a buffer B and a register B in the network card; the protocol conversion module performs data interaction with the buffer A, the register A, the buffer B, the register B and an external network; the main processor is used for receiving an airborne light thunder signal, a sensor signal, an avionics / electromechanical control signal and a graphic video signal, and outputting light thunder sensor data, an avionics / electromechanical control instruction and a graphic video signal; the coprocessor is used for receiving avionics network management data, network time synchronization data and built-in self-inspection data and outputting corresponding data packets.

The application discloses a kind of data processing method, device and readable medium based on blockchain, the blockchain includes terminal equipment, and the terminal equipment includes main processor and coprocessor;The method comprises: generating cryptography operation instruction according to business transaction instruction by main processor, and issuing cryptography operation instruction to coprocessor;Cryptography operation instruction is received by coprocessor, and the instruction type of cryptography operation instruction is identified;The instruction type is used to indicate the cryptography operation type corresponding to cryptography operation instruction;Business transaction instruction is executed by main processor, and cryptography operation instruction is executed according to instruction type by coprocessor.This scheme realizes the parallel execution of business transaction and cryptography operation by the collaborative architecture of main processor and integrated coprocessor, greatly improves the overall data processing speed and concurrent capability of blockchain terminal, avoids that main processor is blocked by a large number of cryptography operation tasks.

The application relates to the technical field of mainboards, in particular to an industrial mainboard security starting method based on a hardware root of trust, which comprises the following steps: after the industrial mainboard is powered on and reset, a security control domain runs prior to a business processing domain, and a main processor is kept waiting for starting; the security control domain reads hardware root anchor credentials and an initial boot program, and sequentially performs integrity measurement and signature verification on the initial boot program and a later-stage boot program; after the verification passes, running key materials are derived based on a random seed, device private credentials and a later-stage boot program digest, a running private key is written into a restricted key area, and a running public key is written into a public storage area; when a boot update package exists, a firmware public key certificate, a boot image signature and a replacement identifier are verified, a boot image is loaded after the certificate is valid and the signature passes, starting proof information is generated, an access path is closed and the main processor is released; any verification failure enters a fault processing flow.

A satellite-borne safety intelligent computing system is used for guaranteeing safety of a satellite edge computing system and comprises a host processor, an AI accelerator and a safety bus connected with the host processor and the accelerator. The satellite-borne safe intelligent computing system further comprises a bus stream encoding and decoding engine which is embedded in the interface controller of the data bus and used for encrypting and decrypting transmission data of the data bus. By encrypting the cache stream on the data bus, key data such as Bias bias cache and the like can be protected. In addition, an attacker can be prevented from stealing structural information of the neural network model through interrupt signals by interrupting obfuscated codes, dual protection of'signal + data 'is formed, and time sequence detection Trojan horse and side channel attacks can be effectively resisted.

Provided in the embodiments of the present disclosure are a server and a server management method. The server comprises a baseboard management controller, a main processor, and a plurality of nodes. The baseboard management controller is connected to the main processor and is configured to monitor and manage the main processor. The main processor is indirectly connected to the plurality of nodes and is configured to monitor and manage the plurality of nodes. The plurality of nodes are configured to execute computing tasks under the management of the main processor. By means of a three-tier management architecture including the baseboard management controller, the main processor and the nodes, the server provided in the embodiments of the present disclosure can allow complex node management tasks to be processed by the main processor, thereby decoupling data center operation and maintenance from a service, and the server can effectively shield a data center operation and maintenance team from the direct perception of node resources, thereby realizing the standardization of an operation and maintenance process.

The invention relates to reverse publication of subtasks from an accelerator to a host processor using cache storage. A computing system includes a main processor and an accelerator. The host processor includes a cache. The main processor is configured to assign a compute task to the accelerator. The accelerator is used to select a sub-task of the compute task and to allocate the sub-task back to the main processor by storing the sub-task directly into a cache of the main processor.

The invention provides an integrated inertial measurement module, a measurement method and terminal equipment, and relates to the technical field of sensors. The integrated inertial measurement module comprises: a packaging body; a substrate disposed within the package; a sensor array disposed on the substrate, the sensor array comprising a plurality of micromechanical gyro sensor units for measuring angular velocity; the plurality of slave processors are arranged on the substrate, each slave processor is electrically connected to one sensing subset in the sensor array, and the slave processors are used for carrying out local weight fusion on measured values of the micromechanical gyroscope sensor units in the sensing subset and outputting local fusion values; and the main processor is arranged on the substrate, is electrically connected to all the slave processors, and is used for carrying out global weighted fusion on each local fusion value and outputting a final angular velocity measurement value. According to the invention, the measurement precision of the micromechanical gyroscope sensor unit can be improved.

Embodiments of the present disclosure relate to a control circuit, a display device, and a method for driving a main processor. Specifically, the invention provides a method. A control circuit, a display device, and a method for driving a main processor may be provided that may reduce power consumption in a transmission / reception circuit connected with an interface by powering off at least one of a source transmission / reception circuit or a sink transmission / reception circuit electrically connected with an auxiliary channel AUX during at least a portion of a vertical blank period.

The present disclosure relates to a video stream processing method and device, electronic equipment and storage medium. The method can include: transmitting a video stream at a current time to a preprocessor to cause the preprocessor to perform road element recognition on the video stream at the current time to obtain an element recognition result corresponding to the current time; sending the element recognition result corresponding to the current time to a main processor to cause the main processor to predict a video stream at a next time based on the element recognition result corresponding to the current time, determining first target allocation information in a case where a video stream prediction result represents that the predicted video stream at the next time is a first type of video stream, and awakening a coprocessor in a case where the coprocessor is not awakened. According to the technical scheme provided by the present disclosure, the video stream at the next time can be predicted, and in a case where it is determined that the video stream at the next time is the first type of video stream, the coprocessor is awakened in advance to improve the response timeliness of the coprocessor, i.e., the timeliness of processing data.

An electro-optical (EOM) included within an enclosure is provided. The EOM comprises at least two camera modules, and configured to determine depth of a target by using a block matching algorithm operative to match pixels derived from an image captured by one of the camera modules with pixels derived from an image captured by another of the two camera modules. The EOM is characterized in that it comprises: a first isolating material located between the EOM and its enclosure, and configured to prevent structural forces from being developed due to deformation of the EOM enclosure; a main processor baseboard PCB to which each of the camera modules is connected; and one or more flat cables connecting the EOM enclosure with the main processor baseboard PCB, wherein the one or more flat cables are placed in an “s” shape within the EOM enclosure.

The invention discloses a method for a display driving circuit, comprising the following steps: receiving an input frame from a main processor, the input frame having a plurality of segments; detecting an earliest horizontal sync start packet in the plurality of segments, where the earliest horizontal sync start packet indicates a start of an earliest segment of a full-refresh display area on an output frame; and updating the full-refresh display area on the output frame when the earliest horizontal synchronization start packet of the earliest segment of the full-refresh display area is detected.

The invention provides a server and a security verification method, the server comprises a security control module provided with an encrypted file and a main processor module provided with a secret key, and the security control module is connected with the main processor module; wherein the main processor module is configured to read an encrypted file in the security control module and perform security verification on the security control module by using a secret key; under the condition that the safety control module is verified successfully, a working voltage is provided for the safety control module; and the safety control module is configured to send an access instruction to the main processor module under the condition that the working voltage is received, and the access instruction is used for accessing storage information in the main processor module. Therefore, the threat of the safety control module to the main processor module can be reduced, and the safety operation of the main processor module is improved.

The invention discloses a communication performance optimization method, electronic equipment and a computer readable storage medium, and belongs to the technical field of communication. The communication performance optimization method is applied to a dual-computer communication system in which a master processor and a slave processor are in communication connection based on a preset communication protocol. The communication performance optimization method comprises the following steps: dynamically obtaining to-do tasks in a task list; determining a task category and a cache space category of the to-be-handled task according to the urgency degree and the complexity of the to-be-handled task; determining an execution position and a task priority of the to-be-handled task according to the task category; and dynamically adjusting data in the cache space according to the cache space type. The working performance of the wearable device can be improved through the dual-machine system.

This invention discloses a fault handling method based on a dual-core lockstep processor. The dual-core lockstep processor includes a master processor and a slave processor. The dual-core lockstep processor receives data from the last four stages of the processor's pipeline via a fault detection module, outputting a fault flag signal and a fault program pointer. A front-end fault handling module receives the fault flag signal and the fault program pointer, performing a pipeline-level rollback. A back-end fault handling module controls the handshake and selection signals of the last four stages of the pipeline and executes a virtual write-back fault-tolerance mechanism, managing the operating status of the last four stages of the pipeline and the instruction fetch stage pipeline. This prevents data conflicts during superscalar processor fault handling, thereby achieving full coverage of fault handling while maintaining low time and area overhead, and simultaneously achieving high performance and high reliability. This invention can be widely applied in the field of dual-core lockstep processors.

An electronic device includes a first non-volatile memory (NVM), a security device and a system on chip (SOC). The first NVM includes a non-security region and a security region. The security device includes a second NVM, a second memory controller and a memory processor. The SOC includes a main processor, a first memory controller and a security processor. In a low power mode, the memory processor is configured to provide, to the second memory controller, in response to a first write request signal, a first control command and a first security data, and the second memory controller is configured to provide, to the second NVM, in response to the first control command, a first program command, a first address, and the first security data.