423 results about "Master processor" patented technology

The invention provides a mud tank liquid level height accurate measurement early warning system and method, the mud tank liquid level height accurate measurement early warning system comprises a measurement support and a control unit comprising a main processor, and the control unit is further connected with a plurality of liquid level detection assemblies, a temperature compensation module, a stirring assembly, an early warning device, a data storage unit and a calibration assembly. The multiple liquid level detection assemblies comprise laser and ultrasonic range finders, the main processor receives detection signals and then corrects the liquid level height in combination with temperature compensation, early warning is started when the liquid level height is abnormal, the detection precision can be calibrated periodically through the calibration assembly, and meanwhile remote data transmission and historical data storage are supported. The method solves the problems that traditional measurement is low in precision, depends on manpower and is delayed in early warning, and is suitable for monitoring the liquid level of the mud tank in various drilling operations.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

The invention discloses an abnormal data real-time filtering method and system based on edge computing in a dynamic environment system, the method is executed by an edge computing gateway, sliding window weighted average preprocessing is equivalently realized by adopting integer shift operation, and the single computing overhead is controlled within 50 clock cycles; dynamically and adaptively adjusting dynamic reference model parameters based on the ratio of the network load to the sensor sampling frequency; performing multi-stage anomaly filtering of a hard threshold value, a mutation rate and a statistical interval on the data through a three-stage pipeline judgment structure executed by atomization; an FPGA hardware queue manager independent of a main processor bypasses a TCP stack to push abnormal data at the highest priority, and redundant data is stored in a zero-copy annular buffer area managed by DMA. According to the invention, the problems of intranet congestion, server I / O bottleneck and alarm delay under the centralized architecture of the traditional dynamic loop system are solved, and the fault, fault, fault, fault, fault and fault are realized on resource-limited platforms such as Cortex-M4 and the like; the average alarm delay is 8 milliseconds; and the data compression rate is more than 90%.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

The invention discloses a cloud edge collaborative information interaction processing device, method and system with an endogenous security architecture. The equipment comprises a main processor, a hardware security chip, a programmable logic unit, a communication unit and an equipment management unit. A trusted execution environment is constructed in the hardware security chip and is in isolated communication with a common execution environment of the main processor through a security bus, a security computing engine, a remote attestation module and a trusted key warehouse are arranged in the trusted execution environment, and the programmable logic unit is directly controlled by the trusted execution environment to realize dynamic hardware acceleration. The communication unit is provided with independent interfaces which are connected with the two execution environments respectively, unification of hardware-level security isolation and efficient cooperative computing is achieved, and the problems of privacy disclosure and untrusted process in cloud edge collaboration are solved.

The invention discloses a camera master control FPGA (Field Programmable Gate Array) multi-mode on-orbit program upgrading method based on dynamic reconstruction, relates to the technical field of camera master control processor program on-orbit upgrading, and solves the problem of upgrading of a master control processor FPGA in an existing camera master control single machine. According to the method, on-orbit program upgrading can be carried out on the camera master control main processor FPGA by adopting six modes based on a dynamic reconstruction strategy according to a stand-alone upgrading feedback result. When the DSP breaks down, on-orbit upgrading of an FPGA program can still be achieved through three modes of functions of the FPGA, when the FPGA breaks down, on-orbit upgrading of the FPGA program is achieved through one of the two upgrading modes of the DSP, in this way, even if the FPGA cannot load the program, on-orbit upgrading of the FPGA program can be achieved, and then the FPGA can recover working after the camera main control single machine is restarted. The problem that a camera master control single machine cannot meet task requirements due to upgrading failure caused by a single-mode upgrading method is avoided.

The invention discloses a multi-mode anti-springback numerical control plate rolling machine, and relates to the technical field of plate rolling machines, the multi-mode anti-springback numerical control plate rolling machine comprises a plate rolling machine shell, a conveyor shell and a first hydraulic telescopic cylinder, a fixing block is mounted in the middle of one side of the inner bottom wall of the plate rolling machine shell, and driven rollers are mounted on one side of the plate rolling machine shell and the other side of the fixing block through bearings. By integrating the image acquisition module and the laser ranging module, the system can accurately acquire the length, moving state and height information of a plate in real time, and after the information is processed by a preset algorithm of the main processor module, the PLC can be accurately guided to adjust the first hydraulic telescopic cylinder and the second hydraulic telescopic cylinder; therefore, accurate control over the positions of the movable roller and the driving roller is achieved, the accuracy and machining precision of plate bending forming can be improved, meanwhile, different plate rolling modes can be applied to the equipment when the equipment is used for coping with plates of different specifications, and the plate rolling efficiency is improved.

The invention discloses a data transmission method and device, electronic equipment and a storage medium, and belongs to the technical field of communication. The method comprises the steps that a first data frame is sent to a coprocessor through a main processor, the first data frame is used for controlling the main processor to write or read data to the coprocessor, the first data frame carries an address increasing identifier, and the address increasing identifier is used for indicating the coprocessor to start writing or reading data from a starting register in N registers, n is an integer greater than 1; and writing or reading data in the N registers from the starting register based on the address increase identification through the coprocessor.

A scalable AI system includes a plurality of slots on a main board, at least one AI module mounted in the slots to perform AI operations, and a main processor that controls the entire system. A user can flexibly scale the overall AI computation performance of the system by adjusting the number of AI modules as needed. Each AI module is equipped with a low-power NPU specialized for AI operations and adopts standard form factors (e.g., M.2, E1.S) to improve economy and scalability. This can solve the problems of high-power consumption and cost, which are limitations of GPU-based systems, and can efficiently support various AI applications.

The invention discloses an intelligent box, intelligent glasses and split type intelligent glasses, and relates to the technical field of intelligent glasses, the intelligent box comprises a first connection module and a main processor, the first connection module is used for realizing communication connection between the intelligent box and the intelligent glasses; the main processor is electrically connected with the first connection module, and the main processor is used for receiving and processing a first signal output by the intelligent glasses and outputting a second signal to the intelligent glasses, so that the intelligent glasses respond to the second signal and execute a corresponding action. According to the technical scheme provided by the invention, the computing power center and part of functional modules of the intelligent glasses are moved outwards, so that the weight of the intelligent glasses is reduced, and the user experience is improved.

The invention belongs to the field of edge computing, and discloses an edge intelligent computing device and method supporting multi-level storage and computing integrated acceleration, and the device comprises a main processor system, a near memory computing module and a near flash memory computing module. The near memory calculation module integrates an NPU (Network Processing Unit) with a distributed SRAM (Static Random Access Memory) and an HBM DRAM (Dynamic Random Access Memory) with an MAC (Media Access Control) array, and realizes high-throughput reasoning acceleration And the near flash memory calculation module is used for tightly coupling the SSD controller and the retrieval acceleration engine to realize the nearest retrieval acceleration of mass data at the SSD level. All the modules are interconnected through a PCIe bus, a three-level storage and calculation integrated framework of SRAM-HBM DRAM-SSD is constructed, cross-level data migration is effectively reduced, and the bottleneck of the PCIe bus is avoided. According to the method, high-throughput video reasoning and TB-level data retrieval tasks on the edge side can be efficiently supported at the same time, and the calculation energy efficiency ratio and the system throughput rate are remarkably increased.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

The utility model relates to the technical field of die bonder detection circuits, in particular to a sensor detection circuit for a die bonder, which comprises a master control module, a sensor interface module, a display control module, a signal processing module and a power supply module. The power supply module is used for supplying power to the main control module, the sensor interface module and the display control module; the sensor interface module and the display control module are respectively connected with the main control module; the main control module comprises a main processor and an auxiliary processor, the signal processing module comprises an AD7730 chip, the input end of the AD7730 chip is connected with a low-pass filter, and the main processor is connected with the auxiliary processor through an SPI interface. According to the utility model, a plurality of sensor interface circuits are arranged and can be used for high-speed and high-precision data detection of the die bonder, so that high-speed, low-noise and rapid system response of the die bonder is met, the connection complexity of the die bonder sensor is reduced, and the requirements of high precision and high sampling rate of the die bonder sensor are met.

The application provides a vehicle-mounted unit, a mobile device and a control method. The vehicle-mounted unit comprises a first SIM, a second SIM, a main processor, a modem, a radio frequency switch module and an antenna module. The first SIM and the second SIM are electrically connected to the main processor. The main processor is also electrically connected to the modem. The modem is electrically connected to the radio frequency switch module and the antenna module. The main processor selects the first SIM and / or the second SIM to make a call to generate a corresponding baseband signal. The baseband signal is output to the modem. The modem is used to convert the baseband signal into a corresponding radio frequency signal and output the radio frequency signal to the radio frequency switch module for external emission via the antenna module. The vehicle-mounted unit provided by the application has a wider network coverage range to ensure a higher success rate of emergency calls.

The invention discloses a screen-off display method and device, and relates to the technical field of terminals. The method is applied to the electronic equipment, the electronic equipment comprises a main processor and an auxiliary processor, and the method comprises the steps that when the electronic equipment is in a screen-off display state, the auxiliary processor obtains event information of a first event corresponding to a first application program; if the auxiliary processor determines that the first event needs to be responded by the main processor, the main processor is awakened, and the main processor is indicated to respond to the first event to generate display data; and after the auxiliary processor obtains display data obtained by the main processor in response to the first event, performing display control according to the display data.

A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

The application provides a three-level inverter fault diagnosis method based on an output voltage vector image, and relates to the technical field of power electronic equipment state monitoring and fault diagnosis, and the method comprises the following steps: collecting three-phase output voltage signals in real time by an inverter master control microcontroller, obtaining voltage vector sequences in a two-phase stationary coordinate system after filtering, normalization and Clarke transformation; setting a short-time analysis window, generating a two-dimensional gray image representing the instantaneous motion trajectory form of the voltage vector by coordinate mapping, bilinear interpolation and gray processing on the continuous vector sequences in the window; loading and executing a pre-quantized lightweight convolutional neural network model by using a special lightweight convolutional neural network model integrated in the microcontroller, performing real-time inference and fault mode matching on the trajectory image; and feeding back the microsecond-level diagnosis result to the main processor core by the model through a hardware interrupt, so as to trigger immediate protection or fault-tolerant control.

There is provided a system having a server unit with a host processor and a service processor, a first bus interface and a second bus interface, a data storage unit with a plurality of drives grouped into a first and second group, a first serial-to-parallel-input / output (S2PIO) device connected to the first group, and a second S2PIO device connected to the second group. The system is configured to acquire, by the service processor from the host processor, an indication of a faulty memory drive in the data storage unit, the indication being indicative of a target link amongst the first link and the second link, and a position of the faulty memory drive in the target group. The system is configured to transmit, by the service processor using the target link, a command to a target S2PIO device for triggering a visual indicator associated with the faulty memory drive.

The application discloses a bottom-layer security defense architecture and method based on thermodynamic entropy and nanosecond physical short circuit, which comprises a thermodynamic chaotic true random number generator configured to collect physical thermal noise and generate a true random number; a time-space jump memory management configured to dynamically remap the physical storage address of a volatile memory based on the true random number; a programmable hardware logic unit configured to run independently of a host processor and perform out-of-band polling on a physical intrusion detection signal; and a physical short circuit module connected between the power supply rail and the ground of the volatile memory, wherein the programmable hardware logic unit sends a trigger signal to the physical short circuit module when detecting the physical intrusion signal, and the physical short circuit module responds to the trigger signal to short the power supply rail of the volatile memory to the ground within a preset transient time threshold, so that the physical level data destruction less than 5 nanoseconds and the dynamic address confusion driven by the true random number are realized.

The invention discloses a version upgrading method and a related device thereof, and the version upgrading method comprises the steps that a main processor receives request version information sent by a target sub-processor, and sends the version information of to-be-upgraded system version data corresponding to the target sub-processor to the target sub-processor, the main processor is used for controlling the upgrading of each sub-processor; in response to the received upgrade request information sent by the target sub-processor, the to-be-upgraded system version data is forwarded to the target sub-processor through the bridging channel, and the upgrade request information is generated after the target sub-processor receives the version information and confirms authorization. According to the scheme, the version upgrading efficiency of the processor can be improved.

The application discloses an abnormal power consumption processing method, an abnormal power consumption processing device, a terminal device and a storage medium, and relates to the technical field of power management. In the application, an abnormal power consumption processing method for balancing application running and device endurance is provided, and is applied to a terminal device including a main processor. In the use process of the intelligent device, if there is an abnormal power consumption problem caused by application running, a processing strategy is determined through a judgment rule of an abnormal power consumption type and an abnormal power consumption level and power consumption data when the application is running, and abnormal power consumption processing is performed, instead of directly ending or exiting the running application, so that the application can be run while ensuring the device endurance, and the application is suitable for the actual use scene of the intelligent device.

Techniques are disclosed relating to performing remote cache invalidations. In some embodiments, primary processor circuitry is configured to, based on execution of a remote invalidate instruction (e.g., an ISA-defined instruction), send a cache invalidate command to coprocessor circuitry. The coprocessor circuitry includes coprocessor cache circuitry and cache invalidation control circuitry configured to, in response to the cache invalidate command sent by the primary processor, invalidate one or more cache lines in the coprocessor cache circuitry without executing any instructions on the coprocessor circuitry.

The invention belongs to the technical field of avionics, and particularly relates to an architecture design method of a TSN network end system with dual-processor collaboration. The system architecture comprises a main processor and a network card; a buffer A, a register A, a buffer B, a register B, a coprocessor and a protocol conversion module are arranged in the network card; the main processor performs data interaction with a buffer A and a register A in the network card; the coprocessor performs data interaction with a buffer B and a register B in the network card; the protocol conversion module performs data interaction with the buffer A, the register A, the buffer B, the register B and an external network; the main processor is used for receiving an airborne light thunder signal, a sensor signal, an avionics / electromechanical control signal and a graphic video signal, and outputting light thunder sensor data, an avionics / electromechanical control instruction and a graphic video signal; the coprocessor is used for receiving avionics network management data, network time synchronization data and built-in self-inspection data and outputting corresponding data packets.

A computer-implemented method of obtaining user state data and underlying signal data in a wearable device, the wearable device comprising a main processor unit and a lower power processor unit, the method comprising: accessing an indicator of a device sub-state; if the device sub-state is an unknown device sub-state, continuing operation with the main processor unit turned on, and acquiring and processing the first plurality of sensor signals in the main processor unit to acquire user state data; and if the device sub-state is a known device sub-state, continuing operation with the main processor unit off and acquiring and processing a second sensor signal in the lower power processor unit, the second sensor signal being used for the known device sub-state to acquire user state data.

The invention discloses a business processing method and device, and relates to the field of computers. And the main processing core determines the processing core for processing the job according to the load information and the job attribute of each processing core. Thus, the main processing core schedules the operation included in the processing core processing service, a guarantee is provided for the low-power-consumption processing core to process complex services, the service processing range of the low-power-consumption processing core is expanded, the power consumption of the computing device is reduced, and the endurance time of the computing device is prolonged. And the master processing core schedules the master processing core and the slave processing core to process each job in the service so as to process the service, and the master processor and / or the slave processing core are / is adopted to schedule and process the service, so that the time required for processing the service is saved, and the scheduling efficiency of processing the service is improved.

The application discloses a kind of data processing method, device and readable medium based on blockchain, the blockchain includes terminal equipment, and the terminal equipment includes main processor and coprocessor;The method comprises: generating cryptography operation instruction according to business transaction instruction by main processor, and issuing cryptography operation instruction to coprocessor;Cryptography operation instruction is received by coprocessor, and the instruction type of cryptography operation instruction is identified;The instruction type is used to indicate the cryptography operation type corresponding to cryptography operation instruction;Business transaction instruction is executed by main processor, and cryptography operation instruction is executed according to instruction type by coprocessor.This scheme realizes the parallel execution of business transaction and cryptography operation by the collaborative architecture of main processor and integrated coprocessor, greatly improves the overall data processing speed and concurrent capability of blockchain terminal, avoids that main processor is blocked by a large number of cryptography operation tasks.