536 results about "Master processor" patented technology

An embodiment of the present application provides a data processing method, a data processing device, a processor and related devices thereof. The method is applied to a main processor core bound to a network card and configured with a cryptographic coprocessor. By receiving packets to be processed sequentially sent by a network end, network layer processing is then performed to obtain a data vector; the data vector is sequentially recorded in a circular buffer so that the main processor core and the slave processor core can obtain the data vector; after obtaining the data vector, the cryptographic coprocessor is used to perform encryption / decryption processing on the data indicated by the data vector to obtain first result data, and the result information is fed back to the circular buffer; based on the indication of the data vector in the circular buffer, the result data is sent to the network end; the result data includes the first result data and second result data obtained by the slave processor core performing encryption / decryption processing on the data indicated by the data vector using an encryption / decryption program, thereby realizing the full utilization of computing resources.

The invention provides a mud tank liquid level height accurate measurement early warning system and method, the mud tank liquid level height accurate measurement early warning system comprises a measurement support and a control unit comprising a main processor, and the control unit is further connected with a plurality of liquid level detection assemblies, a temperature compensation module, a stirring assembly, an early warning device, a data storage unit and a calibration assembly. The multiple liquid level detection assemblies comprise laser and ultrasonic range finders, the main processor receives detection signals and then corrects the liquid level height in combination with temperature compensation, early warning is started when the liquid level height is abnormal, the detection precision can be calibrated periodically through the calibration assembly, and meanwhile remote data transmission and historical data storage are supported. The method solves the problems that traditional measurement is low in precision, depends on manpower and is delayed in early warning, and is suitable for monitoring the liquid level of the mud tank in various drilling operations.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

The invention discloses an abnormal data real-time filtering method and system based on edge computing in a dynamic environment system, the method is executed by an edge computing gateway, sliding window weighted average preprocessing is equivalently realized by adopting integer shift operation, and the single computing overhead is controlled within 50 clock cycles; dynamically and adaptively adjusting dynamic reference model parameters based on the ratio of the network load to the sensor sampling frequency; performing multi-stage anomaly filtering of a hard threshold value, a mutation rate and a statistical interval on the data through a three-stage pipeline judgment structure executed by atomization; an FPGA hardware queue manager independent of a main processor bypasses a TCP stack to push abnormal data at the highest priority, and redundant data is stored in a zero-copy annular buffer area managed by DMA. According to the invention, the problems of intranet congestion, server I / O bottleneck and alarm delay under the centralized architecture of the traditional dynamic loop system are solved, and the fault, fault, fault, fault, fault and fault are realized on resource-limited platforms such as Cortex-M4 and the like; the average alarm delay is 8 milliseconds; and the data compression rate is more than 90%.

The invention provides a mode switching method and electronic equipment, the mode switching method is applied to the electronic equipment, the electronic equipment comprises a main processor, a coprocessor and an internal memory, operation modes of the electronic equipment comprise a power-saving mode and a working mode, the coprocessor works in the power-saving mode, the main processor does not work, and the internal memory does not work in the working mode. In the working mode, the main processor and the coprocessor work, and the method comprises the steps that first operation is received, and the first operation is used for switching the operation mode of the electronic equipment from the power-saving mode to the working mode; controlling the main processor to be powered on; and obtaining first data from the internal memory, wherein the first data is business data of the main processor stored when the operation mode of the electronic equipment is switched from the working mode to the power saving mode. By adopting the method and the device, the running mode of the electronic equipment can provide due function effects, and the function availability is improved, so that the user experience is improved.

The invention provides a solution for integrating a fault arc detection function into an existing intelligent electric energy meter, and aims at solving the problems that an independent fault arc detection device is low in popularization degree, complex in installation, high in cost, poor in compatibility and the like. The intelligent electric meter comprises a data acquisition module, an electric energy metering module, a fault arc detection sub-module, an A / D conversion module, a storage module, a communication and remote control module, a clock module, a display module, a key module, a power supply module and a main processor module. The data acquisition module acquires voltage and current signals through a voltage transformer and a current transformer, converts the voltage and current signals into digital signals, and extracts high-frequency characteristics and waveform distortion parameters. And the communication and remote control module realizes closed-loop control of fault alarm, user interaction and algorithm optimization. All the modules are coordinated to work through the main processor, and according to a real-time detection result, the following operations are automatically triggered: pushing alarm information; controlling a circuit breaker to cut off a power supply according to a preset threshold; and dynamic upgrading of the fault detection algorithm is completed based on an updating instruction issued by the remote management platform.

The invention provides a current sharing method for multiple power supply racks, which can be applied to the technical field of server power supply current sharing. The current sharing method comprises the following steps: a master controller detects the number of first current power supply units in a plurality of first power supply units and a first total current output quantity, receives the number of second current power supply units in a plurality of second power supply units from a slave controller and a second total current output quantity, and determines a current mean value, a current-sharing signal including a current average value is synchronously issued to the master controller and the plurality of slave controllers; the main processor detects a heartbeat signal of the main controller, controls the first switch module to disconnect the electric connection between the main controller and the plurality of first power supply units and controls the second switch module to disconnect the electric connection between the main controller and the fourth switch module under the condition that the heartbeat signal is not detected within a preset time period; and the second switch module is electrically connected with the plurality of first power supply units and the fourth switch module so as to realize the function of the main controller.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

Disclosed in the present application are a storage format conversion method, system and apparatus, and an electronic device and a storage medium, which are applied to the technical field of storage. The method is applied to a coprocessor. The method comprises: acquiring row storage page data and configuration information, which are sent by a main processor, wherein the configuration information comprises format information of each column field in a row storage page; parsing the row storage page data according to the configuration information, so as to obtain a column descriptor, wherein the column descriptor comprises a first offset address and field length of each column field in the row storage page; performing calculation according to the column descriptor, so as to obtain filling information related to a column storage page, wherein the filling information comprises a first offset address and column length of each data column in the column storage page, and column fields with the same field attribute form a data column; filling the column storage page according to the filling information, so as to generate column storage page data; and feeding back the column storage page data to the main processor. The row-column storage format conversion of variable-length field data can be supported, thereby improving the applicability of a row-column conversion method.

The invention discloses a cloud edge collaborative information interaction processing device, method and system with an endogenous security architecture. The equipment comprises a main processor, a hardware security chip, a programmable logic unit, a communication unit and an equipment management unit. A trusted execution environment is constructed in the hardware security chip and is in isolated communication with a common execution environment of the main processor through a security bus, a security computing engine, a remote attestation module and a trusted key warehouse are arranged in the trusted execution environment, and the programmable logic unit is directly controlled by the trusted execution environment to realize dynamic hardware acceleration. The communication unit is provided with independent interfaces which are connected with the two execution environments respectively, unification of hardware-level security isolation and efficient cooperative computing is achieved, and the problems of privacy disclosure and untrusted process in cloud edge collaboration are solved.

The invention provides a synchronous communication device and method based on multiple coprocessors, equipment and a storage medium. The device comprises a main processor which is configured to send a communication instruction to a primary buffer; the cache controller is configured to distribute the communication instruction from the first-level cache to the first second-level cache and the second second-level cache; the first coprocessor is configured to read the communication instruction from the first second-level buffer and configure the communication instruction to the first terminal node; the second coprocessor is configured to read the communication instruction from the second secondary buffer and configure the communication instruction to a second terminal node; and the synchronous triggering module is configured to control the first terminal node and the second terminal node to perform synchronous communication according to the communication instruction to obtain a communication result. Therefore, the first coprocessor and the second coprocessor can simultaneously configure the corresponding terminal nodes, so that the instruction sending time is shortened, and optical fiber bus communication for spaceflight control can be accelerated through the multiple coprocessors.

The invention discloses a camera master control FPGA (Field Programmable Gate Array) multi-mode on-orbit program upgrading method based on dynamic reconstruction, relates to the technical field of camera master control processor program on-orbit upgrading, and solves the problem of upgrading of a master control processor FPGA in an existing camera master control single machine. According to the method, on-orbit program upgrading can be carried out on the camera master control main processor FPGA by adopting six modes based on a dynamic reconstruction strategy according to a stand-alone upgrading feedback result. When the DSP breaks down, on-orbit upgrading of an FPGA program can still be achieved through three modes of functions of the FPGA, when the FPGA breaks down, on-orbit upgrading of the FPGA program is achieved through one of the two upgrading modes of the DSP, in this way, even if the FPGA cannot load the program, on-orbit upgrading of the FPGA program can be achieved, and then the FPGA can recover working after the camera main control single machine is restarted. The problem that a camera master control single machine cannot meet task requirements due to upgrading failure caused by a single-mode upgrading method is avoided.

The invention discloses an automatic calibration intelligent horizontal bending machine and relates to the technical field of horizontal bending machines, the automatic calibration intelligent horizontal bending machine comprises a workbench, a top plate and a fixing box, supporting rods are installed at the four corners of the top of the workbench, the top plate is installed at the tops of the supporting rods, and the tail end of the top of the workbench is fixedly connected with the fixing box. The supporting rods and the top plate are mounted at the top of the workbench, and the laser displacement sensor is arranged at the bottom of the top plate, so that displacement data of a bent plate and all structures of the workbench are accurately obtained, and the laser displacement sensor transmits the collected data to the main processor module in real time; the main processor module sends an instruction to the PLC after analysis, the PLC drives a first servo motor in the execution mechanism to work according to the instruction, the first servo motor is meshed with a rack through a first transmission gear at the output end of the first servo motor, a moving rod is driven to slide in a moving groove of the fixing box, and then the position of the calibration plate is adjusted. And an automatic calibration task is completed.

The invention discloses a multi-mode anti-springback numerical control plate rolling machine, and relates to the technical field of plate rolling machines, the multi-mode anti-springback numerical control plate rolling machine comprises a plate rolling machine shell, a conveyor shell and a first hydraulic telescopic cylinder, a fixing block is mounted in the middle of one side of the inner bottom wall of the plate rolling machine shell, and driven rollers are mounted on one side of the plate rolling machine shell and the other side of the fixing block through bearings. By integrating the image acquisition module and the laser ranging module, the system can accurately acquire the length, moving state and height information of a plate in real time, and after the information is processed by a preset algorithm of the main processor module, the PLC can be accurately guided to adjust the first hydraulic telescopic cylinder and the second hydraulic telescopic cylinder; therefore, accurate control over the positions of the movable roller and the driving roller is achieved, the accuracy and machining precision of plate bending forming can be improved, meanwhile, different plate rolling modes can be applied to the equipment when the equipment is used for coping with plates of different specifications, and the plate rolling efficiency is improved.

The invention provides an extensible near-memory computing coprocessor architecture for a computing system. The architecture comprises a main processor; the storage module comprises a plurality of storage particles, and the storage module is configured to store calculation data required by the main processor; the at least one near memory coprocessor is integrated with all the storage particles through 2D, and the interface protocol of the near memory coprocessor architecture is the same as the interface protocol of the storage particles; the near-memory coprocessor is configured to perform near-memory computation on a storage-intensive computation task and store a result of the near-memory computation into the storage particle. Through the framework, the problem that the efficiency is low when an existing processor framework processes memory access intensive tasks is solved.

The invention provides a starting method, related equipment and a readable storage medium, and is applied to the technical field of computers, the method is applied to a system-on-chip configured with a main processor and a bus monitoring module, the bus monitoring module provides an initialization operation sequence, and the operation sequence of the main processor is initialized based on the pre-stored initialization operation sequence. The bus monitoring module initializes the main processor and awakens the main processor after a first starting address of the main processor is configured, the first starting address is obtained after the main processor is awakened, and target starting firmware needing to be executed after the main processor is initialized is executed according to the first starting address. And the bus monitoring module initializes the main processor by using the pre-stored initialization operation sequence and skips a BL1 stage and a BL33 stage, so that the interaction times of BL1 firmware and BL33 firmware in the initialization process of the processor are reduced, the exposure risk is reduced, and the running safety of the processor is improved.

The invention discloses a data transmission method and device, electronic equipment and a storage medium, and belongs to the technical field of communication. The method comprises the steps that a first data frame is sent to a coprocessor through a main processor, the first data frame is used for controlling the main processor to write or read data to the coprocessor, the first data frame carries an address increasing identifier, and the address increasing identifier is used for indicating the coprocessor to start writing or reading data from a starting register in N registers, n is an integer greater than 1; and writing or reading data in the N registers from the starting register based on the address increase identification through the coprocessor.

A scalable AI system includes a plurality of slots on a main board, at least one AI module mounted in the slots to perform AI operations, and a main processor that controls the entire system. A user can flexibly scale the overall AI computation performance of the system by adjusting the number of AI modules as needed. Each AI module is equipped with a low-power NPU specialized for AI operations and adopts standard form factors (e.g., M.2, E1.S) to improve economy and scalability. This can solve the problems of high-power consumption and cost, which are limitations of GPU-based systems, and can efficiently support various AI applications.

The invention discloses an activity identification method based on conditional antagonism data enhancement, which comprises three parts of a conditional generative adversarial network, a kinematic feature constraint module and a prototype sample generator, a system hardware structure is designed based on an embedded heterogeneous computing platform, a main processor adopts an ARM Cortex-A72 core operation condition generative adversarial network, and the model sample generator is designed based on an embedded heterogeneous computing platform. The coprocessor adopts NPU to accelerate kinematics parameter calculation, and the sensor interface module is connected with a six-axis IMU sensor through an SPI bus to collect data of an accelerometer and a gyroscope in real time. According to the activity recognition method based on conditional antagonism data enhancement, enhancement data with diversity, authenticity and semantic accuracy can be provided for a human body activity recognition model in a scene of insufficient training data, so that the overall recognition accuracy of the model on a UCI HAR data set is improved by 14.7%, the F1 value on the aspect of few sample categories is averagely improved by 21.3%, and the recognition accuracy of the model on the UCI HAR data set is greatly improved. And an effective technical solution is provided for data scarce scenes such as medical monitoring and motion analysis.

The invention discloses an intelligent box, intelligent glasses and split type intelligent glasses, and relates to the technical field of intelligent glasses, the intelligent box comprises a first connection module and a main processor, the first connection module is used for realizing communication connection between the intelligent box and the intelligent glasses; the main processor is electrically connected with the first connection module, and the main processor is used for receiving and processing a first signal output by the intelligent glasses and outputting a second signal to the intelligent glasses, so that the intelligent glasses respond to the second signal and execute a corresponding action. According to the technical scheme provided by the invention, the computing power center and part of functional modules of the intelligent glasses are moved outwards, so that the weight of the intelligent glasses is reduced, and the user experience is improved.

The invention relates to the technical field of surface temperature measurement based on an infrared radiation principle, and discloses a non-contact surface temperature measurement device which realizes surface temperature measurement through cooperation of a plurality of components. The optical system is located in front of the infrared detector, the field angle is determined, infrared radiation is focused, and a 3D printing black sealing shell of the optical system is rainproof and windproof. The infrared radiation detector of the MLX90614 chip converts infrared energy into a voltage signal and processes data, the data is sent to the main processor through the signal conditioning circuit for analog-to-digital conversion and other operations, and the sensor is endowed with digital and intelligent characteristics. The communication module comprises an RS-232 serial port and a ZigBee wireless communication module and is used for data transmission and connection with an upper computer, and the state monitoring module monitors the work of the processor. Hardware design is completed by using an embedded system and a ZigBee technology, software design is realized by IAR and Z-Stack protocol stacks, and the surface temperature can be accurately measured. The device also has two-way communication and online upgrading functions, the emissivity and the distance are corrected through an algorithm, the efficiency is improved, the standard requirements are met, and meteorological observation and ground temperature measurement are assisted.

The invention discloses a multiprocessor architecture intelligent adaptive base plate of a nuclear power DCS controller, and relates to the field of nuclear power control, and the base plate comprises a signal processing module which is used for collecting and preprocessing each path of signal and then realizing bidirectional data communication with a core board card main processor; the PCIE network controller expansion module is used for realizing gigabit network interface expansion; the storage module is used for storing data; the redundancy synchronization module is used for realizing redundancy switching and network synchronization of the main controller and the standby controller; the bottom plate power supply system is used for providing voltage; the bottom plate clock system is used for providing time information; the connector is used for connecting the core board card and the backboard; and each peripheral module. Each peripheral module comprises a USB module, a serial port module, a network module, an output driving module, an isolation communication module and a B code circuit module. According to the method, the compatibility can be improved, the complexity and cost of system upgrading are reduced, and the flexibility of technical iteration is improved.

Systems and methods are disclosed for automating firmware updating on a computing system. Specifically, the aspects and features disclosed allow a baseboard management controller (BMC) to automatically step through the local firmware versions of various components of a computing system and compare those versions with up-to-date firmware versions to see whether any of the local firmware versions should be replaced with the respective up-to-date firmware version. The up-to-date firmware versions can be obtained from vendor firmware server(s) either locally by the computing system (e.g., by a BMC or main processor of the computing system) or remotely. When up-to-date firmware versions are obtained remotely, a facilitator system can obtain the up-to-date firmware versions and save them to a removable storage device, which can be temporarily coupled to the BMC of the computing system to automatically update the firmware of the components of that computing system.

A cell matching system capable of extending the life of a battery pack belongs to the technical field of control systems, and particularly relates to a cell matching system capable of extending the life of a battery pack. The present invention provides a circuit hardware basis for a cell matching system capable of extending the life of a battery pack. The present invention includes a local host processor part, a node host and touch screen connection communication part, a host RS485 communication part, a node data upload part, a node host power supply part, a battery charging current acquisition part, a battery voltage acquisition part, a battery charge and discharge circuit part, an ADC acquisition post-filtering circuit part, a slave processor part, a slave RS485 communication part, a slave power supply part, a slave cell temperature control circuit part, and a battery discharge current ADC conversion circuit part.

The invention discloses a platform heterogeneous inter-core communication method and device and communication equipment, and the method comprises the steps: a main processor carries out initialization, and the initialization comprises the steps: determining a shared memory region, dividing the shared memory region into a plurality of cache regions, writing the addresses and use information of the cache regions into a resource table, and storing the resource table into a shared memory; establishing an RPMsg channel with the slave processor in the shared memory through the service announcement message; when communication is needed, determining a cache region which can be used by the to-be-transmitted message according to the resource table; and performing message interaction with the slave processor by using the determined cache region and the RPMsg channel. By means of the scheme, the inter-core communication of the multi-core heterogeneous system can meet the requirements of ecological expansion and development, and secondary development of the system is facilitated.

The invention provides an extensible near-memory computing coprocessor architecture for a computing system. The architecture comprises a main processor; the storage module comprises a plurality of storage particle layers, each storage particle layer comprises a plurality of storage particles, and the storage module is configured to store calculation data required by the main processor; the at least one near-memory coprocessor is integrated with the at least two storage particle layers through 3D, and the interface protocol of the near-memory coprocessor architecture is the same as the interface protocol of the storage particles; the near-memory coprocessor is configured to perform near-memory computation on a storage-intensive computation task and store a result of the near-memory computation into the storage particle. Through the framework, the problem that the efficiency is low when an existing processor framework processes memory access intensive tasks is solved.

The invention belongs to the field of edge computing, and discloses an edge intelligent computing device and method supporting multi-level storage and computing integrated acceleration, and the device comprises a main processor system, a near memory computing module and a near flash memory computing module. The near memory calculation module integrates an NPU (Network Processing Unit) with a distributed SRAM (Static Random Access Memory) and an HBM DRAM (Dynamic Random Access Memory) with an MAC (Media Access Control) array, and realizes high-throughput reasoning acceleration And the near flash memory calculation module is used for tightly coupling the SSD controller and the retrieval acceleration engine to realize the nearest retrieval acceleration of mass data at the SSD level. All the modules are interconnected through a PCIe bus, a three-level storage and calculation integrated framework of SRAM-HBM DRAM-SSD is constructed, cross-level data migration is effectively reduced, and the bottleneck of the PCIe bus is avoided. According to the method, high-throughput video reasoning and TB-level data retrieval tasks on the edge side can be efficiently supported at the same time, and the calculation energy efficiency ratio and the system throughput rate are remarkably increased.

The embodiment of the invention provides a push message processing method and electronic equipment. The electronic equipment comprises a main processor and a coprocessor. In the method, the coprocessor receives a push message, the coprocessor processes the push message, or the coprocessor sends the push message to the main processor, so that the main processor processes the push message. According to the embodiment of the invention, the power consumption of the push service to the electronic equipment can be reduced, and the standby time of the electronic equipment is prolonged.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.