671 results about "Master processor" patented technology

A vehicle electronic control device, which is mounted on a vehicle and executing a predetermined function of the vehicle, includes a main processor; a sub processor; and a storing unit. The storing unit compares a first calculation result of calculated by the main processor with a second calculation result calculated by the sub processor. When a deviation between the first and second calculation results satisfies a predetermined deviation condition, the storing unit stores, in a storage medium, a data set indicating a situation when the first and second calculation results having the deviation therebetween is acquired. The data set includes at least one of (i) input data or (ii) the first and second calculation results.

Embodiments of the present application relate to the technical field of generation of fault locating information, and provide a method and apparatus for generating fault locating information, an electronic device, and a storage medium. The method comprises: configuring a first operating system for a coprocessor, and configuring a second operating system for a main processor, the first operating system and the second operating system being different operating systems; when a fault signal for a server is acquired by means of the main processor, sending the fault signal to the first operating system by means of the second operating system; and generating fault locating information for the server by means of the first operating system on the basis of the fault signal. Excessively occupying the main processor when the server is subjected to fault locating is effectively avoided, improving the data processing efficiency of the processor.

The embodiment of the invention discloses a taint analysis method and device, computer equipment and a storage medium, and belongs to the technical field of information security. In the application, the coprocessor of the computer equipment comprises a plurality of registers, and the plurality of registers not only can be used for storing stain information corresponding to a plurality of general registers in a main processor of the computer equipment, but also can be used for storing stain information corresponding to a program memory space of a target program currently executed by the main processor. Therefore, when the coprocessor performs taint propagation on the first instruction, the taint information of the operand of the first instruction can be accessed by accessing the plurality of registers, and compared with the mode of accessing the taint information by accessing a memory, the operation is simpler, the speed is faster, and the performance overhead is smaller.

The invention relates to a coprocessor based on an RISC-V architecture and a processing system thereof. The coprocessor comprises a decoding unit, a control unit, an arithmetic unit, a cross-clock transmission unit and a cache unit. The decoding unit receives the value of the source register sent by the main processor and decodes the value to output an operation parameter, the control unit controls the working process of the operation unit based on the operation parameter, and the cross-clock transmission unit communicates with the main processor and comprises transmission of configuration parameters and feedback signals. Therefore, the main coprocessor can run in different clock domains; the cache unit is used for caching part of weight data and all bias data required in single operation, can be used for realizing operation of an expansion instruction, does not occupy the storage space of the main processor, and greatly improves the operation efficiency of the neural network.

The invention belongs to the technical field of storage and calculation integration, and particularly discloses a three-dimensional storage and calculation integration system and an operation method thereof, and the system comprises an input module which has an input end connected to an output end of a main processor and is used for converting to-be-processed data into an analog voltage signal; the input end of the memristor array is connected to the output end of the input module, and the memristor array is used for carrying out matrix vector multiplication or matching operation on pre-stored operation data and the analog voltage signal and outputting a first operation result of the data to be processed; the input end of the sensing module is connected to the output end of the memristor array, and the sensing module is used for converting the first operation result into a corresponding digital signal based on the signal form of the first operation result; and the main processor is used for analyzing the digital signal and determining a second operation result of the data to be processed. According to the invention, the storage area and power consumption of the system can be effectively reduced, and the operation speed and efficiency of the system are improved.

An embodiment of the present application provides a data processing method, a data processing device, a processor and related devices thereof. The method is applied to a main processor core bound to a network card and configured with a cryptographic coprocessor. By receiving packets to be processed sequentially sent by a network end, network layer processing is then performed to obtain a data vector; the data vector is sequentially recorded in a circular buffer so that the main processor core and the slave processor core can obtain the data vector; after obtaining the data vector, the cryptographic coprocessor is used to perform encryption / decryption processing on the data indicated by the data vector to obtain first result data, and the result information is fed back to the circular buffer; based on the indication of the data vector in the circular buffer, the result data is sent to the network end; the result data includes the first result data and second result data obtained by the slave processor core performing encryption / decryption processing on the data indicated by the data vector using an encryption / decryption program, thereby realizing the full utilization of computing resources.

The invention discloses a train signal processing method, system and device which are applied to the technical field of rail transit, a master processor and a slave processor are in communication connection, and a first hardware device sends time synchronization hard line signals to the master processor and the slave processor at the same time. The train signal processing method comprises the steps that whether first collection data received through a first input channel is consistent with second collection data sent by a processor or not is judged; if not, entering a guiding safety state; if yes, data processing operation is executed, and a first processing result is obtained and executed; the first acquisition data and the second acquisition data are respectively data of a target position acquired by the master processor and the slave processor at a first moment. According to the scheme, the reliability of the train signal processing process is guaranteed through the arrangement of the master processor and the slave processor, time synchronization of the master processor and the slave processor is achieved through the time synchronization hard line signals, and the response time of the train signal processing process is saved.

The invention provides a mud tank liquid level height accurate measurement early warning system and method, the mud tank liquid level height accurate measurement early warning system comprises a measurement support and a control unit comprising a main processor, and the control unit is further connected with a plurality of liquid level detection assemblies, a temperature compensation module, a stirring assembly, an early warning device, a data storage unit and a calibration assembly. The multiple liquid level detection assemblies comprise laser and ultrasonic range finders, the main processor receives detection signals and then corrects the liquid level height in combination with temperature compensation, early warning is started when the liquid level height is abnormal, the detection precision can be calibrated periodically through the calibration assembly, and meanwhile remote data transmission and historical data storage are supported. The method solves the problems that traditional measurement is low in precision, depends on manpower and is delayed in early warning, and is suitable for monitoring the liquid level of the mud tank in various drilling operations.

The invention relates to the technical field of computer encryption, and discloses a fully homomorphic encryption system based on a coprocessor architecture, which comprises a main processor, a coprocessor realized by an FPGA (Field Programmable Gate Array) and an upper computer, in the coprocessor, a data transmission and storage module is connected with a block random access memory through an on-chip bus to store data; the encryption module is used for encoding and encrypting the data; the KNN algorithm implementation module is used for performing distance calculation and sorting on ciphertext or plaintext data; the decryption module is used for decrypting and decoding the encrypted classification result based on a key issued by the upper computer; and the FPGA main processing module is used for controlling data input selection and comparing classification results. Through the control of the FPGA main processing module, the standardized data processing flow and the hardware collaborative architecture, the problem of difficulty in chip branch prediction is solved, and the stability and the safety of data processing are improved.

The invention relates to the technical field of converters, in particular to a three-phase converter control method and system, a medium and equipment. The method comprises the steps that a main processor transmits sampling original data of a three-phase converter to a first storage area; the coprocessor reads the sampled original data, performs operation to obtain operation result data, and transmits the operation result data to the second storage area; the coprocessor runs at a period higher than the preset control frequency of the main processor, and immediately triggers the operation of the sampled original data after completing the collection of the sampled original data; the main processor performs control loop calculation, reads the operation result data when the newest operation result data is needed, and loads the newest operation result data for updating operation; the main processor runs the control program at the preset control frequency, and the control program triggering time is set in a minimum allowable time window before the control output quantity loading moment. Through the above arrangement, real-time sampling is effectively realized, CPU load is optimized, and the control performance of the converter is improved.

The invention relates to a satellite navigation baseband processing device optimized by a coprocessor. A core processing part of the device adopts a realization framework of a main processor and a coprocessor; the coprocessor is used for scheduling hardware acceleration computing resources in real time under exchange control of the main processor, and completing high-real-time processing tasks such as signal capture and tracking loop processing of satellite navigation; an instruction set and an external interface of the coprocessor are subjected to targeted optimization, the bus bit width and the internal storage width of the coprocessor are expanded, and the in-situ width of an ALU and a register of the coprocessor is reserved; performing bus data access and storage by adopting an external port access instruction and an internal memory access instruction which are matched with the expanded bus according to the expansion state; and performing access and storage of single register data by adopting a bus write enable, an access instruction and a storage instruction which are matched with the expanded internal storage width. According to the invention, the function load of the main processor is effectively reduced, and the implementation cost of the baseband processing device is reduced.

The invention discloses an abnormal data real-time filtering method and system based on edge computing in a dynamic environment system, the method is executed by an edge computing gateway, sliding window weighted average preprocessing is equivalently realized by adopting integer shift operation, and the single computing overhead is controlled within 50 clock cycles; dynamically and adaptively adjusting dynamic reference model parameters based on the ratio of the network load to the sensor sampling frequency; performing multi-stage anomaly filtering of a hard threshold value, a mutation rate and a statistical interval on the data through a three-stage pipeline judgment structure executed by atomization; an FPGA hardware queue manager independent of a main processor bypasses a TCP stack to push abnormal data at the highest priority, and redundant data is stored in a zero-copy annular buffer area managed by DMA. According to the invention, the problems of intranet congestion, server I / O bottleneck and alarm delay under the centralized architecture of the traditional dynamic loop system are solved, and the fault, fault, fault, fault, fault and fault are realized on resource-limited platforms such as Cortex-M4 and the like; the average alarm delay is 8 milliseconds; and the data compression rate is more than 90%.

The invention discloses a general parallel computing architecture co-processing system based on RISC-V, belongs to the technical field of digital integrated circuits, and is used for solving the problems of low computing speed and complex data propagation path in the prior art. A universal parallel operation module, a scheduling module and a shared memory; the scheduling module receives an operation request sent by the RISC-V main processor, and schedules the shared memory and controls the universal parallel operation module according to decoding information; and the universal parallel operation module performs operation on the data in the shared memory to obtain an operation result, and writes the operation result back to the shared memory. According to the method, multiple complex algorithms such as multiplication, floating point, vector and matrix are supported at the same time based on the general parallel computing architecture, support of other computing coprocessors is not needed, hardware computing resources are reused to the maximum extent in the general parallel computing architecture, hardware redundancy is reduced, non-parallel computing is optimized by utilizing the advantages of the parallel architecture, the computing speed is increased, and the computing cost is reduced. A data propagation path is optimized, and redundant data reading and writing in the transmission process are reduced.

The invention provides a mode switching method and electronic equipment, the mode switching method is applied to the electronic equipment, the electronic equipment comprises a main processor, a coprocessor and an internal memory, operation modes of the electronic equipment comprise a power-saving mode and a working mode, the coprocessor works in the power-saving mode, the main processor does not work, and the internal memory does not work in the working mode. In the working mode, the main processor and the coprocessor work, and the method comprises the steps that first operation is received, and the first operation is used for switching the operation mode of the electronic equipment from the power-saving mode to the working mode; controlling the main processor to be powered on; and obtaining first data from the internal memory, wherein the first data is business data of the main processor stored when the operation mode of the electronic equipment is switched from the working mode to the power saving mode. By adopting the method and the device, the running mode of the electronic equipment can provide due function effects, and the function availability is improved, so that the user experience is improved.

The invention provides a solution for integrating a fault arc detection function into an existing intelligent electric energy meter, and aims at solving the problems that an independent fault arc detection device is low in popularization degree, complex in installation, high in cost, poor in compatibility and the like. The intelligent electric meter comprises a data acquisition module, an electric energy metering module, a fault arc detection sub-module, an A / D conversion module, a storage module, a communication and remote control module, a clock module, a display module, a key module, a power supply module and a main processor module. The data acquisition module acquires voltage and current signals through a voltage transformer and a current transformer, converts the voltage and current signals into digital signals, and extracts high-frequency characteristics and waveform distortion parameters. And the communication and remote control module realizes closed-loop control of fault alarm, user interaction and algorithm optimization. All the modules are coordinated to work through the main processor, and according to a real-time detection result, the following operations are automatically triggered: pushing alarm information; controlling a circuit breaker to cut off a power supply according to a preset threshold; and dynamic upgrading of the fault detection algorithm is completed based on an updating instruction issued by the remote management platform.

The invention provides a current sharing method for multiple power supply racks, which can be applied to the technical field of server power supply current sharing. The current sharing method comprises the following steps: a master controller detects the number of first current power supply units in a plurality of first power supply units and a first total current output quantity, receives the number of second current power supply units in a plurality of second power supply units from a slave controller and a second total current output quantity, and determines a current mean value, a current-sharing signal including a current average value is synchronously issued to the master controller and the plurality of slave controllers; the main processor detects a heartbeat signal of the main controller, controls the first switch module to disconnect the electric connection between the main controller and the plurality of first power supply units and controls the second switch module to disconnect the electric connection between the main controller and the fourth switch module under the condition that the heartbeat signal is not detected within a preset time period; and the second switch module is electrically connected with the plurality of first power supply units and the fourth switch module so as to realize the function of the main controller.

The invention provides a task processing method and device, electronic equipment and a storage medium, the method is applied to a coprocessor of a first heterogeneous system, the first heterogeneous system further comprises a main processor, the main processor and the coprocessor are in communication connection, and the method comprises the steps that a task request of the main processor is received; selecting in the processor list according to the type of the task request to obtain a communication list, the processor list comprising a plurality of second heterogeneous systems, and the second heterogeneous systems being heterogeneous systems in network connection with the first heterogeneous system; sending the cooperation request to a coprocessor in a target heterogeneous system, wherein the target heterogeneous system is a plurality of heterogeneous systems in the communication list; and receiving the return data of the coprocessor in the target heterogeneous system, and sending the return data to the main processor, thereby relieving the situation that the response is not timely or wrong when the main processor is in shortage of resources.

The invention provides a master control system for energy storage battery management. The master control system comprises a main processor, and a high-voltage detection circuit, a driving control circuit and an input detection circuit which are electrically connected with the main processor. The high-voltage detection circuit comprises a total voltage detection circuit and an insulation detection circuit, and the insulation detection circuit adopts an unbalanced bridge method and can detect insulation resistance; the total voltage detection circuit divides the input total voltage through a resistor and then converts the total voltage through a digital-to-analog converter, and the main processor and the digital-to-analog converter perform information interaction through an isolation chip to obtain a conversion value; the driving control circuit comprises a high-side driving chip, a channel is selected based on an IS pin of the high-side driving chip, current is output, and the main processor monitors the state of the monitoring equipment in real time by detecting the voltage of the IS pin; and the input detection circuit comprises multiple paths of digital and analog input detection circuits and is used for performing dual detection and proofreading on detection data. The system is rich in function and high in adaptability, and can be used for energy storage systems under various use conditions.

The invention provides an algorithm-agile post quantum cryptography system and a working method thereof.The system comprises a hardware platform and a software system, the hardware platform comprises a main processor, the main processor comprises a multi-core CPU, a GPU and a PCIe interface, and the software system comprises a password master control module, a PCIe-EP driving module, a PQC algorithm module, a GPU acceleration module and an algorithm upgrading module. The password master control module receives a PQC algorithm request message of an external host through the PCIe-EP driving module, sends the PQC algorithm request message to the PQC algorithm module and the GPU acceleration module for multi-thread asynchronous acceleration processing, and returns a processing result to the external host through the PCIe interface. According to the algorithm-agile post quantum cryptography system and the working method provided by the invention, the problems that a traditional password card cannot quickly support the PQC algorithm and cannot be quickly reconstructed when the PQC algorithm is updated in the process that the password system migrates to the post quantum cryptography can be solved.

The invention provides a high-efficiency matrix engine (RVME) architecture based on RISC-V matrix extension and a calculation method, and the architecture comprises an instruction buffering and decoding module, a matrix loading / storage module, a matrix register file, a parallel outer product array and an element-by-element operation module; the matrix register file comprises a Tile register and an Acculator register; the storage modules are respectively used for storing an input matrix and an accumulation result and supporting efficient data access and parallel computing; the matrix loading / storage module significantly improves the data loading efficiency through cache line alignment and matrix transposition optimization; the instruction buffering and decoding module cooperates with a main processor through a reordering buffer area and an instruction buffer area to ensure efficient scheduling and execution of instructions. The parallel outer product array is adopted to replace a traditional systolic array, the idle period in the calculation process is eliminated through multicast data flow scheduling and a ping-pong buffer read-write mechanism, and matrix multiplication and addition operation with high calculation utilization rate and low delay is achieved.

Disclosed in the present application are a storage format conversion method, system and apparatus, and an electronic device and a storage medium, which are applied to the technical field of storage. The method is applied to a coprocessor. The method comprises: acquiring row storage page data and configuration information, which are sent by a main processor, wherein the configuration information comprises format information of each column field in a row storage page; parsing the row storage page data according to the configuration information, so as to obtain a column descriptor, wherein the column descriptor comprises a first offset address and field length of each column field in the row storage page; performing calculation according to the column descriptor, so as to obtain filling information related to a column storage page, wherein the filling information comprises a first offset address and column length of each data column in the column storage page, and column fields with the same field attribute form a data column; filling the column storage page according to the filling information, so as to generate column storage page data; and feeding back the column storage page data to the main processor. The row-column storage format conversion of variable-length field data can be supported, thereby improving the applicability of a row-column conversion method.

The invention discloses a cloud edge collaborative information interaction processing device, method and system with an endogenous security architecture. The equipment comprises a main processor, a hardware security chip, a programmable logic unit, a communication unit and an equipment management unit. A trusted execution environment is constructed in the hardware security chip and is in isolated communication with a common execution environment of the main processor through a security bus, a security computing engine, a remote attestation module and a trusted key warehouse are arranged in the trusted execution environment, and the programmable logic unit is directly controlled by the trusted execution environment to realize dynamic hardware acceleration. The communication unit is provided with independent interfaces which are connected with the two execution environments respectively, unification of hardware-level security isolation and efficient cooperative computing is achieved, and the problems of privacy disclosure and untrusted process in cloud edge collaboration are solved.

The invention provides a synchronous communication device and method based on multiple coprocessors, equipment and a storage medium. The device comprises a main processor which is configured to send a communication instruction to a primary buffer; the cache controller is configured to distribute the communication instruction from the first-level cache to the first second-level cache and the second second-level cache; the first coprocessor is configured to read the communication instruction from the first second-level buffer and configure the communication instruction to the first terminal node; the second coprocessor is configured to read the communication instruction from the second secondary buffer and configure the communication instruction to a second terminal node; and the synchronous triggering module is configured to control the first terminal node and the second terminal node to perform synchronous communication according to the communication instruction to obtain a communication result. Therefore, the first coprocessor and the second coprocessor can simultaneously configure the corresponding terminal nodes, so that the instruction sending time is shortened, and optical fiber bus communication for spaceflight control can be accelerated through the multiple coprocessors.

The invention discloses a camera master control FPGA (Field Programmable Gate Array) multi-mode on-orbit program upgrading method based on dynamic reconstruction, relates to the technical field of camera master control processor program on-orbit upgrading, and solves the problem of upgrading of a master control processor FPGA in an existing camera master control single machine. According to the method, on-orbit program upgrading can be carried out on the camera master control main processor FPGA by adopting six modes based on a dynamic reconstruction strategy according to a stand-alone upgrading feedback result. When the DSP breaks down, on-orbit upgrading of an FPGA program can still be achieved through three modes of functions of the FPGA, when the FPGA breaks down, on-orbit upgrading of the FPGA program is achieved through one of the two upgrading modes of the DSP, in this way, even if the FPGA cannot load the program, on-orbit upgrading of the FPGA program can be achieved, and then the FPGA can recover working after the camera main control single machine is restarted. The problem that a camera master control single machine cannot meet task requirements due to upgrading failure caused by a single-mode upgrading method is avoided.

The invention discloses a convolutional neural network acceleration processing system based on RISC-V. The convolutional neural network acceleration processing system comprises a main processor and a coprocessor, the main processor is used for sending a self-defined input data instruction to the coprocessor, and the coprocessor is used for sending a storage request signal to the main processor based on the input data instruction; the main processor is used for loading input data stored in the data tight coupling memory of the main processor into the coprocessor based on the storage request signal, and the coprocessor is used for caching the input data; after the loading of the input data is completed, the main controller is used for sending a convolution operation instruction to the coprocessor; the coprocessor is used for performing convolution calculation on input data based on the convolution operation instruction to obtain and cache output data; the main processor is also used for sending an output data instruction to the coprocessor; the co-processor is further to write back the output data to the main processor based on the output data instruction. According to the invention, the problems of low CPU computing parallelism and over-high GPU power consumption can be solved.

The invention discloses an automatic calibration intelligent horizontal bending machine and relates to the technical field of horizontal bending machines, the automatic calibration intelligent horizontal bending machine comprises a workbench, a top plate and a fixing box, supporting rods are installed at the four corners of the top of the workbench, the top plate is installed at the tops of the supporting rods, and the tail end of the top of the workbench is fixedly connected with the fixing box. The supporting rods and the top plate are mounted at the top of the workbench, and the laser displacement sensor is arranged at the bottom of the top plate, so that displacement data of a bent plate and all structures of the workbench are accurately obtained, and the laser displacement sensor transmits the collected data to the main processor module in real time; the main processor module sends an instruction to the PLC after analysis, the PLC drives a first servo motor in the execution mechanism to work according to the instruction, the first servo motor is meshed with a rack through a first transmission gear at the output end of the first servo motor, a moving rod is driven to slide in a moving groove of the fixing box, and then the position of the calibration plate is adjusted. And an automatic calibration task is completed.

The invention discloses a multi-mode anti-springback numerical control plate rolling machine, and relates to the technical field of plate rolling machines, the multi-mode anti-springback numerical control plate rolling machine comprises a plate rolling machine shell, a conveyor shell and a first hydraulic telescopic cylinder, a fixing block is mounted in the middle of one side of the inner bottom wall of the plate rolling machine shell, and driven rollers are mounted on one side of the plate rolling machine shell and the other side of the fixing block through bearings. By integrating the image acquisition module and the laser ranging module, the system can accurately acquire the length, moving state and height information of a plate in real time, and after the information is processed by a preset algorithm of the main processor module, the PLC can be accurately guided to adjust the first hydraulic telescopic cylinder and the second hydraulic telescopic cylinder; therefore, accurate control over the positions of the movable roller and the driving roller is achieved, the accuracy and machining precision of plate bending forming can be improved, meanwhile, different plate rolling modes can be applied to the equipment when the equipment is used for coping with plates of different specifications, and the plate rolling efficiency is improved.

The invention provides an extensible near-memory computing coprocessor architecture for a computing system. The architecture comprises a main processor; the storage module comprises a plurality of storage particles, and the storage module is configured to store calculation data required by the main processor; the at least one near memory coprocessor is integrated with all the storage particles through 2D, and the interface protocol of the near memory coprocessor architecture is the same as the interface protocol of the storage particles; the near-memory coprocessor is configured to perform near-memory computation on a storage-intensive computation task and store a result of the near-memory computation into the storage particle. Through the framework, the problem that the efficiency is low when an existing processor framework processes memory access intensive tasks is solved.

The invention discloses a low-power-consumption standby intelligent awakening control system and method for a percussion drill, and particularly relates to the technical field of percussion drills. A user operation signal and an external interference signal are accurately distinguished by using a built-in classification model in combination with the frequency characteristic, the duration and the mode of a vibration signal, and an accurate wake-up signal is triggered; according to a real-time evaluation result of the classification model, a threshold value of a wake-up condition is dynamically adjusted, system adaptability is improved, and a main processor and a high-power-consumption module are rapidly activated after confirmation of a user operation signal; if the false wake-up behavior is recognized, the device can automatically recover the low-power-consumption mode, and the false wake-up characteristics are recorded, the problems that in the prior art, external interference signals are sensitive, false wake-up is frequent, and consequently battery loss and insufficient endurance are caused are effectively solved, and the operation efficiency and the endurance capacity of the device in the complex environment are remarkably improved.

The invention relates to the technical field of computer data, in particular to a floating point data processing method and device, computer equipment and a storage medium. The floating point data processing method is applied to a main processor, a coprocessor composed of an anti-trigonometric function module is embedded in the main processor, and the method comprises the steps that a to-be-processed floating point variable of an anti-trigonometric function and corresponding data processing information are obtained from the coprocessor according to a preset floating point instruction; the method comprises the following steps: converting a to-be-processed floating point variable into a to-be-processed fixed point variable, carrying out shift processing according to an index part and a mantissa part of the to-be-processed floating point variable, mapping a shifted target fixed point variable to a preset coordinate space, carrying out vector iteration on the mapped fixed point variable, obtaining an initial output result after iteration, and carrying out reflection mapping to obtain a target fixed point variable; and obtaining a target output result after reflection and carrying out floating point conversion to obtain a target floating point quantity. The invention provides an anti-trigonometric function floating point data processing method with higher efficiency.