67 results about "Power-on reset" patented technology

Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.

The invention belongs to the technical field of power distribution, and particularly relates to a power distribution terminal power-on reset and watchdog function implementation system and method. According to the method, the FPGA sends the dog feeding signal during the period that the SoC is not started, the dog feeding main right is reasonably handed over according to the starting state of the SoC, meanwhile, a processing mechanism for the SoC starting abnormity is set, the situation that the watchdog is reset by mistake due to the fact that the SoC starting time is too long can be effectively avoided, the problem that the system is restarted repeatedly is solved, and the system reliability is improved. And stable operation of the power distribution terminal is ensured. The FPGA is not only responsible for maintaining a watchdog signal in the SoC starting stage, but also accurately monitoring and judging the starting state of the SoC. When the SoC is started abnormally, different recovery measures are taken according to the number of times of stopping feeding the dog, such as forcing the system-on-chip to restart or cutting off the SoC power supply and re-electrifying and resetting.

The invention discloses a reset circuit and a power-on reset system, and relates to the technical field of radio frequency transceiver chips, and the circuit comprises a first detection module which is connected with a power supply and is used for obtaining a power supply voltage and generating a first current signal according to the change of the power supply voltage, and the first current signal is in linear correlation with the size of the power supply voltage; the second detection module is connected with the power supply and is used for acquiring the power supply voltage and generating a second current signal according to the change of the power supply voltage, and the second current signal is in quadratic correlation with the size of the power supply voltage; the signal generation module is connected with the first detection module, the second detection module and the to-be-reset module, and is used for outputting a power supply reset signal to the to-be-reset module when the amplitude of the second current signal is greater than the amplitude of the first current signal. Compared with the prior art. According to the invention, the power supply reset signal is automatically generated through internal comparison of two current signals with different change rules, and the to-be-reset module can be reset without an external reference source.

This application relates to a reset circuit, which includes a clock module, a processor, and a reset control module. The reset control module is configured to: send a power-on reset signal to the processor during the power-on startup process of the system to which the reset circuit belongs; the power-on reset signal includes a low level of a first preset duration and a high level of a second preset duration; and clear a power-on reset flag to zero during the low-level period of the power-on reset signal; the processor is configured to: execute a power-on reset after receiving the power-on reset signal; and set the power-on reset flag to 1 after the power-on reset is completed; the reset control module is further configured to: detect the power-on reset flag during the high-level period of the power-on reset signal; and determine that the processor power-on reset is complete when the power-on reset flag is detected to be 1. Embodiments of this application can improve the reliability of the reset circuit.

The application discloses a power-on reset circuit of a multi-power supply chip, a chip and electronic equipment, and relates to the technical field of chips. The power-on reset circuit comprises a plurality of power supply detection circuits, the input ends of each power supply detection circuit are respectively connected to a corresponding power supply, and each power supply detection circuit is configured to output a detection completion signal when detecting that the corresponding power supply voltage reaches a preset detection threshold; and a logic processing circuit, the input end of the logic processing circuit is electrically connected to the output ends of the plurality of power supply detection circuits, and the logic processing circuit is configured to output a power-on reset signal when simultaneously receiving all detection completion signals. The application is configured with independent voltage detection modules for each power supply of the multi-power supply chip, and cooperates with logic centralized processing of detection signals, can adapt to any power supply power-on sequence, realizes independent voltage detection of each power supply, ensures that a reset signal is released only when all power supplies reach a preset detection threshold, fundamentally avoids abnormal work of the chip at a low voltage, and can greatly reduce the design complexity of a multi-power supply POR circuit.

The invention discloses a high-frequency high-power motor driving circuit in an astronavigation extreme environment. The high-frequency high-power motor driving circuit comprises a DSP (Digital Signal Processor), a pull-down resistor group, a direct connection prevention circuit, an optical coupler isolation circuit, a C43524RHF driving chip and a power MOS (Metal Oxide Semiconductor) tube, according to the circuit, six C43524RHF driving chips are adopted, so that the problem that conventional single-resistor adjustment cannot meet two time requirements at the same time is solved; six paths of control signals output by the DSP are firstly subjected to resistor pull-down processing, so that uncertain state signals output during the power-on reset period of the DSP can be ensured to be pulled to be low level, and straight-through of a post-stage power MOS (Metal Oxide Semiconductor) tube caused by phase overlapping of upper and lower complementary signals is avoided; meanwhile, an anti-straight-through circuit is formed by a logic gate circuit, so that straight-through burning of upper and lower power tubes in the three-phase bridge circuit can be prevented when control signals of the upper and lower paired tubes are abnormal, and an overcurrent protection function is realized; in addition, isolation of a control signal and a power signal is realized by means of a high-speed optocoupler, interference of a power strong electric signal on the control signal can be avoided, and stable realization of high-power driving control is guaranteed.

This application provides a battery protection chip, system, short-circuit protection detection comparator, and electronic device, relating to the technical field of power supplies. The battery protection chip includes: a power-on reset circuit, a delay circuit, a short-circuit protection detection comparator, a logic processing module, and a power transistor; the power-on reset circuit generates an enable signal based on the voltage output by the power supply; the delay circuit outputs the enable signal after a preset delay; the short-circuit protection detection comparator receives a preset threshold signal, a VM signal, and the delayed enable signal, and outputs a detection signal indicating whether a short circuit has occurred; the logic processing module receives the detection signal and the delayed enable signal, and generates a control signal based on the detection signal and the enable signal; when the control signal is a first control signal, the power transistor is turned off, keeping the VM signal at a high level; when the control signal is a second control signal, the power transistor is turned on, pulling the VM signal low.

In described examples, an integrated circuit (IC) includes an isolation, an input / output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.

The application belongs to the technical field of communication, and particularly relates to a power-on reset circuit and a radio frequency chip. The power-on reset circuit comprises a power-on reset unit and a buffer unit. An input end of the power-on reset unit is used for connecting a power supply voltage, an output end of the power-on reset unit is connected to an input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in a power-on process of the power supply voltage. An output end of the buffer unit is used for outputting a reset signal. The buffer unit is used for generating the reset signal according to the initial reset logic signal and outputting the reset signal. Compared with the prior art, the power-on reset circuit provided by the application has a simple structure, no static power consumption after reset is completed, and high reliability. The power-on reset circuit can normally reset in the case of power supply power-on time fluctuation or continuous power-on and power-off.

The invention provides a power-on reset circuit, a chip and an electronic product, and the circuit comprises a current mirror circuit which is provided with an input end and an output end; the biasing circuit comprises a first branch circuit, a second branch circuit and a resistance circuit, the first end of the first branch circuit is coupled to the input end of the current mirror circuit, the first end of the second branch circuit is coupled to the output end of the current mirror circuit, and the resistance circuit is coupled to the second end of the first branch circuit and the second end of the second branch circuit; and the driving circuit is provided with an input end coupled to the output end of the current mirror circuit and an output end for providing a power-on reset signal. The power-on reset circuit, the chip and the electronic product are simple in structure, high in anti-interference capability, low in power consumption and small in layout area.

The invention discloses a receiver, a digital isolator and a disconnection protection method thereof. The digital isolator includes a transmitter and a receiver connected via a differential line. The receiver comprises an amplifier, an envelope detector and a driver which are connected in sequence, and the envelope detector is configured to perform envelope detection on a differential input signal received by the receiver so as to generate a corresponding envelope signal; the switch module is configured to control the on-off state of an input signal path of the envelope detector; and the broken line protection module is used for detecting the line fault of the differential line according to the signal change of the envelope signal in different on-off states during the power-on reset period, and stopping providing the output signal when the line fault exists in the differential line.

The invention relates to the technical field of household appliances, and discloses a single-chip microcomputer fault detection method and device, a household appliance and a storage medium, and the method comprises the steps: carrying out the initialization configuration of the working state of each output pin of a single-chip microcomputer; circularly detecting the input level of each output pin within a first time, and determining whether an abnormal output pin with an abnormal input level exists or not; if the abnormal output pin with the abnormal input level exists, the input level of the abnormal output pin is detected again within second time after the single-chip microcomputer is subjected to power-on reset; based on the detection result, determining a fault detection result of the single-chip microcomputer; hardware hidden dangers are found in advance before the system is put into formal work, the purpose of single-chip microcomputer fault self-detection is achieved, single-chip microcomputer fault recognition accuracy is improved, and household appliance operation efficiency is improved.

A power extraction circuit for Radio Frequency Identification (RFID) tags and power extraction method thereof is a circuit and method for maximizing the efficiency of power harvesting in RFID tags. The power extraction circuit comprises an impedance matching network, a rectifier, and a tuning circuit. The tuning circuit comprises a power-on-reset (POR) circuit, a voltage regulator, two voltage-controlled switches, two voltage-to-time converters, a clock generator, a counter, and a control circuit.

The application discloses a method for configuring ECU CAN bus baud rate, a storage medium and equipment, a baud rate matching table in the ECU stores a commonly used baud rate list and its mark, and a host computer GUI initiates a baud rate configuration request according to an encrypted protocol agreed in advance, using the current CAN bus baud rate BaudRate_Cur of the APP; the ECU compares the received to-be-configured baud rate BaudRate_New with the baud rates in the matching table one by one, if equal, sets the mark of the baud rate in the matching table as valid and sets the marks of other baud rates as invalid, after power-on reset, the ECU can use the to-be-configured baud rate BaudRate_New; if not equal to the baud rates in the matching table, the to-be-configured baud rate BaudRate_New is discarded, and the ECU continues to use the current baud rate BaudRate_Cur. The application can change the CAN bus baud rate of the ECU without refreshing the ECU APP software, meets the needs of different customers, has strong universality, and greatly saves production cost.

The application belongs to the technical field of electronic circuits and provides a power-on reset circuit and a chip. The power-on reset circuit comprises a first logic module, a second logic module, a third logic module and a switch module. The second logic module is connected with the third logic module and the switch module respectively. The switch module is connected with the first logic module and the third logic module respectively. The first logic module and the second logic module both receive a power supply voltage. When the power supply voltage is less than a first threshold voltage, which indicates that the power supply voltage is less than the threshold voltage of an NMOS transistor, the first logic module outputs a first logic signal to control the switch module to be turned on. After the switch module is turned on, the first node and the second node are pulled down to a low level, so that the third logic module locks a power-on reset signal to a low level, thereby ensuring that the chip is in a reset state. The problem that the output of the traditional power-on reset circuit is in an uncertain state when the power supply voltage is lower than the threshold voltage of the NMOS transistor, thereby causing the abnormal reset state of the chip, is solved.

Integrated circuit devices, methods, and circuitry for configuring input / output (IO) circuitry for boundary scan chain testing is provided. An integrated circuit device may include a configuration register and IO configuration selector circuitry. The configuration register may define a voltage level of the IO circuitry based on a code stored in the configuration register. The IO configuration selector circuitry may determine the code based on a power-on-reset (POR) instruction.

A circuit arrangement and a real-time clock arrangement are provided, capable of appropriately performing a power-on reset action during initial startup. The circuit arrangement includes a first power line supplied with a first power supply voltage, a second power line supplied with a second power supply voltage, a third power line, a power supply circuit, a specified circuit, a first power-on reset circuit, a second power-on reset circuit, and a reset control circuit. When the first and second power-on reset circuits are at reset release levels, the reset control circuit causes a third power-on reset signal output to at least a portion of the specified circuit to become a reset release level.

A chiplet-based smart integrated compute system includes a safe compute subsystem and a safe compute and safety monitoring subsystem linked by die-to-die interconnects for high- speed, low-latency, freedom-from-interference operation. Dedicated secondary storage subsystems, clock-generation subsystems (with crystal oscillators), and power-regulation subsystems (with pre-regulators) provide domain-specific memory, timing, and power. A safe smart power management subsystem with a microcontroller manages intelligent distribution, autonomous power-on / reset, over-the-air (OTA) updates to power-management integrated circuits, and selective isolation during faults. The microcontroller monitors thermal / electrical health and can selectively shut down a faulty domain. The safe compute subsystem may serve as a secure communication gateway to external electronic control units via a wireless link on a network, using a cryptographic processing unit with hardware-embedded keys. Diagnostic telemetry is transmitted to a cloud for predictive maintenance and policy refinement.

The application relates to a power-on reset circuit for an electric energy metering chip and belongs to the field of integrated circuit design. The circuit comprises a coarse detection module, a fine detection module and a logic combination module; a power supply voltage VDD is connected with the input ends of the coarse detection module and the fine detection module, the output ends of the coarse detection module and the fine detection module are connected with the input ends of the logic combination module, and the output end of the logic combination module outputs a signal as a system signal. The coarse detection module comprises four PMOS tubes PM0-PM3, five NMOS tubes NM0-NM4, a three-stage inverter and a transmission gate T0. The fine detection module comprises four series-connected voltage division resistors R1-R4, two operational amplifiers A0-A1 and an SR latch. The application solves the defects of a traditional power-on reset circuit in terms of detection precision, anti-interference and scene configuration, and ensures stable reset of a chip system during power-on / power-off and no abnormal starting risk.

The invention discloses a system and a method for abnormal reset processing and state recovery of servo software. The system comprises a control center module, an interrupt processing module, a return telemetry data module and a watchdog register. The reset mode comprises power-on reset and watchdog reset; when the generated reset is power-on reset, initializing a watchdog, a servo system and an external clock, initializing an underflow interruption period, and initializing an SRAM area address of a variable to be stored to be 0; and when the generated reset is watchdog reset, loading the SRAM variable, loading the SRAM variable into the global variable of the servo system, and initializing the watchdog. According to the method, after the servo system software is subjected to thermal reset, the servo software can be executed according to the state before reset.

The invention belongs to the technical field of electronic circuits, and provides a power-on reset circuit and a chip. The power-on reset circuit comprises a first logic module, a second logic module, a third logic module and a switch module, the second logic module is respectively connected with the third logic module and the switch module, the switch module is respectively connected with the first logic module and the third logic module, and the first logic module and the second logic module receive power supply voltage. When the power supply voltage is smaller than a first threshold voltage, it is represented that the power supply voltage is smaller than the threshold voltage of the NMOS tube, the first logic module outputs a first logic signal and controls the switch module to be switched on, and after the switch module is switched on, the first node and the second node are pulled down to a low level, so that the third logic module locks the power-on reset signal to the low level, and the power-on reset signal is locked to the low level. According to the power-on reset circuit, the reset state of the chip is ensured, and the problem that the reset state of the chip is abnormal due to the fact that the output of a traditional power-on reset circuit is in an uncertain state when the power supply voltage is lower than the threshold voltage of the NMOS tube is solved.

The application discloses a primary voltage reduction and power-on reset circuit and belongs to the technical field of power management. The application circuit is applied to an integrated circuit chip with high-voltage input, is used for providing a primary voltage reduction power supply PRE_VCC for internal circuits with higher priority and higher power supply requirement in a system, and integrates a power-on reset function. Through the circuit design of the application, two-stage voltage reduction and smooth switching from high voltage VCC_HV to medium voltage PRE_VCC and then to precision power supply VCC are realized, the system is ensured to start quickly, and the final high-precision power supply requirement is met. The integrated power-on reset function effectively protects the system at low voltage and prevents the chip from malfunctioning when the power supply is insufficient. The high-performance requirement of the whole system on the power supply is met.

The utility model provides an engineering special vehicle MCU rapid reset control circuit and a power management system. The engineering special vehicle MCU rapid reset control circuit comprises a micro-control unit and a reset control module. The reset control module comprises a power-on reset sub-module and a power-off reset sub-module; the power-on reset sub-module outputs a reset signal to a chip reset signal end when the micro-control unit is powered on; the power-off reset sub-module adopts the combination of a rapid reset chip and a divider resistor, the input end of the rapid reset chip is connected with an external power supply, and the output end is connected to a chip reset signal end through the divider resistor. According to the circuit, a traditional passive RC network reset mechanism is replaced by the rapid reset chip, the problem of MCU reset abnormity caused by frequent ignition start and flameout turn-off of the engineering special vehicle is effectively solved, it is ensured that when the voltage drops to a preset threshold value, the rapid reset chip can rapidly recognize and output a low level to the MCU, sufficient time is provided for the MCU to complete a complete reset process, and the reliability of the MCU is improved. Therefore, continuous and stable operation of the MCU is ensured.

The invention discloses a chip-based multifunctional reset circuit and method. The circuit comprises an MCU, a signal control module, a primary timing unit, a reset monitoring module, a power supply monitoring module and a low-energy-consumption management module. A single-path three-state gate device of the signal control module is connected with a dog feeding pin of the MCU; a reset chip output of the reset monitoring module is connected with an MCU reset pin, and a reset input of the reset monitoring module is connected with the power supply monitoring module; and the low-energy-consumption management module adjusts the power consumption of the circuit according to the MCU sleep signal. The method comprises a plurality of stages of power-on reset, voltage detection, normal operation, under-voltage reset, watchdog timeout processing, manual reset, program update shielding and low-energy-consumption operation. According to the invention, the functions of power supply monitoring, watchdog timing, manual reset and program update protection are integrated, accurate and reliable system reset management and energy efficiency optimization are realized through a configurable enabling piece and a self-adaptive low-power-consumption design, and the stability and maintainability of an embedded system are remarkably improved.

The application discloses a power supply clamping circuit, an IO interface and an integrated circuit chip, and relates to the technical field of integrated circuits. The RC branch is connected between a power supply and a ground; the source of a first PMOS transistor is connected to the power supply, the drain of the first PMOS transistor is connected to the source of a second PMOS transistor, and the drain of the second PMOS transistor is connected to the ground through a second NMOS transistor; the gate of a first NMOS transistor is connected to the drain of the second PMOS transistor, the drain of the first NMOS transistor is connected to the power supply, and the source of the first NMOS transistor is connected to the ground; the gate of the second PMOS transistor and the gate of the second NMOS transistor are both connected to the common end of a resistor and a capacitor; the gate of the first PMOS transistor is connected to a power-on reset module of the power supply; and the power-on reset module is used for outputting a reset signal according to the voltage of the power supply, and the reset signal is synchronous with the voltage of the power supply.

A bias circuit includes a first resistive device connected between a power supply node to supply a supply voltage and a first node, a first N-type transistor diode-connected between the first node and a ground, a second N-type transistor, a second resistive device connected between a second node and a third node, and a third N-type transistor connected between the third node and the ground to implement a current source. The second N-type transistor has a drain connected to the power supply node, a source connected to the second node to output a bias voltage, and a gate connected to the first node.

This utility model discloses a circuit structure for automatic power-on reset of a chip to enter a readable mode, including an RC circuit, an oscillator, logic gates, and D flip-flops. The logic gates are connected to the RC circuit, the oscillator, and the D flip-flops respectively. When the RC circuit is powered on, it generates a high-level active power-on reset signal POR_1. The oscillator internally generates a high-level active synchronous reset signal POR_2 and a clock signal. After receiving the power-on reset signal POR_1 and the synchronous reset signal POR_2, the logic gate generates a low-level active clear signal, which clears all D flip-flops inside the chip. After all D flip-flops are cleared, the clock of the D flip-flops operates normally, outputting a POR signal of 1. Simultaneously, the synchronous reset signal POR_2 of the oscillator is turned off, releasing the reset state, and the chip's registers automatically enter a forced data read mode. This allows the chip to directly read data without configuring the registers after power-on.

According to the power-on reset control method compatible with multiple environments provided by the invention, the built power-on reset control circuit comprises the thermosensitive comparison circuit, the configuration trimming circuit and the power-on reset signal generation circuit, and whether the current environment temperature accords with the working temperature range of the consumable chip or not is judged through the thermosensitive comparison circuit; the follow-up work is executed only under the condition of conformity; according to the method, configuration data for electrification of a consumable chip of each signal is stored in the chip in advance, the configuration data for electrification is sent to a configuration trimming circuit after electrification, and the configuration trimming circuit is matched with the configuration data for electrification to modulate and generate a control voltage signal suitable for the consumable chip in real time; and the power-on reset signal is sent to the power-on reset signal generation circuit to generate a power-on reset signal.

The invention provides a high-capacity Nor Flash partition data recovery method and device, relates to the field of data storage, and solves the technical problem that the reliability and the performance of an existing high-capacity Nor Flash are not high enough. The method comprises the steps that Nor Flash is powered on and reset, and the size of a single data recovery area is obtained from a physical configuration area; when the chip receives an erasing instruction, executing an erasing operation on the target storage area; obtaining the address of the storage area needing data recovery currently from the physical state area; based on the weak state judgment voltage and the strong state judgment voltage, judging the logic states of the storage units in the storage area, and executing data recovery operation on the storage units which are judged to be 'weak 0'; and calculating the storage address of the next data recovery area, and writing the storage address into the physical state area. The data recovery method and device are used for the data recovery process of the high-capacity Nor Flash partition.