246 results about "Power-on reset" patented technology

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention provides a voltage control circuit and a display device.The voltage control circuit comprises a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit, the power-on reset circuit correspondingly outputs a third level signal or a fourth level signal during power-on or power-off, the comparison circuit compares power supply voltages, and the switch control circuit controls the first switch circuit and the second switch circuit. The switch control circuit correspondingly controls the on-off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit, and the power-off voltage can be detected through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit. When voltage rebound occurs in the power-down process, the first switching circuit can be effectively kept switched off, and abnormal restart of the power management integrated circuit is prevented, so that the problem of picture abnormity or splash screen caused by abnormal power-on of the display panel is effectively prevented, and the display quality and the user experience of the display device are improved.

The invention provides a power management and power consumption control device and method of a continuous blood glucose detection circuit. Relates to the technical field of continuous blood glucose detection, solves the problems of power consumption control and switching in the prior art, and is characterized in that a power input end of a charge pump is connected with an anode of an external power supply; the control input end of the charge pump is connected with a mode control signal end; the power output end of the charge pump is connected with the first control end of the power switch device; the switching signal control end of the charge pump is connected with the second control end of the power switching device through the delayer; the output end of the power switch device is connected with the working voltage input end, and the working voltage output end is connected with the grounding capacitor; the power output end of the charge pump is connected with the input end of the power-on reset module, the power switch switching signal end of the power-on reset module is connected with the power switch switching signal end of the charge pump, and different working modes can be achieved, so that power consumption control is achieved.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention provides a flash memory controller and a control method of the flash memory controller, after the flash memory controller completes power-on reset, a host side controller issues configuration information and an instruction of a register to the flash memory controller, and the instruction is written into an instruction cache; reading the instruction from the instruction cache, and decoding an operation code, an instruction weight and a command index corresponding to the instruction according to an instruction format; the weighted arbiter arbitrates and outputs instruction indexes from the instruction queues of all the states according to the weights, and the instruction indexes are stored in a command index buffer in the flash memory controller; and reading the instruction index from the instruction index buffer, and completing the reading of the command word according to the instruction index in the instruction corresponding to the instruction index. By customizing the instruction format, the weighted scheduling of different operations of the flash memory controller can be realized, the response sequence of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, and the quick response and dynamic scheduling of high-priority instructions can be realized.

A circuit for battery detection including a power-on reset (POR) block, an analog-to-digital converter (ADC) circuit, a switch circuit, and a logic control circuit is provided. The POR block is coupled to a node and is configured to output an output voltage with logic high level or logic low level when the node has a battery voltage higher or lower than a preset value, respectively. The switch circuit is coupled to the logic control circuit and the ADC circuit. The logic control circuit is coupled to the POR block and is configured to generate a control signal with the logic low level when the output voltage is at the logic low level, so that the switch circuit disconnects the ADC circuit and the node, and the ADC circuit does not read the battery voltage.

The invention is suitable for the technical field of communication, and particularly relates to a power-on reset circuit and a radio frequency chip. The power-on reset circuit comprises a power-on reset unit and a buffer unit. The input end of the power-on reset unit is used for being connected with power supply voltage, the output end of the power-on reset unit is connected with the input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in the power-on process of the power supply voltage; the output end of the buffer unit is used for outputting a reset signal; the buffer unit is used for generating reset signal output according to the initial reset logic signal. Compared with the prior art, the power-on reset circuit provided by the invention has the advantages of simple structure, no static power consumption after resetting, high reliability and capability of normally resetting under the conditions of power supply power-on time fluctuation or continuous power-on and power-off and the like.

The invention relates to a power management unit redundancy reset system, an automobile chip and an automobile. The reset system comprises a voltage stabilization module, a native power-on reset module, an internal redundancy power-on reset module, a reset mode configuration module and a reset signal output module. Digital voltage is accessed through the voltage stabilizing module, and the digital voltage is converted into analog voltage to be input to the original power-on reset module and the internal redundancy power-on reset module. In the boosting process, the original power-on reset module continuously detects the climbing of the digital voltage and the analog voltage, and can output a reset signal to the chip function system after the digital voltage reaches a first threshold value and the analog voltage reaches a second threshold value. In addition, the internal redundant power-on reset module can also continuously detect the climbing of the analog voltage and output the reset signal to the chip function system when the analog voltage reaches the third threshold value, so that the reset signal can be provided when the original power-on reset module fails, and the operation stability and reliability of the chip can be improved.

During system power-on, Ethernet controllers in a server are initialized and configured by a Power-On-Reset (POR) mechanism. A user-defined time period can be selected to delay configuration of an Ethernet link to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation. After configuration of an Ethernet PHY in the Ethernet controller is complete, an Ethernet link is established by exchanging messages with link partners according to the Ethernet protocol.

The invention provides a power-on reset circuit and a chip. The power-on reset circuit comprises a power-on module, and the power-on module is used for controlling connection or disconnection of a first end and a second end of the power-on module based on a control voltage and a power supply voltage of a first power supply end, and adjusting an output voltage of the power-on module based on the change of the power supply voltage when the power-on module is connected; the voltage dividing module is used for providing control voltage to the power-on module; the conversion module is used for converting the output voltage of the power-on module to output a reset control signal under the condition that the output voltage of the power-on module is changed to the overturning voltage of the conversion module; the first inverting module is used for converting the reset control signal to output a reset signal. Therefore, the power consumption generated in the circuit can be reduced while the circuit area is saved.

Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.

The invention discloses a reset circuit, a control chip and a radio frequency front-end module. The reset circuit comprises a voltage division module and a first control module. A first voltage dividing unit and a second voltage dividing unit included in the voltage dividing module are connected in series between a power supply voltage input end and a grounding end, a first control unit and a resistor unit included in the first control module are connected in series between the power supply voltage input end and the grounding end, and a control end of the first control unit is connected to a first node. Wherein the total resistance value of the resistor unit is greater than or equal to a specified resistance value, so that after the reset signal output end generates a power-on reset signal, the current value of a branch where the resistor unit is located is less than or equal to 2 [mu] A. The total resistance value of the resistor unit is large enough, and the current value of the branch circuit where the resistor unit is located can be reduced, so that after the power-on reset signal is generated, the overall power consumption of the reset circuit can be low.

A chip power-on reset circuit disclosed by the present invention comprises a sampling unit and a control unit, the control unit is connected with the sampling unit, the sampling unit is used for collecting the voltage when a chip is powered on and feeding back the voltage to the control unit, and the control unit feeds back a chip reset signal based on the feedback of the sampling unit and the working voltage range of the chip. The control unit comprises an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier and a seventh operational amplifier, one end of the ninth resistor and one end of the thirteenth resistor are connected with the power supply, and the other end of the ninth resistor is connected with one end of the tenth resistor and the in-phase end of the second operational amplifier; the inverting end of the second operational amplifier is connected with one end of the eighth resistor, the output end of the second operational amplifier is connected with the other end of the eighth resistor, and the other end of the thirteenth resistor is connected with one end of the fourteenth resistor and the in-phase end of the seventh operational amplifier.

The invention provides a chip pin multiplexing control circuit and a control method thereof, and a chip, the circuit comprises a multiplexing terminal, a chip power supply terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debugging controller, the multiplexing terminal is used for receiving a general function signal and a debugging function signal; the power-on reset controller is used for sending a first enabling control signal to the pin signal detector during power-on; the pin signal detector is used for obtaining an input signal of the multiplexing terminal when enabling is confirmed according to the first enabling control signal, and sending the first control signal to the debugging controller; the voltage detector is used for detecting a voltage signal of a chip power supply terminal and sending a second control signal to the debugging controller; the debugging controller is used for confirming whether to enter a debugging mode according to the first control signal and the second control signal. By applying the chip pin multiplexing control circuit provided by the invention, the waste of chip pin resources can be reduced, and accurate identification of the debugging request signal is ensured.

The invention discloses a low-power-consumption power-on reset circuit applied to a vehicle gauge chip. The low-power-consumption power-on reset circuit comprises a biasing circuit, a starting circuit and a power-on reset circuit body. When the power-on reset circuit is powered on, the starting circuit starts to work, output of a fourth node in the power-on reset circuit is forcibly set to be high level through a starting signal, and the power-on reset circuit outputs a reset signal; after the biasing circuit is started, a first current source and a second current source in the power-on reset circuit are controlled to start working, a third node in the power-on reset circuit starts to be charged, and after the third node is charged to be higher than the break-over voltage, the power-on reset circuit starts to execute reset judgment logic.

Disclosed is a storage device which includes a memory device, a power supply port that receives a first external power voltage from a host device, a power supply circuit that receives the first external power voltage from the power supply port and generates a first internal power voltage based on the first external power voltage, a monitoring circuit that receives the first external power voltage from the power supply port and generates a first power-on-reset signal based on monitoring the first external power voltage, and a storage controller configured to control the memory device. The storage controller is driven based on the first internal power voltage and the first power-on-reset signal, and the monitoring circuit detects a voltage drop in the first power-on-reset signal transmitted from the monitoring circuit to the storage controller and provides an error detection signal to the storage controller in response to detecting the voltage drop.

A multi-bit, asynchronous e-fuse macro, the macro comprising: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with the e-fuse macro.

The invention discloses a link test method and device, equipment, a medium and a product, and relates to the technical field of high-speed signal communication, and the method comprises the steps: loading firmware parameters and executing link training under the condition of system power-on reset; and recording the training result every time the link training is completed. And when the training result does not meet the training requirement, determining the firmware parameter of the next round based on the firmware parameter corresponding to the training result and a set firmware parameter loading strategy, and returning to the operation steps of loading the firmware parameter and executing the link training. The firmware loading and link training process is executed for multiple times in the power-on reset stage, and different firmware parameters are read during each firmware loading. When the training result meets the training requirement, the window width of the channel available parameter can be determined based on the minimum available gain value and the maximum available gain value contained in all the training results, and the larger the window width of the channel available parameter is, the smaller the link loss of the system is, and the better the PCIe link signal integrity is.

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

The present disclosure provides a reset circuit and a chip. The reset circuit includes a power-on reset circuit, an undervoltage reset circuit and a drive output circuit; the power-on reset circuit includes a resistor voltage divider module, a power supply voltage threshold detection module, a switch module and a power-on reset latch circuit, the undervoltage reset circuit includes a transmission tube voltage divider module, an undervoltage threshold detection module and a clamp module, and the power-on reset circuit and the undervoltage reset circuit are both connected to the drive output circuit; the power-on reset circuit is used to detect the power supply voltage and generate a power-on reset signal, which is sent to the drive output circuit; the undervoltage reset circuit is used to detect the power supply voltage and generate an undervoltage reset signal, which is sent to the drive output circuit; the drive output circuit is used to output a target reset drive signal according to the power-on reset signal and the undervoltage reset signal, so as to drive the chip to enter a reset state or exit a reset state. The present disclosure can independently and accurately adjust the power-on reset voltage and the undervoltage reset voltage, thereby ensuring the robustness of the chip.

The invention belongs to the technical field of power distribution, and particularly relates to a power distribution terminal power-on reset and watchdog function implementation system and method. According to the method, the FPGA sends the dog feeding signal during the period that the SoC is not started, the dog feeding main right is reasonably handed over according to the starting state of the SoC, meanwhile, a processing mechanism for the SoC starting abnormity is set, the situation that the watchdog is reset by mistake due to the fact that the SoC starting time is too long can be effectively avoided, the problem that the system is restarted repeatedly is solved, and the system reliability is improved. And stable operation of the power distribution terminal is ensured. The FPGA is not only responsible for maintaining a watchdog signal in the SoC starting stage, but also accurately monitoring and judging the starting state of the SoC. When the SoC is started abnormally, different recovery measures are taken according to the number of times of stopping feeding the dog, such as forcing the system-on-chip to restart or cutting off the SoC power supply and re-electrifying and resetting.

The invention discloses a primary step-down and power-on reset circuit, which belongs to the technical field of power management, is applied to an integrated circuit chip with high-voltage input, is used for providing a primary step-down power supply PREVCC for an internal circuit with higher priority and higher power supply requirement in a system, and is integrated with a power-on reset function. Through the circuit design of the invention, two-stage voltage reduction and smooth switching from high voltage VCCHV to medium voltage PREVCC and then to precise power supply VCC are realized, rapid starting of the system is ensured, and the final high-precision power supply requirement is met. Meanwhile, the integrated power-on reset function effectively protects the system at low voltage, and prevents the chip from malfunctioning when the power supply is insufficient. And the high-performance requirement of the whole system on the power supply is met.

The present invention proposes a voltage control circuit and a display device, wherein the voltage control circuit includes a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit. The power-on reset circuit outputs a third level signal or a fourth level signal correspondingly when the power is turned on or off. The comparison circuit compares the supply voltage and outputs a fifth level signal or a sixth level signal correspondingly. The switch control circuit controls the on and off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit. Through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit, the power-off voltage can be detected. When a voltage rebound occurs during the power-off process, the first switch circuit can be effectively kept off to prevent the power management integrated circuit from restarting abnormally, thereby effectively preventing the display panel from abnormally powering on and causing screen abnormalities or flickering problems, thereby improving the display quality and user experience of the display device.

This invention discloses a chip power-on reset circuit, including a sampling unit and a control unit. The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier, and a seventh operational amplifier. One end of the ninth resistor and one end of the thirteenth resistor are connected to a power supply. The other end of the ninth resistor is connected to one end of the tenth resistor and the non-inverting input of the second operational amplifier. The inverting input of the second operational amplifier is connected to one end of the eighth resistor. The output terminal of the second operational amplifier is connected to the other end of the eighth resistor. The other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the non-inverting input of the seventh operational amplifier.

The invention relates to a reset circuit, the reset circuit comprises a clock module, a processor and a reset control module, the reset control module is used for sending a power-on reset signal to the processor in the power-on starting process of a system to which the reset circuit belongs, the power-on reset signal comprises a low level of a first preset duration and a high level of a second preset duration, when the power-on reset signal is at a low level, the power-on reset mark is reset; the processor is used for executing power-on reset after receiving the power-on reset signal, and setting a power-on reset mark as 1 after the power-on reset is executed; and the reset control module is also used for detecting the power-on reset mark when the power-on reset signal is at the high level, and determining that the power-on reset of the processor is completed when the power-on reset mark is detected to be 1. According to the embodiment of the invention, the reliability of the reset circuit can be improved.

A voltage monitor circuit that signals if an input voltage is above or below an internally established reference level proportional to the bandgap voltage of silicon. The voltage monitor circuit mitigates main error sources generally associated with bandgap reference generation such that high accuracy and good performance may be achieved at low power cost. The techniques allow voltage monitors (e.g., brown-out and power on reset (POR) detectors) to be implemented with higher accuracy, lower power consumption, smaller area cost, and support to lower supply voltage than other solutions.

The invention discloses a reset circuit and a power-on reset system, and relates to the technical field of radio frequency transceiver chips, and the circuit comprises a first detection module which is connected with a power supply and is used for obtaining a power supply voltage and generating a first current signal according to the change of the power supply voltage, and the first current signal is in linear correlation with the size of the power supply voltage; the second detection module is connected with the power supply and is used for acquiring the power supply voltage and generating a second current signal according to the change of the power supply voltage, and the second current signal is in quadratic correlation with the size of the power supply voltage; the signal generation module is connected with the first detection module, the second detection module and the to-be-reset module, and is used for outputting a power supply reset signal to the to-be-reset module when the amplitude of the second current signal is greater than the amplitude of the first current signal. Compared with the prior art. According to the invention, the power supply reset signal is automatically generated through internal comparison of two current signals with different change rules, and the to-be-reset module can be reset without an external reference source.

The invention discloses a power-on reset and reference voltage composite function circuit based on current comparison and application thereof, and the circuit comprises a comparison current and reference voltage generation module, a following current generation module, a current comparison module and a signal output module which are respectively connected with a power circuit. The comparison current and reference voltage generation module generates and outputs stable comparison current and reference voltage, the following current generation module generates following current increasing along with rising of power supply voltage, and the current comparison module generates and outputs a comparison result of the comparison current and the following current. The signal output module generates and outputs a power-on reset signal or a power-off detection signal. Effective power-on reset and power-off detection can be achieved, stable reference voltage can be output, in addition, power-on threshold voltage in the circuit can obtain effective temperature compensation and is not affected by temperature, and the circuit is simple in structure and high in reliability and has high practical value and wide application prospects.

This application relates to the field of integrated circuit technology and provides a power-on reset circuit and method for generating a reset signal. For the problem of the power-on reset protection mechanism, the power-on reset circuit effectively avoids misjudgment and improves the anti-interference ability of the circuit through the cooperation between the comparison module, the selection module, and the resistor-capacitor filtering module. By using the adjustable resistor-capacitor constant switching of the resistor-capacitor filtering module and the output switching of the comparison module. Moreover, without the intervention of external devices, the power-on reset circuit can continuously monitor the power supply voltage signal by itself, thereby adaptively determining when to generate the reset signal and when to abort the generation of the reset signal, which is beneficial to integration and miniaturization, helps to adapt to the application environment and device characteristics, and helps to support the customized requirements and device expansion requirements in application fields such as high-performance computers, automotive electronics, communication devices, and industrial control.