134 results about "Power-on reset" patented technology

The invention is suitable for the technical field of communication, and particularly relates to a power-on reset circuit and a radio frequency chip. The power-on reset circuit comprises a power-on reset unit and a buffer unit. The input end of the power-on reset unit is used for being connected with power supply voltage, the output end of the power-on reset unit is connected with the input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in the power-on process of the power supply voltage; the output end of the buffer unit is used for outputting a reset signal; the buffer unit is used for generating reset signal output according to the initial reset logic signal. Compared with the prior art, the power-on reset circuit provided by the invention has the advantages of simple structure, no static power consumption after resetting, high reliability and capability of normally resetting under the conditions of power supply power-on time fluctuation or continuous power-on and power-off and the like.

During system power-on, Ethernet controllers in a server are initialized and configured by a Power-On-Reset (POR) mechanism. A user-defined time period can be selected to delay configuration of an Ethernet link to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation. After configuration of an Ethernet PHY in the Ethernet controller is complete, an Ethernet link is established by exchanging messages with link partners according to the Ethernet protocol.

Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.

A multi-bit, asynchronous e-fuse macro, the macro comprising: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with the e-fuse macro.

The invention discloses a link test method and device, equipment, a medium and a product, and relates to the technical field of high-speed signal communication, and the method comprises the steps: loading firmware parameters and executing link training under the condition of system power-on reset; and recording the training result every time the link training is completed. And when the training result does not meet the training requirement, determining the firmware parameter of the next round based on the firmware parameter corresponding to the training result and a set firmware parameter loading strategy, and returning to the operation steps of loading the firmware parameter and executing the link training. The firmware loading and link training process is executed for multiple times in the power-on reset stage, and different firmware parameters are read during each firmware loading. When the training result meets the training requirement, the window width of the channel available parameter can be determined based on the minimum available gain value and the maximum available gain value contained in all the training results, and the larger the window width of the channel available parameter is, the smaller the link loss of the system is, and the better the PCIe link signal integrity is.

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

The invention belongs to the technical field of power distribution, and particularly relates to a power distribution terminal power-on reset and watchdog function implementation system and method. According to the method, the FPGA sends the dog feeding signal during the period that the SoC is not started, the dog feeding main right is reasonably handed over according to the starting state of the SoC, meanwhile, a processing mechanism for the SoC starting abnormity is set, the situation that the watchdog is reset by mistake due to the fact that the SoC starting time is too long can be effectively avoided, the problem that the system is restarted repeatedly is solved, and the system reliability is improved. And stable operation of the power distribution terminal is ensured. The FPGA is not only responsible for maintaining a watchdog signal in the SoC starting stage, but also accurately monitoring and judging the starting state of the SoC. When the SoC is started abnormally, different recovery measures are taken according to the number of times of stopping feeding the dog, such as forcing the system-on-chip to restart or cutting off the SoC power supply and re-electrifying and resetting.

The invention discloses a primary step-down and power-on reset circuit, which belongs to the technical field of power management, is applied to an integrated circuit chip with high-voltage input, is used for providing a primary step-down power supply PREVCC for an internal circuit with higher priority and higher power supply requirement in a system, and is integrated with a power-on reset function. Through the circuit design of the invention, two-stage voltage reduction and smooth switching from high voltage VCCHV to medium voltage PREVCC and then to precise power supply VCC are realized, rapid starting of the system is ensured, and the final high-precision power supply requirement is met. Meanwhile, the integrated power-on reset function effectively protects the system at low voltage, and prevents the chip from malfunctioning when the power supply is insufficient. And the high-performance requirement of the whole system on the power supply is met.

This invention discloses a chip power-on reset circuit, including a sampling unit and a control unit. The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier, and a seventh operational amplifier. One end of the ninth resistor and one end of the thirteenth resistor are connected to a power supply. The other end of the ninth resistor is connected to one end of the tenth resistor and the non-inverting input of the second operational amplifier. The inverting input of the second operational amplifier is connected to one end of the eighth resistor. The output terminal of the second operational amplifier is connected to the other end of the eighth resistor. The other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the non-inverting input of the seventh operational amplifier.

The invention discloses a reset circuit and a power-on reset system, and relates to the technical field of radio frequency transceiver chips, and the circuit comprises a first detection module which is connected with a power supply and is used for obtaining a power supply voltage and generating a first current signal according to the change of the power supply voltage, and the first current signal is in linear correlation with the size of the power supply voltage; the second detection module is connected with the power supply and is used for acquiring the power supply voltage and generating a second current signal according to the change of the power supply voltage, and the second current signal is in quadratic correlation with the size of the power supply voltage; the signal generation module is connected with the first detection module, the second detection module and the to-be-reset module, and is used for outputting a power supply reset signal to the to-be-reset module when the amplitude of the second current signal is greater than the amplitude of the first current signal. Compared with the prior art. According to the invention, the power supply reset signal is automatically generated through internal comparison of two current signals with different change rules, and the to-be-reset module can be reset without an external reference source.

This application relates to a reset circuit, which includes a clock module, a processor, and a reset control module. The reset control module is configured to: send a power-on reset signal to the processor during the power-on startup process of the system to which the reset circuit belongs; the power-on reset signal includes a low level of a first preset duration and a high level of a second preset duration; and clear a power-on reset flag to zero during the low-level period of the power-on reset signal; the processor is configured to: execute a power-on reset after receiving the power-on reset signal; and set the power-on reset flag to 1 after the power-on reset is completed; the reset control module is further configured to: detect the power-on reset flag during the high-level period of the power-on reset signal; and determine that the processor power-on reset is complete when the power-on reset flag is detected to be 1. Embodiments of this application can improve the reliability of the reset circuit.

The invention provides a high-precision delay protection low-voltage locking circuit and a control method, and the circuit comprises an analog signal part: a comparison module which is used for comparing a power supply voltage with a reference voltage to generate a corresponding threshold signal; the power-on reset module outputs a first reset signal or a power-on signal to the digital logic part based on the power-on process of the power supply voltage to the power-on reset module; the clock module is used as a clock source for outputting a clock signal; a digital logic section: a reset logic unit that generates an enable reset signal based on a threshold signal and a first reset signal; the frequency division clock generation unit adopts a multi-stage trigger and a logic gate to form a frequency division counter, performs frequency division operation on a clock signal, and provides a time reference for delay control; and the enabling generation unit is used for enabling an enabling signal to be output only when the voltage is stable and the delay is satisfied through logic combination analysis of the clock signal after frequency division and a threshold signal.

The application discloses a power-on reset circuit of a multi-power supply chip, a chip and electronic equipment, and relates to the technical field of chips. The power-on reset circuit comprises a plurality of power supply detection circuits, the input ends of each power supply detection circuit are respectively connected to a corresponding power supply, and each power supply detection circuit is configured to output a detection completion signal when detecting that the corresponding power supply voltage reaches a preset detection threshold; and a logic processing circuit, the input end of the logic processing circuit is electrically connected to the output ends of the plurality of power supply detection circuits, and the logic processing circuit is configured to output a power-on reset signal when simultaneously receiving all detection completion signals. The application is configured with independent voltage detection modules for each power supply of the multi-power supply chip, and cooperates with logic centralized processing of detection signals, can adapt to any power supply power-on sequence, realizes independent voltage detection of each power supply, ensures that a reset signal is released only when all power supplies reach a preset detection threshold, fundamentally avoids abnormal work of the chip at a low voltage, and can greatly reduce the design complexity of a multi-power supply POR circuit.

Examples of the present disclosure provide a memory device and an operation method thereof, a memory system and a storage medium. The memory device includes: a memory cell array, and a peripheral circuit coupled with the memory cell array, wherein the peripheral circuit is configured to: before performing a power on reset operation, set all state information of a plurality of main memory areas in a page buffer to a normal state; in the process of performing the power on reset operation, match a second address of each of the plurality of main memory areas with a first address in a register; and determine, according to a match result, whether to modify state information of a respective main memory area in the page buffer to a fault state.

The invention discloses a high-voltage power-on reset circuit, and the circuit comprises a band-gap reference module which generates a preset reference voltage; the sampling module is used for sampling power supply voltage and outputting a power-on reset signal; the phase reversal module is used for performing phase reversal processing on the sampling voltage and outputting a phase reversal power-on reset signal; the comparator is used for comparing a preset reference voltage with the reverse-phase power-on reset signal and outputting a power-on reset control signal; and the power-on reset module outputs a reset signal under the control of the power-on reset control signal so as to complete power-on reset. The comparator is used for comparing the preset reference voltage with the anti-phase power-on reset signal and outputting the power-on reset control signal to control the power-on reset module to complete power-on reset; a voltage-limiting diode is added to a gate-source electrode of a high-voltage MOS tube in the power-on reset module, and positive and negative electrode voltages of the diode are controlled to protect the high-voltage MOS tube; the high-voltage power-on reset circuit is simple in structure and small in occupied chip area.

The invention discloses a high-frequency high-power motor driving circuit in an astronavigation extreme environment. The high-frequency high-power motor driving circuit comprises a DSP (Digital Signal Processor), a pull-down resistor group, a direct connection prevention circuit, an optical coupler isolation circuit, a C43524RHF driving chip and a power MOS (Metal Oxide Semiconductor) tube, according to the circuit, six C43524RHF driving chips are adopted, so that the problem that conventional single-resistor adjustment cannot meet two time requirements at the same time is solved; six paths of control signals output by the DSP are firstly subjected to resistor pull-down processing, so that uncertain state signals output during the power-on reset period of the DSP can be ensured to be pulled to be low level, and straight-through of a post-stage power MOS (Metal Oxide Semiconductor) tube caused by phase overlapping of upper and lower complementary signals is avoided; meanwhile, an anti-straight-through circuit is formed by a logic gate circuit, so that straight-through burning of upper and lower power tubes in the three-phase bridge circuit can be prevented when control signals of the upper and lower paired tubes are abnormal, and an overcurrent protection function is realized; in addition, isolation of a control signal and a power signal is realized by means of a high-speed optocoupler, interference of a power strong electric signal on the control signal can be avoided, and stable realization of high-power driving control is guaranteed.

This application provides a battery protection chip, system, short-circuit protection detection comparator, and electronic device, relating to the technical field of power supplies. The battery protection chip includes: a power-on reset circuit, a delay circuit, a short-circuit protection detection comparator, a logic processing module, and a power transistor; the power-on reset circuit generates an enable signal based on the voltage output by the power supply; the delay circuit outputs the enable signal after a preset delay; the short-circuit protection detection comparator receives a preset threshold signal, a VM signal, and the delayed enable signal, and outputs a detection signal indicating whether a short circuit has occurred; the logic processing module receives the detection signal and the delayed enable signal, and generates a control signal based on the detection signal and the enable signal; when the control signal is a first control signal, the power transistor is turned off, keeping the VM signal at a high level; when the control signal is a second control signal, the power transistor is turned on, pulling the VM signal low.

A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.

The utility model discloses a control module and an ultrahigh pressure electric control needle valve system, relates to the field of needle valve control, solves the problem that a reduction gearbox gear is seriously abraded after the reverse torsion of an output end is increased, and adopts the technical scheme that the control module comprises a current limiting circuit and a single chip microcomputer circuit; the single-chip microcomputer circuit comprises an STM32F0 single-chip microcomputer, a resistor R4, a capacitor C2 and a resistor R2. The NRST of the STM32F0 single-chip microcomputer forms an RC power-on reset circuit through a resistor R4 and a capacitor C2, and the resistor R2 controls the starting sequence of the STM32F0 single-chip microcomputer to be a built-in FLASH; the single-chip microcomputer circuit is connected with a current limiting circuit and used for controlling the current limiting circuit to output limiting current. The current limiting circuit is connected with the brushless direct current motor and used for limiting the maximum working current of the brushless direct current motor so as to control torque output of the brushless direct current motor and complete protection of the worm and gear reduction gearbox.

In described examples, an integrated circuit (IC) includes an isolation, an input / output (IO), and a low power mode (LPM) control logic. The isolation includes a level shift with pull-down configured to weakly pull down the voltage of signals that travel through the isolation. The IO includes an input and a physical connector for coupling to a power management IC. The IO provides an asserted-low LPM enable signal to the physical connector in response to the IO input. An output of the LPM control logic is coupled via the isolation to the input of the IO. The LPM control logic provides a high voltage signal to the input of the IO as a default during power on reset (POR) of the IC. The pull-down pulls the LPM enable signal voltage to the asserted low voltage in response to a voltage of the LPM enable signal falling below a threshold.

The present invention relates to a reset anomaly monitoring device, method, chip, and circuit, comprising: a system-on-chip (SoC) determining configuration information based on the number of occurrences and the number of exception requests, as well as changes thereto; updating the configuration information and writing it into a register configuration module when the configuration information changes; and a reset monitoring module monitoring reset requests from various on-chip submodules of the SoC based on the updated configuration information. The present invention utilizes the computing resources of the SoC to analyze SoC-level reset signal anomaly data, dynamically monitoring the reset status and request anomalies of each reset source, and, upon detecting an anomaly, bypassing the reset management module to directly initiate a system-level power-on reset, returning the entire system-level reset signal to a power-on initialization state, thereby restoring the system to a safe state and enabling normal operation.

The embodiment of the invention provides a power-on reset system, a battery management chip and a vehicle, and the system comprises a sampling circuit, the first end of which is connected with a power supply; the first end of the band-gap reference core is connected with the second end of the sampling circuit, and the second end of the band-gap reference core is connected with the power supply; the first end of the comparator module is connected with the third end of the band-gap reference core, the second end of the comparator module is connected with the fourth end of the band-gap reference core, and the third end of the comparator module is connected with a power supply; and the first end of the phase inverter module is connected with the fourth end of the comparator module, the second end of the phase inverter module is connected with the target equipment, and the third end of the phase inverter module is connected with the power supply. According to the method and the device, the technical problem of relatively poor stability of power-on reset of the target equipment in the prior art is solved.

The application belongs to the technical field of communication, and particularly relates to a power-on reset circuit and a radio frequency chip. The power-on reset circuit comprises a power-on reset unit and a buffer unit. An input end of the power-on reset unit is used for connecting a power supply voltage, an output end of the power-on reset unit is connected to an input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in a power-on process of the power supply voltage. An output end of the buffer unit is used for outputting a reset signal. The buffer unit is used for generating the reset signal according to the initial reset logic signal and outputting the reset signal. Compared with the prior art, the power-on reset circuit provided by the application has a simple structure, no static power consumption after reset is completed, and high reliability. The power-on reset circuit can normally reset in the case of power supply power-on time fluctuation or continuous power-on and power-off.

The invention discloses a power-on reset circuit with a self-detection backlock function. The power-on reset circuit comprises a first detection unit, a second detection unit and a logic comparison unit, a first RC charging and discharging unit of a first detection unit is used for power supply voltage detection and pre-charging, and a first back lock turn-off unit of the first detection unit is used for back lock turn-off and signal locking, so that first detection voltage is obtained; power supply voltage detection and pre-charging are carried out through a second RC charging and discharging unit of a second detection unit, and back lock turn-off and signal locking are carried out through a second back lock turn-off unit of the second detection unit, so that second detection voltage is obtained; outputting a corresponding reset signal through an NAND gate of the logic comparison unit according to the first detection voltage and the second detection voltage; therefore, power consumption is greatly reduced, and the whole circuit area is reduced.

The invention provides a power-on reset circuit, a chip and an electronic product, and the circuit comprises a current mirror circuit which is provided with an input end and an output end; the biasing circuit comprises a first branch circuit, a second branch circuit and a resistance circuit, the first end of the first branch circuit is coupled to the input end of the current mirror circuit, the first end of the second branch circuit is coupled to the output end of the current mirror circuit, and the resistance circuit is coupled to the second end of the first branch circuit and the second end of the second branch circuit; and the driving circuit is provided with an input end coupled to the output end of the current mirror circuit and an output end for providing a power-on reset signal. The power-on reset circuit, the chip and the electronic product are simple in structure, high in anti-interference capability, low in power consumption and small in layout area.

The invention discloses a receiver, a digital isolator and a disconnection protection method thereof. The digital isolator includes a transmitter and a receiver connected via a differential line. The receiver comprises an amplifier, an envelope detector and a driver which are connected in sequence, and the envelope detector is configured to perform envelope detection on a differential input signal received by the receiver so as to generate a corresponding envelope signal; the switch module is configured to control the on-off state of an input signal path of the envelope detector; and the broken line protection module is used for detecting the line fault of the differential line according to the signal change of the envelope signal in different on-off states during the power-on reset period, and stopping providing the output signal when the line fault exists in the differential line.

The invention relates to the technical field of household appliances, and discloses a single-chip microcomputer fault detection method and device, a household appliance and a storage medium, and the method comprises the steps: carrying out the initialization configuration of the working state of each output pin of a single-chip microcomputer; circularly detecting the input level of each output pin within a first time, and determining whether an abnormal output pin with an abnormal input level exists or not; if the abnormal output pin with the abnormal input level exists, the input level of the abnormal output pin is detected again within second time after the single-chip microcomputer is subjected to power-on reset; based on the detection result, determining a fault detection result of the single-chip microcomputer; hardware hidden dangers are found in advance before the system is put into formal work, the purpose of single-chip microcomputer fault self-detection is achieved, single-chip microcomputer fault recognition accuracy is improved, and household appliance operation efficiency is improved.

The application discloses a circuit and a chip for preventing mis-triggering, which comprises a first power regulator, a main circuit load, a second power regulator, a static load and a control circuit. The first power regulator and the second power regulator are connected with a power-on reset circuit; the static load is connected with the power-on reset circuit; and the control circuit is connected with the power-on reset circuit, the first power regulator and the main circuit load. The circuit for preventing mis-triggering of the application adopts the mode of copying the first power regulator to obtain the second power regulator and the static load without jump, and the power-on reset circuit switches from monitoring the first output voltage and the second output voltage simultaneously to monitoring only the second output voltage from the power-on process to the completion of the power-on, which effectively reflects the power voltage change of the main circuit load and avoids the mis-triggering problem of the power-on reset circuit caused by the glitch of the main circuit load jump.

A power extraction circuit for Radio Frequency Identification (RFID) tags and power extraction method thereof is a circuit and method for maximizing the efficiency of power harvesting in RFID tags. The power extraction circuit comprises an impedance matching network, a rectifier, and a tuning circuit. The tuning circuit comprises a power-on-reset (POR) circuit, a voltage regulator, two voltage-controlled switches, two voltage-to-time converters, a clock generator, a counter, and a control circuit.