190 results about "Power-on reset" patented technology

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention provides a voltage control circuit and a display device.The voltage control circuit comprises a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit, the power-on reset circuit correspondingly outputs a third level signal or a fourth level signal during power-on or power-off, the comparison circuit compares power supply voltages, and the switch control circuit controls the first switch circuit and the second switch circuit. The switch control circuit correspondingly controls the on-off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit, and the power-off voltage can be detected through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit. When voltage rebound occurs in the power-down process, the first switching circuit can be effectively kept switched off, and abnormal restart of the power management integrated circuit is prevented, so that the problem of picture abnormity or splash screen caused by abnormal power-on of the display panel is effectively prevented, and the display quality and the user experience of the display device are improved.

The invention provides a power management and power consumption control device and method of a continuous blood glucose detection circuit. Relates to the technical field of continuous blood glucose detection, solves the problems of power consumption control and switching in the prior art, and is characterized in that a power input end of a charge pump is connected with an anode of an external power supply; the control input end of the charge pump is connected with a mode control signal end; the power output end of the charge pump is connected with the first control end of the power switch device; the switching signal control end of the charge pump is connected with the second control end of the power switching device through the delayer; the output end of the power switch device is connected with the working voltage input end, and the working voltage output end is connected with the grounding capacitor; the power output end of the charge pump is connected with the input end of the power-on reset module, the power switch switching signal end of the power-on reset module is connected with the power switch switching signal end of the charge pump, and different working modes can be achieved, so that power consumption control is achieved.

According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input / output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

The invention provides a flash memory controller and a control method of the flash memory controller, after the flash memory controller completes power-on reset, a host side controller issues configuration information and an instruction of a register to the flash memory controller, and the instruction is written into an instruction cache; reading the instruction from the instruction cache, and decoding an operation code, an instruction weight and a command index corresponding to the instruction according to an instruction format; the weighted arbiter arbitrates and outputs instruction indexes from the instruction queues of all the states according to the weights, and the instruction indexes are stored in a command index buffer in the flash memory controller; and reading the instruction index from the instruction index buffer, and completing the reading of the command word according to the instruction index in the instruction corresponding to the instruction index. By customizing the instruction format, the weighted scheduling of different operations of the flash memory controller can be realized, the response sequence of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, and the quick response and dynamic scheduling of high-priority instructions can be realized.

A circuit for battery detection including a power-on reset (POR) block, an analog-to-digital converter (ADC) circuit, a switch circuit, and a logic control circuit is provided. The POR block is coupled to a node and is configured to output an output voltage with logic high level or logic low level when the node has a battery voltage higher or lower than a preset value, respectively. The switch circuit is coupled to the logic control circuit and the ADC circuit. The logic control circuit is coupled to the POR block and is configured to generate a control signal with the logic low level when the output voltage is at the logic low level, so that the switch circuit disconnects the ADC circuit and the node, and the ADC circuit does not read the battery voltage.

The invention is suitable for the technical field of communication, and particularly relates to a power-on reset circuit and a radio frequency chip. The power-on reset circuit comprises a power-on reset unit and a buffer unit. The input end of the power-on reset unit is used for being connected with power supply voltage, the output end of the power-on reset unit is connected with the input end of the buffer unit, and the power-on reset unit is used for generating an initial reset logic signal and sending the initial reset logic signal to the buffer unit in the power-on process of the power supply voltage; the output end of the buffer unit is used for outputting a reset signal; the buffer unit is used for generating reset signal output according to the initial reset logic signal. Compared with the prior art, the power-on reset circuit provided by the invention has the advantages of simple structure, no static power consumption after resetting, high reliability and capability of normally resetting under the conditions of power supply power-on time fluctuation or continuous power-on and power-off and the like.

During system power-on, Ethernet controllers in a server are initialized and configured by a Power-On-Reset (POR) mechanism. A user-defined time period can be selected to delay configuration of an Ethernet link to allow sufficient time for completion of the initialization of the Ethernet controller for post-boot operation. After configuration of an Ethernet PHY in the Ethernet controller is complete, an Ethernet link is established by exchanging messages with link partners according to the Ethernet protocol.

The invention provides a power-on reset circuit and a chip. The power-on reset circuit comprises a power-on module, and the power-on module is used for controlling connection or disconnection of a first end and a second end of the power-on module based on a control voltage and a power supply voltage of a first power supply end, and adjusting an output voltage of the power-on module based on the change of the power supply voltage when the power-on module is connected; the voltage dividing module is used for providing control voltage to the power-on module; the conversion module is used for converting the output voltage of the power-on module to output a reset control signal under the condition that the output voltage of the power-on module is changed to the overturning voltage of the conversion module; the first inverting module is used for converting the reset control signal to output a reset signal. Therefore, the power consumption generated in the circuit can be reduced while the circuit area is saved.

Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.

The invention discloses a reset circuit, a control chip and a radio frequency front-end module. The reset circuit comprises a voltage division module and a first control module. A first voltage dividing unit and a second voltage dividing unit included in the voltage dividing module are connected in series between a power supply voltage input end and a grounding end, a first control unit and a resistor unit included in the first control module are connected in series between the power supply voltage input end and the grounding end, and a control end of the first control unit is connected to a first node. Wherein the total resistance value of the resistor unit is greater than or equal to a specified resistance value, so that after the reset signal output end generates a power-on reset signal, the current value of a branch where the resistor unit is located is less than or equal to 2 [mu] A. The total resistance value of the resistor unit is large enough, and the current value of the branch circuit where the resistor unit is located can be reduced, so that after the power-on reset signal is generated, the overall power consumption of the reset circuit can be low.

The invention provides a chip pin multiplexing control circuit and a control method thereof, and a chip, the circuit comprises a multiplexing terminal, a chip power supply terminal, a power-on reset controller, a pin signal detector, a voltage detector and a debugging controller, the multiplexing terminal is used for receiving a general function signal and a debugging function signal; the power-on reset controller is used for sending a first enabling control signal to the pin signal detector during power-on; the pin signal detector is used for obtaining an input signal of the multiplexing terminal when enabling is confirmed according to the first enabling control signal, and sending the first control signal to the debugging controller; the voltage detector is used for detecting a voltage signal of a chip power supply terminal and sending a second control signal to the debugging controller; the debugging controller is used for confirming whether to enter a debugging mode according to the first control signal and the second control signal. By applying the chip pin multiplexing control circuit provided by the invention, the waste of chip pin resources can be reduced, and accurate identification of the debugging request signal is ensured.

Disclosed is a storage device which includes a memory device, a power supply port that receives a first external power voltage from a host device, a power supply circuit that receives the first external power voltage from the power supply port and generates a first internal power voltage based on the first external power voltage, a monitoring circuit that receives the first external power voltage from the power supply port and generates a first power-on-reset signal based on monitoring the first external power voltage, and a storage controller configured to control the memory device. The storage controller is driven based on the first internal power voltage and the first power-on-reset signal, and the monitoring circuit detects a voltage drop in the first power-on-reset signal transmitted from the monitoring circuit to the storage controller and provides an error detection signal to the storage controller in response to detecting the voltage drop.

A multi-bit, asynchronous e-fuse macro, the macro comprising: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with the e-fuse macro.

The invention discloses a link test method and device, equipment, a medium and a product, and relates to the technical field of high-speed signal communication, and the method comprises the steps: loading firmware parameters and executing link training under the condition of system power-on reset; and recording the training result every time the link training is completed. And when the training result does not meet the training requirement, determining the firmware parameter of the next round based on the firmware parameter corresponding to the training result and a set firmware parameter loading strategy, and returning to the operation steps of loading the firmware parameter and executing the link training. The firmware loading and link training process is executed for multiple times in the power-on reset stage, and different firmware parameters are read during each firmware loading. When the training result meets the training requirement, the window width of the channel available parameter can be determined based on the minimum available gain value and the maximum available gain value contained in all the training results, and the larger the window width of the channel available parameter is, the smaller the link loss of the system is, and the better the PCIe link signal integrity is.

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

The invention belongs to the technical field of power distribution, and particularly relates to a power distribution terminal power-on reset and watchdog function implementation system and method. According to the method, the FPGA sends the dog feeding signal during the period that the SoC is not started, the dog feeding main right is reasonably handed over according to the starting state of the SoC, meanwhile, a processing mechanism for the SoC starting abnormity is set, the situation that the watchdog is reset by mistake due to the fact that the SoC starting time is too long can be effectively avoided, the problem that the system is restarted repeatedly is solved, and the system reliability is improved. And stable operation of the power distribution terminal is ensured. The FPGA is not only responsible for maintaining a watchdog signal in the SoC starting stage, but also accurately monitoring and judging the starting state of the SoC. When the SoC is started abnormally, different recovery measures are taken according to the number of times of stopping feeding the dog, such as forcing the system-on-chip to restart or cutting off the SoC power supply and re-electrifying and resetting.

The invention discloses a primary step-down and power-on reset circuit, which belongs to the technical field of power management, is applied to an integrated circuit chip with high-voltage input, is used for providing a primary step-down power supply PREVCC for an internal circuit with higher priority and higher power supply requirement in a system, and is integrated with a power-on reset function. Through the circuit design of the invention, two-stage voltage reduction and smooth switching from high voltage VCCHV to medium voltage PREVCC and then to precise power supply VCC are realized, rapid starting of the system is ensured, and the final high-precision power supply requirement is met. Meanwhile, the integrated power-on reset function effectively protects the system at low voltage, and prevents the chip from malfunctioning when the power supply is insufficient. And the high-performance requirement of the whole system on the power supply is met.

The present invention proposes a voltage control circuit and a display device, wherein the voltage control circuit includes a first switch circuit, a power-on reset circuit, a comparison circuit and a switch control circuit. The power-on reset circuit outputs a third level signal or a fourth level signal correspondingly when the power is turned on or off. The comparison circuit compares the supply voltage and outputs a fifth level signal or a sixth level signal correspondingly. The switch control circuit controls the on and off of the first switch circuit based on the level signals output by the power-on reset circuit and the comparison circuit. Through the cooperation of the power-on reset circuit, the comparison circuit and the switch control circuit, the power-off voltage can be detected. When a voltage rebound occurs during the power-off process, the first switch circuit can be effectively kept off to prevent the power management integrated circuit from restarting abnormally, thereby effectively preventing the display panel from abnormally powering on and causing screen abnormalities or flickering problems, thereby improving the display quality and user experience of the display device.

This invention discloses a chip power-on reset circuit, including a sampling unit and a control unit. The control unit and the sampling unit are connected. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback from the sampling unit and the chip's operating voltage range. The control unit includes an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier, and a seventh operational amplifier. One end of the ninth resistor and one end of the thirteenth resistor are connected to a power supply. The other end of the ninth resistor is connected to one end of the tenth resistor and the non-inverting input of the second operational amplifier. The inverting input of the second operational amplifier is connected to one end of the eighth resistor. The output terminal of the second operational amplifier is connected to the other end of the eighth resistor. The other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the non-inverting input of the seventh operational amplifier.

The invention discloses a reset circuit and a power-on reset system, and relates to the technical field of radio frequency transceiver chips, and the circuit comprises a first detection module which is connected with a power supply and is used for obtaining a power supply voltage and generating a first current signal according to the change of the power supply voltage, and the first current signal is in linear correlation with the size of the power supply voltage; the second detection module is connected with the power supply and is used for acquiring the power supply voltage and generating a second current signal according to the change of the power supply voltage, and the second current signal is in quadratic correlation with the size of the power supply voltage; the signal generation module is connected with the first detection module, the second detection module and the to-be-reset module, and is used for outputting a power supply reset signal to the to-be-reset module when the amplitude of the second current signal is greater than the amplitude of the first current signal. Compared with the prior art. According to the invention, the power supply reset signal is automatically generated through internal comparison of two current signals with different change rules, and the to-be-reset module can be reset without an external reference source.

This application relates to the field of integrated circuit technology and provides a power-on reset circuit and method for generating a reset signal. For the problem of the power-on reset protection mechanism, the power-on reset circuit effectively avoids misjudgment and improves the anti-interference ability of the circuit through the cooperation between the comparison module, the selection module, and the resistor-capacitor filtering module. By using the adjustable resistor-capacitor constant switching of the resistor-capacitor filtering module and the output switching of the comparison module. Moreover, without the intervention of external devices, the power-on reset circuit can continuously monitor the power supply voltage signal by itself, thereby adaptively determining when to generate the reset signal and when to abort the generation of the reset signal, which is beneficial to integration and miniaturization, helps to adapt to the application environment and device characteristics, and helps to support the customized requirements and device expansion requirements in application fields such as high-performance computers, automotive electronics, communication devices, and industrial control.

A power-on reset (POR) circuit includes a first transistor and a stack of transistors. The first transistor generates an enable voltage based on a first supply voltage. The enable voltage is a reduced version of the first supply voltage and ramps up based on a ramp-up of the first supply voltage. The stack of transistors generates a control voltage. The control voltage is a reduced version of the enable voltage and ramps up based on the ramp-up of the enable voltage. The control voltage delays ramping of the enable voltage such that the enable voltage ramps up to a first threshold voltage associated with the stack of transistors in a first time period. Further, a reset signal generated by the POR circuit is asserted when the enable voltage exceeds the first threshold voltage at the end of the first time period.

This application relates to a reset circuit, which includes a clock module, a processor, and a reset control module. The reset control module is configured to: send a power-on reset signal to the processor during the power-on startup process of the system to which the reset circuit belongs; the power-on reset signal includes a low level of a first preset duration and a high level of a second preset duration; and clear a power-on reset flag to zero during the low-level period of the power-on reset signal; the processor is configured to: execute a power-on reset after receiving the power-on reset signal; and set the power-on reset flag to 1 after the power-on reset is completed; the reset control module is further configured to: detect the power-on reset flag during the high-level period of the power-on reset signal; and determine that the processor power-on reset is complete when the power-on reset flag is detected to be 1. Embodiments of this application can improve the reliability of the reset circuit.

The utility model discloses a band-gap reference current source and a power-on reset circuit, and relates to the technical field of power-on reset circuits. The reset circuit comprises a low-noise current reference circuit and a reference current and power-on reset signal output circuit, and the signal output end of the low-noise current reference circuit is connected with the signal input end of the reference current and power-on reset signal output circuit. The low-noise current reference circuit is used for generating a current signal required by the reference current and power-on reset signal output circuit, and the reference current and power-on reset signal output circuit is used for processing the input current signal and respectively outputting a band-gap reference current signal and a power-on reset signal. According to the low-noise band-gap reference current circuit, the NPN low-noise transistor and the PMOS transistor are adopted to design the low-noise band-gap reference current circuit, substrate noise, 1 / f flicker noise and far-end phase noise introduced by the NMOS transistor are reduced, and the precision is high.

The present invention discloses a power-on reset circuit and electronic device. The power-on reset circuit includes first, second, and third voltage-dividing resistors, a PNP transistor, a comparator, and a first inverter. The first voltage-dividing resistor, a power supply end of the comparator, and a power supply end of the first inverter are all connected to an input power supply. The first voltage-dividing resistor is connected to the second and third voltage-dividing resistors and the first input end of the comparator. The second voltage-dividing resistor is connected to the second input end of the comparator and the emitter of the PNP transistor. The third voltage-dividing resistor, the base and collector of the PNP transistor, the ground end of the comparator, and the ground end of the first inverter are all grounded. The output end of the comparator is connected to the input end of the first inverter. The output end of the first inverter outputs a reset signal. The present invention uses a structure similar to a bandgap reference to achieve variable reset levels. The PNP transistor does not require an additional mask layer, making process transplantation easier, thereby achieving a low-cost design.

The invention provides a high-precision delay protection low-voltage locking circuit and a control method, and the circuit comprises an analog signal part: a comparison module which is used for comparing a power supply voltage with a reference voltage to generate a corresponding threshold signal; the power-on reset module outputs a first reset signal or a power-on signal to the digital logic part based on the power-on process of the power supply voltage to the power-on reset module; the clock module is used as a clock source for outputting a clock signal; a digital logic section: a reset logic unit that generates an enable reset signal based on a threshold signal and a first reset signal; the frequency division clock generation unit adopts a multi-stage trigger and a logic gate to form a frequency division counter, performs frequency division operation on a clock signal, and provides a time reference for delay control; and the enabling generation unit is used for enabling an enabling signal to be output only when the voltage is stable and the delay is satisfied through logic combination analysis of the clock signal after frequency division and a threshold signal.

The application discloses a power-on reset circuit of a multi-power supply chip, a chip and electronic equipment, and relates to the technical field of chips. The power-on reset circuit comprises a plurality of power supply detection circuits, the input ends of each power supply detection circuit are respectively connected to a corresponding power supply, and each power supply detection circuit is configured to output a detection completion signal when detecting that the corresponding power supply voltage reaches a preset detection threshold; and a logic processing circuit, the input end of the logic processing circuit is electrically connected to the output ends of the plurality of power supply detection circuits, and the logic processing circuit is configured to output a power-on reset signal when simultaneously receiving all detection completion signals. The application is configured with independent voltage detection modules for each power supply of the multi-power supply chip, and cooperates with logic centralized processing of detection signals, can adapt to any power supply power-on sequence, realizes independent voltage detection of each power supply, ensures that a reset signal is released only when all power supplies reach a preset detection threshold, fundamentally avoids abnormal work of the chip at a low voltage, and can greatly reduce the design complexity of a multi-power supply POR circuit.

Examples of the present disclosure provide a memory device and an operation method thereof, a memory system and a storage medium. The memory device includes: a memory cell array, and a peripheral circuit coupled with the memory cell array, wherein the peripheral circuit is configured to: before performing a power on reset operation, set all state information of a plurality of main memory areas in a page buffer to a normal state; in the process of performing the power on reset operation, match a second address of each of the plurality of main memory areas with a first address in a register; and determine, according to a match result, whether to modify state information of a respective main memory area in the page buffer to a fault state.