180 results about "Interrupt request" patented technology

The invention relates to the field of energy-saving computing, and discloses a low-power-consumption control method and system of a controller, which are used for realizing prediction-sleep-wake-up-response full-link hardware in the controller. Time sequence state data of a controlled object is collected in real time, and a predictive sleep window value is dynamically generated by utilizing a predictive cooperative computing unit, so that intelligent scheduling of sleep and awakening is realized, and the power consumption of a controller is effectively reduced. Meanwhile, in combination with the technologies of threshold comparison, DMA data transmission optimization and the like, the data processing efficiency is improved, and invalid data transmission is reduced. And on the awakening mechanism, an asynchronous awakening circuit and an interrupt request mechanism are adopted to ensure that power supply is quickly recovered and control response is executed when an effective instruction is received, so that the real-time performance of the system is guaranteed. According to the invention, a prediction algorithm, hardware acceleration and an intelligent scheduling technology are fused, the performance of the controller is ensured, the power consumption is obviously reduced, and the endurance time of equipment is prolonged.

The invention aims to provide a communication method of a multi-core system and the multi-core system, and relates to the technical field of computers. The method applied to the Mailbox hardware module in the multi-core system comprises the following steps: receiving an operation configuration instruction of a processor core to the Mailbox hardware module; under the condition that an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address according to a communication channel expected to be used so as to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that the communication channels of the mailbox source registers recording the source addresses are all used, and the destination addresses recorded by the mailbox target registers of the communication channels are all transmitted. Therefore, the communication concurrency and throughput of the multi-core system can be improved. And meanwhile, the communication reliability of the multi-core system can be improved.

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

The invention discloses an ARMv8-based virtual machine interrupt through routing method, which comprises the following steps that: a Hypervisor directly routes a physical interrupt to an EL1 through configuration, sets a top page table address of a vCPU (Virtual Central Processing Unit) and a Hypervisor control register at the same time, and sets a vcpudid flag bit for indicating whether the vCPU adopts a virtual interrupt injection mechanism or a physical interrupt through routing mechanism; and judging whether an interrupt through routing condition is met or not so as to determine whether an interrupt through routing mechanism or a virtual interrupt injection mechanism is adopted, periodically judging whether a switching condition is met or not when the interrupt through routing mechanism is adopted, and switching from the interrupt through routing mechanism to the virtual interrupt injection mechanism if the switching condition is met. The method is compatible with two interrupt controller specifications of GICv2 and GICv3, supports the virtual machine and the hypervisor to respectively and independently respond to respective corresponding interrupt requests, and meanwhile, the method has the capability of dynamically switching an interrupt routing mechanism during the system operation period, so that the flexibility of interrupt processing and the expandability of the system are improved.

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

The invention belongs to the field of electronic equipment communication, and discloses an SPI bus active hang-up prevention method and device based on a clock line state, and the method comprises the steps: presetting a first level signal of an SPI clock line in an idle state, and presetting a hang-up prevention counting threshold; the SPI controller monitors a second level signal of the clock line in real time; when the condition that the second level signal is inconsistent with the first level signal continues, an internal counter is started for counting; when the count value of the counter reaches an anti-hanging counting threshold value, the SPI controller judges that the clock line is hung and sets an internal hanging state flag; if the SPI is enabled to hang the interrupt function through the software configuration, the SPI controller sends an interrupt request signal to the processor; and the processor responds to the interrupt request signal and executes a corresponding fault recovery operation. The state of the clock line is monitored in real time through the SPI controller and compared with the preset idle level, and the recognition process can be started at the moment that the clock line is pulled dead.

The invention relates to the technical field of computers, and discloses a method, device and equipment for hot plugging of PF equipment, a medium and a program product, and the method comprises the following steps: configuring at least one hot-pluggable PF equipment for a data processing unit; the PF equipment supports multiple equipment types, and the initial state is invisible to the host; in response to a first hot plug instruction for hot plug of the first device type, determining a first PF device which is invisible to the host at present; the identification information of the first PF equipment is configured to be first identification information corresponding to the first equipment type, and the state of the first PF equipment is updated to be visible to the host; sending a first interrupt request to the host; the first interrupt request is used for notifying the host to scan equipment. According to the method and the device, the PF equipment of the specified equipment type can be hot-plugged in the corresponding PF slot position according to the hot-plugging instruction of the user, and is presented to the host for use, so that flexible configuration of different equipment types can be realized, and various requirements of the user are met.

An interrupt processing method includes when a first interrupt request is triggered, determining a target CPU that responds to the first interrupt request; determining a first target interrupt running entity in the target CPU; scheduling a target thread from a user mode to a kernel mode; replacing a running entity in the target thread with the first target interrupt running entity; and scheduling the target thread including the first target interrupt running entity to the user mode, and running the first target interrupt running entity by using the target CPU.

The invention discloses a network flow processing method, device and equipment and a storage medium, and relates to the technical field of system resource management, and the method comprises the steps: monitoring a current network load of a computer system, and determining a to-be-isolated processor core from the computer system when the current network load is judged to meet a preset high load condition; binding the network data packet buffer area and the network protocol stack data structure to a high-speed cache of the processor core to be isolated, and distributing a target buffer pool for the processor core to be isolated in a memory area of a computer system to obtain a target processor core; the network data packet buffer area is used for storing a data packet related to an interrupt request in the current network flow of the computer system, and the network protocol stack data structure is a data structure related to the data packet; and respectively processing the interrupt request and other network flows through the target processor core and other processor cores. Therefore, high-intensity load change can be coped with in a mode of isolating the processor cores.

The invention discloses a resource binding method, electronic equipment and a storage medium. The method comprises the steps that in response to an interrupt request to be processed of a target instance, a target binding strategy is determined, and the target binding strategy is used for determining that a network card interface corresponding to the interrupt request and processor resources to be bound with the interrupt request are located in the same resource node of a processor architecture; and carrying out resource binding processing on the interrupt request according to the target binding strategy to obtain a binding processing result. The technical problem of poor network performance caused by sequential binding of processor resources only according to the interrupt number in the prior art is solved.

The invention relates to the technical field of chips, and provides an interrupt module verification method and device, a medium and a program product, the method comprises the following steps: when it is monitored that an interrupt module generates an external observable behavior, comparing monitored behavior information with a reference value of the external observable behavior, and verifying the correctness of the external observable behavior; performing state calculation on the interrupt request input to the interrupt module, and determining an internal processing state of the interrupt request; an internal register state of the interrupt module is verified based on an internal processing state of the interrupt request. According to the invention, through a mode of combining black box verification of external observable behaviors with white box verification based on an internal processing state, comprehensive, deep and efficient function verification of a complex interrupt module is realized.

The invention discloses an interrupt request processing method, device and equipment and a storage medium, and relates to the technical field of computer system optimizing.The method comprises the steps that according to monitored real-time interrupt loads of a plurality of processor cores of a server, a low-load core and a high-load core are divided; generating a migration decision result representing that the target interrupt request corresponding to the high-load core is migrated to the target processor core; the target processor core is a processor core, corresponding to the same NUMA domain as the high-load core, in the low-load cores; updating the affinity file corresponding to the target processor core by using the migration decision result, and adjusting the target mapping table in combination with the updated affinity file, so as to execute the target interrupt request based on the adjusted mapping table; the affinity file represents a binding relationship between the interrupt request and the processor core, and the target mapping table represents a data transmission relationship between a processing queue of a network card related to the interrupt request and the processor core. Therefore, the interrupt request can be dynamically migrated, and the problem of interrupt overload is relieved.

The present disclosure relates to a method and system for managing a meeting session. In accordance with one example, there is provided a method of managing a meeting session on a server that manages the meeting session, the meeting session comprising one or more participant devices and a presenter device. The method comprises receiving one or more break request messages from the participant devices, and sending a break message to the participant devices, the break message causing a break notification to be displayed on a display of the participant devices.

An interrupt processing method. The method comprises: acquiring a first interrupt request; processing the first interrupt request by means of a first interrupt processing method; acquiring a second interrupt request; and processing the second interrupt request by means of a second interrupt processing method, wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method is different from the second interrupt processing method. In the present application, different interrupt processing methods may be used to process different interrupt requests. Since various types of interrupt requests are not processed by means of a fixed interrupt processing method, a corresponding interrupt request may be configured on the basis of a service scenario corresponding to the interrupt request.

Systems or methods of the present disclosure may provide for interrupt migration using a processor and / or system on a chip. The system includes multiple processing cores and an interrupt controller. The interrupt controller includes an input terminal configured to receive an interrupt request and an interrupt controller timer. The interrupt controller also includes an output terminal configured to output an interrupt based on the interrupt request. Furthermore, the interrupt controller includes an interface configuration and status circuitry configured to track a period of time that the interrupt is transmitted to a first processing core of the multiple processing cores.

The invention discloses a communication method, electronic equipment, a computer program product and a storage medium, which are applied to the technical field of communication, and comprise the following steps: when an interrupt request generated by a slave is detected, analyzing a slave address and taking the slave address as an index of an interrupt control table, and reading response information from the interrupt control table; the interrupt control table comprises response information corresponding to all slave addresses; the first equipment address table and the second equipment address table jointly form equipment information of all slaves, the second equipment address table and the interrupt control table are both stored in host hardware, and the first equipment address table is stored in a memory; when the data needs to be read from the slave, inquiring whether the slave address exists in the first equipment address table or not; and if yes, performing table item exchange, otherwise, receiving communication information issued by the host program and realizing communication with the slave. By applying the scheme of the invention, the problem of frequent replacement of slave equipment information can be effectively solved, and excessive host hardware resources cannot be consumed.

This invention discloses a master-slave task synchronization method, device, controller, and rail train, relating to the field of rail transit technology. The method includes: the current controller identifying the master-slave presence status on the rail train's chassis; determining the system master control status corresponding to the current controller based on the master-slave presence status; if the system master control status is in master control mode, generating an interrupt request at a first preset time interval, performing synchronization task processing according to the interrupt request, and sending the interrupt request to other present controllers. This invention achieves automatic master-slave controller identification by determining the system master control status corresponding to the current controller based on the identified master-slave presence status; by having one controller acting as the system master controller generate and send an interrupt request to other controllers acting as system slave controllers, all controllers can perform strict master-slave task synchronization according to the interrupt request of the system master controller, thus improving the accuracy of master-slave task synchronization.

The invention provides an abnormal event processing method, electronic equipment and a storage medium, and relates to the technical field of communication. The electronic device detects a first interrupt request from a touch chip. In response to the first interrupt request, judging whether the touch chip has an interrupt abnormal event or not; and if the interruption abnormal event occurs in the touch chip, the electronic equipment sends first notification information to an upper system process, and shields an interruption request of the touch chip. The first notification information is used for notifying the system process not to indicate to start the interrupt response. By means of the mode, in the process that the interruption abnormal event happens to the touch control chip, the electronic device does not start the interruption response of the interruption request again, and the influence of the interruption abnormal event is reduced.

The application relates to the technical field of interrupt control, and discloses an interrupt control method, an interrupt controller, computer equipment and a storage medium, the method is applied to an interrupt controller, the method comprises the following steps: receiving a plurality of interrupt requests; determining the current priority of each interrupt request in the plurality of interrupt requests according to the N-time historical processing time length of each interrupt request in the plurality of interrupt requests, wherein N is a positive integer; and sending the plurality of interrupt requests to a processor according to the sequence of the current priorities of the plurality of interrupt requests. The application can flexibly adjust the priorities of the plurality of interrupt requests according to actual application scenes, and improves the performance of a system.

This application discloses an interrupt control device and method based on a RISC-V architecture, relating to the field of interrupt handling technology. The device includes a processor, an interrupt controller, and a data preparation module. The interrupt controller is used to acquire a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; and generates a first interrupt signal based on the acquired first interrupt request. The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information. The processor is used to suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handler, and acquire the target data corresponding to the interrupt handler from the data preparation module.

The invention provides a processor system and an interrupt response method. In the processor system, an interrupt controller is used for setting the state of a control register, receiving an interrupt request signal which is sent from the outside and is used for requesting to execute an interrupt service program, setting the state of the control register to be a first state value when the interrupt request signal is received, and executing the interrupt service program after the interrupt server program is executed. Setting the state of the control register as a second state value; the multiplexer is used for reading the state value of the control register, when the read state value of the control register is a first state value, the multiplexer is communicated with the shadow register group and the arithmetic unit, and when the read state value of the control register is a second state value, the multiplexer is communicated with the main register group and the arithmetic unit; the main register group is used for storing data when the main program is operated; and the shadow register group is used for storing data when the interrupt server program runs. The delay in the interrupt response process can be reduced, and the system performance is improved.

Embodiments of the present disclosure provide an interrupt controller, a chip, a computer device, an interrupt control method and a medium. The interrupt controller comprises a configuration unit, a first selection unit and a normalization processing unit. The normalization processing unit comprises a plurality of normalization sub-units. Each normalization sub-unit is connected to the first selection unit. Different normalization sub-units adopt different normalization processing modes. The configuration unit is configured to obtain first configuration information. The first configuration information is generated in advance based on the type of an interrupt request. Each type of interrupt request corresponds to a normalization processing mode. The first selection unit is configured to send the interrupt request to one of the plurality of normalization sub-units based on the first configuration information. Each normalization sub-unit of the plurality of normalization sub-units is configured to normalize the received interrupt request by using the normalization processing mode corresponding to the sub-unit.

Embodiments of the present application disclose a data access method, a data access system and a storage medium. After receiving a migration interrupt request sent by a target processing unit, a central processing unit of a processing unit cluster according to a virtual address of target data in the migration interrupt request controls the target processing unit to acquire an address mapping relationship of the target data, and controls a source processing unit to migrate the target data to the target processing unit, and then controls the target processing unit to update the address mapping relationship of the target data after the target data is migrated, so that the target processing unit reads the target data from the memory according to the updated address mapping relationship. In the embodiments of the present application, the target processing unit can access data in the source processing unit according to the received address mapping relationship without waiting for the data migration to be completed, so that the data access delay can be effectively reduced, and the data processing efficiency is improved.

A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

Disclosed are a method and apparatus for optimizing server system interrupts, a device and a medium, which relate to the field of servers. The method is applied to a server system, and comprises: when a peripheral driver of a kernel space monitors an interrupt request signal sent by a hardware peripheral, reading a hardware event queue in the hardware peripheral, so as to acquire a target hardware event in the hardware event queue; then, converting the target hardware event into a target software event by using the peripheral driver, and writing the target software event into a preset global event queue; reading the target software event in the global event queue by means of a user space, and forwarding the target software event to a corresponding target service process by means of the user space, such that the target service process processes the target. In this way, by using hardware interrupt coalescing and software event coalescing techniques, this solution may not only reduce the interrupt processing overhead, but also reduce the processor utilization.

A touch circuit includes a micro control circuit and a readout integrated circuit configured to communicate with the micro control circuit though a selection signal line, a clock signal line, a master output slave input (MOSI) signal line, and a master input slate output (MISO) signal line. In a first period, the readout integrated circuit generates a first interrupt request signal representing completion of touch sensing, and transfers the first interrupt request signal to the micro control circuit through the MISO signal line. In a second period which differs from the first period, the readout integrated circuit generates a second interrupt request signal, representing a kind of error and whether an operation state thereof is normal, and transfers the second interrupt request signal to the micro control circuit through the MOSI signal line.

The invention provides a substrate management controller self-recovery method and device, computer equipment and a readable storage medium, and the method comprises the steps: determining a server component controller related to an interrupt request when an interrupt storm occurs; storing the fault associated information of the server component controller to a reserved memory area of the baseboard management controller; when the substrate management controller is restarted, fault associated information in the reserved memory area is obtained through the bootstrap program; loading equipment tree data of the baseboard management controller into a memory of the baseboard management controller through the bootstrap program, and modifying the equipment tree data based on the fault associated information; and starting the baseboard management controller based on the modified equipment tree data. According to the technical scheme, the self-recovery capability of the substrate management controller is improved, and the stability of the substrate management controller is enhanced.

The invention relates to a consistency group management method and device, a storage management system, a storage medium and a program product. Comprising the steps that when a consistency group snapshot is created, tasks to be processed of a consistency group are solidified in a system disk; sending a silence request to each member volume corresponding to the consistency group; in the process of creating the snapshots corresponding to the member volumes, if a storage pool to which any member volume belongs fails, solidifying an interrupt mark of a to-be-processed task in a system disk, and sending an interrupt request to each member volume; the system disk is a combination of all disks in the storage management system; member volumes included in the consistency group are volumes in a plurality of different storage pools; each storage pool is composed of different disks in the storage management system; the silence request is used for indicating each member volume to stop receiving and processing a new input / output IO request. According to the method, the consistency group can be managed when the storage pool fails.

The application discloses a kind of SSE streaming output interruption control method, device, server and medium.The application relates to data transmission technical field, wherein the method comprises: obtaining the data transmission interruption request sent by client, the data transmission interruption request includes the unique identification of the client;According to the unique identification of the client, the corresponding data transmission control field stored is inquired and the data transmission control field is updated, the data transmission control field is used to identify whether the streaming output of current data is interrupted;According to the query result of the data transmission control field, it is judged whether the streaming output of current data is interrupted.The application can actively interrupt the streaming output of server, and there is no network disconnection exception in the whole process of actively interrupting streaming output, so as to not affect the performance of server.

The present application discloses an integrated circuit, a method and a system for processing interrupt requests, and belongs to the field of computer technology. The integrated circuit includes one or more processor clusters, and a coupled interrupt circuit. The interrupt circuit is used to receive an interrupt request through a first interrupt node in a multi-level interrupt node, query a first memory according to an interrupt identifier of the interrupt request, and obtain a first identifier corresponding to the interrupt identifier. In the case where the first identifier indicates a second interrupt node in a multi-level interrupt node, an interrupt request is sent to a target processor cluster through the first interrupt node and the second interrupt node, or in the case where the first identifier indicates a target processor cluster, an interrupt request is sent to the target processor cluster through the first interrupt node, so that the target processor cluster processes the interrupt request. The first interrupt node routes the interrupt request quickly and flexibly according to the first memory, thereby improving the processing efficiency of the interrupt request.