119 results about "Interrupt request" patented technology

An interrupt processing method includes when a first interrupt request is triggered, determining a target CPU that responds to the first interrupt request; determining a first target interrupt running entity in the target CPU; scheduling a target thread from a user mode to a kernel mode; replacing a running entity in the target thread with the first target interrupt running entity; and scheduling the target thread including the first target interrupt running entity to the user mode, and running the first target interrupt running entity by using the target CPU.

The invention discloses a network flow processing method, device and equipment and a storage medium, and relates to the technical field of system resource management, and the method comprises the steps: monitoring a current network load of a computer system, and determining a to-be-isolated processor core from the computer system when the current network load is judged to meet a preset high load condition; binding the network data packet buffer area and the network protocol stack data structure to a high-speed cache of the processor core to be isolated, and distributing a target buffer pool for the processor core to be isolated in a memory area of a computer system to obtain a target processor core; the network data packet buffer area is used for storing a data packet related to an interrupt request in the current network flow of the computer system, and the network protocol stack data structure is a data structure related to the data packet; and respectively processing the interrupt request and other network flows through the target processor core and other processor cores. Therefore, high-intensity load change can be coped with in a mode of isolating the processor cores.

The invention relates to the technical field of chips, and provides an interrupt module verification method and device, a medium and a program product, the method comprises the following steps: when it is monitored that an interrupt module generates an external observable behavior, comparing monitored behavior information with a reference value of the external observable behavior, and verifying the correctness of the external observable behavior; performing state calculation on the interrupt request input to the interrupt module, and determining an internal processing state of the interrupt request; an internal register state of the interrupt module is verified based on an internal processing state of the interrupt request. According to the invention, through a mode of combining black box verification of external observable behaviors with white box verification based on an internal processing state, comprehensive, deep and efficient function verification of a complex interrupt module is realized.

The invention discloses an interrupt request processing method, device and equipment and a storage medium, and relates to the technical field of computer system optimizing.The method comprises the steps that according to monitored real-time interrupt loads of a plurality of processor cores of a server, a low-load core and a high-load core are divided; generating a migration decision result representing that the target interrupt request corresponding to the high-load core is migrated to the target processor core; the target processor core is a processor core, corresponding to the same NUMA domain as the high-load core, in the low-load cores; updating the affinity file corresponding to the target processor core by using the migration decision result, and adjusting the target mapping table in combination with the updated affinity file, so as to execute the target interrupt request based on the adjusted mapping table; the affinity file represents a binding relationship between the interrupt request and the processor core, and the target mapping table represents a data transmission relationship between a processing queue of a network card related to the interrupt request and the processor core. Therefore, the interrupt request can be dynamically migrated, and the problem of interrupt overload is relieved.

The present disclosure relates to a method and system for managing a meeting session. In accordance with one example, there is provided a method of managing a meeting session on a server that manages the meeting session, the meeting session comprising one or more participant devices and a presenter device. The method comprises receiving one or more break request messages from the participant devices, and sending a break message to the participant devices, the break message causing a break notification to be displayed on a display of the participant devices.

An interrupt processing method. The method comprises: acquiring a first interrupt request; processing the first interrupt request by means of a first interrupt processing method; acquiring a second interrupt request; and processing the second interrupt request by means of a second interrupt processing method, wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method is different from the second interrupt processing method. In the present application, different interrupt processing methods may be used to process different interrupt requests. Since various types of interrupt requests are not processed by means of a fixed interrupt processing method, a corresponding interrupt request may be configured on the basis of a service scenario corresponding to the interrupt request.

The invention discloses a communication method, electronic equipment, a computer program product and a storage medium, which are applied to the technical field of communication, and comprise the following steps: when an interrupt request generated by a slave is detected, analyzing a slave address and taking the slave address as an index of an interrupt control table, and reading response information from the interrupt control table; the interrupt control table comprises response information corresponding to all slave addresses; the first equipment address table and the second equipment address table jointly form equipment information of all slaves, the second equipment address table and the interrupt control table are both stored in host hardware, and the first equipment address table is stored in a memory; when the data needs to be read from the slave, inquiring whether the slave address exists in the first equipment address table or not; and if yes, performing table item exchange, otherwise, receiving communication information issued by the host program and realizing communication with the slave. By applying the scheme of the invention, the problem of frequent replacement of slave equipment information can be effectively solved, and excessive host hardware resources cannot be consumed.

This invention discloses a master-slave task synchronization method, device, controller, and rail train, relating to the field of rail transit technology. The method includes: the current controller identifying the master-slave presence status on the rail train's chassis; determining the system master control status corresponding to the current controller based on the master-slave presence status; if the system master control status is in master control mode, generating an interrupt request at a first preset time interval, performing synchronization task processing according to the interrupt request, and sending the interrupt request to other present controllers. This invention achieves automatic master-slave controller identification by determining the system master control status corresponding to the current controller based on the identified master-slave presence status; by having one controller acting as the system master controller generate and send an interrupt request to other controllers acting as system slave controllers, all controllers can perform strict master-slave task synchronization according to the interrupt request of the system master controller, thus improving the accuracy of master-slave task synchronization.

The application relates to the technical field of interrupt control, and discloses an interrupt control method, an interrupt controller, computer equipment and a storage medium, the method is applied to an interrupt controller, the method comprises the following steps: receiving a plurality of interrupt requests; determining the current priority of each interrupt request in the plurality of interrupt requests according to the N-time historical processing time length of each interrupt request in the plurality of interrupt requests, wherein N is a positive integer; and sending the plurality of interrupt requests to a processor according to the sequence of the current priorities of the plurality of interrupt requests. The application can flexibly adjust the priorities of the plurality of interrupt requests according to actual application scenes, and improves the performance of a system.

This application discloses an interrupt control device and method based on a RISC-V architecture, relating to the field of interrupt handling technology. The device includes a processor, an interrupt controller, and a data preparation module. The interrupt controller is used to acquire a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; and generates a first interrupt signal based on the acquired first interrupt request. The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information. The processor is used to suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handler, and acquire the target data corresponding to the interrupt handler from the data preparation module.

The invention provides a processor system and an interrupt response method. In the processor system, an interrupt controller is used for setting the state of a control register, receiving an interrupt request signal which is sent from the outside and is used for requesting to execute an interrupt service program, setting the state of the control register to be a first state value when the interrupt request signal is received, and executing the interrupt service program after the interrupt server program is executed. Setting the state of the control register as a second state value; the multiplexer is used for reading the state value of the control register, when the read state value of the control register is a first state value, the multiplexer is communicated with the shadow register group and the arithmetic unit, and when the read state value of the control register is a second state value, the multiplexer is communicated with the main register group and the arithmetic unit; the main register group is used for storing data when the main program is operated; and the shadow register group is used for storing data when the interrupt server program runs. The delay in the interrupt response process can be reduced, and the system performance is improved.

Embodiments of the present disclosure provide an interrupt controller, a chip, a computer device, an interrupt control method and a medium. The interrupt controller comprises a configuration unit, a first selection unit and a normalization processing unit. The normalization processing unit comprises a plurality of normalization sub-units. Each normalization sub-unit is connected to the first selection unit. Different normalization sub-units adopt different normalization processing modes. The configuration unit is configured to obtain first configuration information. The first configuration information is generated in advance based on the type of an interrupt request. Each type of interrupt request corresponds to a normalization processing mode. The first selection unit is configured to send the interrupt request to one of the plurality of normalization sub-units based on the first configuration information. Each normalization sub-unit of the plurality of normalization sub-units is configured to normalize the received interrupt request by using the normalization processing mode corresponding to the sub-unit.

Embodiments of the present application disclose a data access method, a data access system and a storage medium. After receiving a migration interrupt request sent by a target processing unit, a central processing unit of a processing unit cluster according to a virtual address of target data in the migration interrupt request controls the target processing unit to acquire an address mapping relationship of the target data, and controls a source processing unit to migrate the target data to the target processing unit, and then controls the target processing unit to update the address mapping relationship of the target data after the target data is migrated, so that the target processing unit reads the target data from the memory according to the updated address mapping relationship. In the embodiments of the present application, the target processing unit can access data in the source processing unit according to the received address mapping relationship without waiting for the data migration to be completed, so that the data access delay can be effectively reduced, and the data processing efficiency is improved.

A trusted computing technology is shown. An isolated memory stores a security interrupt descriptor table (SIDT) to correspond to security interrupts triggered by security peripherals. A first register of the trusted core stores a first address pointing to the SIDT. A local advanced programmable interrupt controller in the trusted core provides an interrupt arbiter that arbitrates between peripheral interrupts received from the chipset. When producing an arbitration result showing that a target interrupt is a security interrupt, the interrupt arbiter outputs a security interrupt request and a security interrupt vector to trigger the trusted core to search the SIDT indicated by the first register, to get a target security interrupt descriptor for execution of the corresponding interrupt program.

Disclosed are a method and apparatus for optimizing server system interrupts, a device and a medium, which relate to the field of servers. The method is applied to a server system, and comprises: when a peripheral driver of a kernel space monitors an interrupt request signal sent by a hardware peripheral, reading a hardware event queue in the hardware peripheral, so as to acquire a target hardware event in the hardware event queue; then, converting the target hardware event into a target software event by using the peripheral driver, and writing the target software event into a preset global event queue; reading the target software event in the global event queue by means of a user space, and forwarding the target software event to a corresponding target service process by means of the user space, such that the target service process processes the target. In this way, by using hardware interrupt coalescing and software event coalescing techniques, this solution may not only reduce the interrupt processing overhead, but also reduce the processor utilization.

A touch circuit includes a micro control circuit and a readout integrated circuit configured to communicate with the micro control circuit though a selection signal line, a clock signal line, a master output slave input (MOSI) signal line, and a master input slate output (MISO) signal line. In a first period, the readout integrated circuit generates a first interrupt request signal representing completion of touch sensing, and transfers the first interrupt request signal to the micro control circuit through the MISO signal line. In a second period which differs from the first period, the readout integrated circuit generates a second interrupt request signal, representing a kind of error and whether an operation state thereof is normal, and transfers the second interrupt request signal to the micro control circuit through the MOSI signal line.

The invention provides a substrate management controller self-recovery method and device, computer equipment and a readable storage medium, and the method comprises the steps: determining a server component controller related to an interrupt request when an interrupt storm occurs; storing the fault associated information of the server component controller to a reserved memory area of the baseboard management controller; when the substrate management controller is restarted, fault associated information in the reserved memory area is obtained through the bootstrap program; loading equipment tree data of the baseboard management controller into a memory of the baseboard management controller through the bootstrap program, and modifying the equipment tree data based on the fault associated information; and starting the baseboard management controller based on the modified equipment tree data. According to the technical scheme, the self-recovery capability of the substrate management controller is improved, and the stability of the substrate management controller is enhanced.

The invention relates to a consistency group management method and device, a storage management system, a storage medium and a program product. Comprising the steps that when a consistency group snapshot is created, tasks to be processed of a consistency group are solidified in a system disk; sending a silence request to each member volume corresponding to the consistency group; in the process of creating the snapshots corresponding to the member volumes, if a storage pool to which any member volume belongs fails, solidifying an interrupt mark of a to-be-processed task in a system disk, and sending an interrupt request to each member volume; the system disk is a combination of all disks in the storage management system; member volumes included in the consistency group are volumes in a plurality of different storage pools; each storage pool is composed of different disks in the storage management system; the silence request is used for indicating each member volume to stop receiving and processing a new input / output IO request. According to the method, the consistency group can be managed when the storage pool fails.

A high-throughput confidential computing method and system based on a RISC-V architecture are provided. The method includes: S1, acquiring a hardware device tree configuration file to classify each physical resource into a normal partition or a security partition; S2, loading a security manager; S3, mapping memory resources in the normal and security partitions to the normal and security domains, respectively; registering CPU resources in the normal and security partitions to the normal and security domains, respectively; and registering an interrupt handler function; S4, linking an image file of a security file system with a security kernel file to generate an operating system image of the security domain; S5, reading the operating system image, and loading the same to a memory address of the security domain; and S6, executing the initialization of the security domain according to an interrupt request from the normal domain.

The invention discloses an interrupt event processing method and device, a storage medium and a program product, and relates to the technical field of servers, the method comprises the following steps: receiving a target interrupt request; in response to the fact that the target interrupt request is the first interrupt request, executing a first task corresponding to the first interrupt request to generate an execution result, and locally updating the basic input / output system graphical user interface according to the execution result; the first interrupt request is an interrupt request related to a basic input / output system graphical user interface; in response to the fact that the target interrupt request is a second interrupt request, a second task corresponding to the second interrupt request is added into the delay processing list, and the second interrupt request and the first interrupt request are of different interrupt types. Through the method, the response efficiency of the BIOS GUI can be improved.

An RTOS includes an event processor construct. The event processor has a task priority and an event processor handler. A stack for the event processor is allocated by the RTOS. The event processor handler is called by the RTOS each time an event is posted by an interrupt request handler or another task. Once processing of the event completes, the event processor handler returns (as opposed to remaining in an infinite loop) thereby allowing the stack allocated to the event processor to not be retained on entry into a sleep state and the memory bank containing the stack to be powered down during a sleep state.

The application discloses a method for transmitting external interruption of a vehicle display screen end by using a DP extension protocol, and comprises the following steps: an Aux GPIO suspension identifier is predefined as a special identifier bit in an AUX register for judging external GPIO interruption, and a receiving end feeds back external interruption to a source end; when the remote device gives an interruption, the receiving end identifies the interruption request through a local GPIO, writes an interruption effective identifier into a DPCD SINK SPECIFIC IRQ address through a DP module, sets the Aux GPIO suspension identifier to 1, pulls down an HPD pin, and notifies the source end; the source end reads corresponding and judges whether there is additional interruption after detecting the pull-down; if yes, the source end reads an interruption judgment identifier bit to judge whether it is external GPIO interruption; and the source end calls an external GPIO interruption processing function after clearing the identifier. The application can complete interruption notification and data interaction without a serializer, a deserializer, and without relying on an external interruption signal.

The embodiment of the invention provides a calling method and device for an interrupt communication system between para-virtualization processors, electronic equipment and a readable storage medium. The method comprises the steps that interrupt characteristics between the para-virtualization processors are configured for virtual processors; if the virtual processor starts the interrupt characteristic between the para-virtualization processors, setting an interrupt call function for the virtual processor so as to call the interrupt call function when an interrupt request is sent; and in response to calling of the interrupt calling function, directly updating the interrupt descriptor corresponding to the target virtual processor so as to enable the target virtual processor to process the interrupt request. According to the embodiment of the invention, by setting the interrupt calling function, when the interrupt request is subsequently transmitted, the interrupt descriptor of the target virtual processor is directly updated so as to process the interrupt request without intervention of a virtual machine monitor, so that the number of times that the virtual machine returns to the host machine state from the client machine state is reduced, and the performance of the virtual machine is improved.

This invention discloses a design method for a RISC-V AIA interrupt-configurable multi-privilege-level IMSIC controller, comprising: setting a programmable configuration register MS_CUT_CFG in the IMSIC to dynamically allocate interrupt file resources for machine mode (M-mode) and supervisor mode (S-mode) at runtime; controlling the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG to achieve dynamic reuse of interrupt file resources; physically sharing the same hardware register array for the interrupt enable register group (IE) and interrupt suspend register group (IP) of machine mode (M-mode) and supervisor mode (S-mode); and mapping suspended but executable interrupt requests to the corresponding privilege level and submitting them to the processor core through an interrupt arbitration circuit based on the current value of the configuration register. This invention overcomes the limitations of the static resource configuration strategy for IMSIC interrupt files, significantly enhancing the flexibility and dynamic scenario adaptability of RISC-V AIA interrupt applications.

The application discloses a kind of interrupt fault tolerance and acceleration response method under heterogeneous platform, including, in interrupt service program, response accelerator message signal interrupt, read the first interrupt state indicating data transmission completion and the second interrupt state of user logic interrupt request, if both are no interrupt, be identified as user logic interrupt, increment kernel state interrupt count value, if second state has interrupt request, also increment count value, if the first state shows data transmission completion, then handle as data transmission interrupt;In application layer thread, obtain kernel state interrupt count value, compare with application layer processing count value, if kernel state count value is greater than application layer count value, send data to accelerator and increment application layer count value, if equal, thread hibernates first preset duration and retry, the application cooperates with application layer, solves interrupt loss problem, uses IOCTL polling acceleration response, and ensures system stability by intelligent hibernation.

The invention relates to a heterogeneous multi-core inter-core communication method, a heterogeneous multi-core processor, a storage medium, a controller, a chip device and a vehicle, and the method comprises the steps: determining the physical positions of a source core and a target core and the data size threshold value of to-be-transmitted communication data; selecting to generate an interrupt request through software to trigger a shared memory to transmit the communication data or transmit the communication data through a register of a message processing unit; wherein the source core is a sending end of communication data, and the target core is a receiving end of the communication data; the source core and the target core are processor cores of different architecture types integrated in a heterogeneous multi-core processor packaged by the same chip. According to the technical scheme, the hierarchical communication of the software interrupt direct connection in the same processor cluster and the message processing unit hardware channel between the clusters is constructed, and the register direct transmission or shared memory transmission path is dynamically selected in combination with the data volume threshold, so that the efficiency of inter-core communication in a high-concurrency scene is improved.

The application discloses a method, device and medium for improving the execution efficiency of a computing-intensive task, relates to the technical field of intensive task processing, and comprises the following steps: in response to an interrupt request received by a multi-core CPU system, determining whether a source CPU for processing the interrupt request is bound to a task; if it is determined that the source CPU is bound to the task, determining a target topology level adapted to the interrupt request according to an interrupt source device of the interrupt request, then determining a target topology node with the lowest interrupt load from the target topology level of the multi-core CPU system, and setting an interrupt affinity mask of the interrupt request to a mask of the target topology node; if it is determined that the source CPU is not bound to the task, then determining that the interrupt request is processed by the source CPU. The application realizes the purpose of considering the influence of interrupt processing on the execution efficiency of a computing-intensive task from the perspective of an external factor, does not need to deploy expensive hardware, does not need to modify the task at the code level, and improves the execution efficiency of the computing-intensive task.

A system comprises a physical processor to execute a virtual machine manager to run, on a logical core, a virtual machine including a guest user application and a virtual CPU. Circuitry coupled to an external device is to receive an interrupt request from the external device for the guest user application, locate a first interrupt data structure associated with the guest user application, generate a first interrupt with the first interrupt data structure based on a first interrupt vector for the interrupt request, locate a second interrupt data structure associated with the virtual CPU, and generate a first notification interrupt for the virtual CPU with the second interrupt data structure based on a first notification vector in the first interrupt data structure. The circuitry may generate a second notification interrupt for the logical core using a second notification vector and a logical core identifier from the second interrupt data structure.

The invention relates to a cluster distributed virtual interrupt control method, device and system. The method comprises the following steps: under the condition that a first distributed virtual interrupt controller DVIC node receives a virtual interrupt request, determining interrupt target routing information corresponding to virtual interrupt; the first DVIC node constructs a cross-chip hardware-level direct injection message according to the interrupt target routing information; and the first DVIC node sends a hardware-level direct injection message to the second DVIC node through inter-chip interconnection, and the hardware-level direct injection message directly writes a virtual interrupt into an IMSIC interrupt file of an incoming message signal interrupt controller through hardware logic by the second DVIC node. According to the invention, the cross-chip virtual interrupt delivery delay can be obviously reduced, and the system certainty is improved.

This invention discloses a DMA communication device and its operating method for a converged computing architecture. The DMA communication device includes a DMA transaction processing module and a protocol conversion module. When the network protocol processing component initiates a DMA read / write request, the DMA transaction processing module parses the relevant DMA read / write request, processes the DMA read / write request, receives DMA read request response data, and handles interrupt requests. The protocol conversion module converts read / write requests between the DMA interface and the AXI interface and maps response states. This invention aims to achieve efficient protocol conversion between the AXI and DMA interfaces, avoid DMA read request starvation caused by resource contention, ensure the consistency of DMA data access, improve the performance of accelerators in high-performance computing and artificial intelligence applications, reduce transmission latency, and increase data transmission bandwidth and energy efficiency.