310 results about "Interrupt request" patented technology

The invention relates to the field of energy-saving computing, and discloses a low-power-consumption control method and system of a controller, which are used for realizing prediction-sleep-wake-up-response full-link hardware in the controller. Time sequence state data of a controlled object is collected in real time, and a predictive sleep window value is dynamically generated by utilizing a predictive cooperative computing unit, so that intelligent scheduling of sleep and awakening is realized, and the power consumption of a controller is effectively reduced. Meanwhile, in combination with the technologies of threshold comparison, DMA data transmission optimization and the like, the data processing efficiency is improved, and invalid data transmission is reduced. And on the awakening mechanism, an asynchronous awakening circuit and an interrupt request mechanism are adopted to ensure that power supply is quickly recovered and control response is executed when an effective instruction is received, so that the real-time performance of the system is guaranteed. According to the invention, a prediction algorithm, hardware acceleration and an intelligent scheduling technology are fused, the performance of the controller is ensured, the power consumption is obviously reduced, and the endurance time of equipment is prolonged.

The invention relates to the technical field of computers, and discloses a heterogeneous acceleration system and method, computing equipment and a storage medium, and the system comprises a host end which is used for obtaining any acceleration task of the computing equipment, splitting the acceleration task into a plurality of sub-tasks, and unloading the plurality of sub-tasks to a heterogeneous acceleration card; the heterogeneous acceleration card is used for receiving and executing a plurality of sub-tasks, generating a corresponding interrupt sub-request when execution of any sub-task is completed, generating a target interrupt request under the condition that the total amount of the currently obtained interrupt sub-requests reaches a preset threshold value, and sending the target interrupt request to the host end; and the host end is used for receiving the target interrupt request and reading the execution result of the subtask from the heterogeneous accelerator card in response to the target interrupt request. The heterogeneous accelerator card is prevented from sending a large number of interrupt sub-requests to the host end in a short time, so that the host end is prevented from frequently responding to the interrupt request, and the overall performance of the computing device is improved.

The invention aims to provide a communication method of a multi-core system and the multi-core system, and relates to the technical field of computers. The method applied to the Mailbox hardware module in the multi-core system comprises the following steps: receiving an operation configuration instruction of a processor core to the Mailbox hardware module; under the condition that an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address according to a communication channel expected to be used so as to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that the communication channels of the mailbox source registers recording the source addresses are all used, and the destination addresses recorded by the mailbox target registers of the communication channels are all transmitted. Therefore, the communication concurrency and throughput of the multi-core system can be improved. And meanwhile, the communication reliability of the multi-core system can be improved.

Disclosed are a method and apparatus for optimizing server system interrupts, a device and a medium, which relate to the field of servers. The method is applied to a server system, and comprises: when a peripheral driver of a kernel space monitors an interrupt request signal sent by a hardware peripheral, reading a hardware event queue in the hardware peripheral, so as to acquire a target hardware event in the hardware event queue; then, converting the target hardware event into a target software event by using the peripheral driver, and writing the target software event into a preset global event queue; reading the target software event in the global event queue by means of a user space, and forwarding the target software event to a corresponding target service process by means of the user space, such that the target service process processes the target. In this way, by using hardware interrupt coalescing and software event coalescing techniques, this solution may not only reduce the interrupt processing overhead, but also reduce the processor utilization.

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

The invention discloses an interrupt control device and method, electronic equipment and a non-volatile computer readable storage medium. The interrupt control device comprises an interrupt detection module, an interrupt arbitration module and an interrupt output module, the interrupt detection module is configured to detect a plurality of interrupt requests respectively sent by a plurality of target interrupt sources; the interrupt arbitration module is coupled with the interrupt detection module and is configured to perform an interrupt arbitration operation on the plurality of interrupt requests so as to select a target interrupt request from the plurality of interrupt requests; the interrupt output module is coupled with the interrupt arbitration module and is configured to output interrupt information according to the target interrupt request. The interrupt control device can reduce the area of a chip and effectively improve the performance, the power consumption and the area of the chip.

The invention discloses an ARMv8-based virtual machine interrupt through routing method, which comprises the following steps that: a Hypervisor directly routes a physical interrupt to an EL1 through configuration, sets a top page table address of a vCPU (Virtual Central Processing Unit) and a Hypervisor control register at the same time, and sets a vcpudid flag bit for indicating whether the vCPU adopts a virtual interrupt injection mechanism or a physical interrupt through routing mechanism; and judging whether an interrupt through routing condition is met or not so as to determine whether an interrupt through routing mechanism or a virtual interrupt injection mechanism is adopted, periodically judging whether a switching condition is met or not when the interrupt through routing mechanism is adopted, and switching from the interrupt through routing mechanism to the virtual interrupt injection mechanism if the switching condition is met. The method is compatible with two interrupt controller specifications of GICv2 and GICv3, supports the virtual machine and the hypervisor to respectively and independently respond to respective corresponding interrupt requests, and meanwhile, the method has the capability of dynamically switching an interrupt routing mechanism during the system operation period, so that the flexibility of interrupt processing and the expandability of the system are improved.

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

The invention relates to a user mode interruption processing method and device, equipment and a program product. Through the interrupt information carried by the user mode interrupt request, the operating system can quickly and accurately determine the source and the processing path of the target user mode interrupt in numerous possible interrupt situations. Meanwhile, the context switching time in the interrupt processing process can be effectively shortened by obtaining the current process and the current stack frame thereof, matching the current process and the current stack frame thereof with the target process and determining a mechanism of the target stack frame in combination with the interrupt address information, so that the context switching time in the interrupt processing process can be effectively shortened when the interrupt occurs. The target stack frame can be quickly determined to provide an accurate execution environment recovery basis for subsequent switching between the kernel mode and the user mode and execution of the interrupt service program, and the interrupt processing speed can be increased by switching the kernel mode to the user mode to run the interrupt service program of the user mode. And the overall performance and resource utilization rate of the operating system are improved.

The invention discloses an automatic traversal test circuit, an automatic traversal test device, an interrupt request test method and an interrupt request test system, and the automatic traversal test circuit comprises a multiplexer which comprises N test pins, and the total number N of the test pins is the same as the number of to-be-tested interfaces of a to-be-tested chip; the chip to be tested and the multiplexer form multi-channel connection; the multiplexer further comprises at least one first control interface and a selection input end; the truth value state of the first control interface is changed under the action of the first control instruction, so that the selection input end is controlled to select a path corresponding to the target test pin to be conducted. According to the invention, the multichannel multiplexer analog switch is added in the test circuit to replace the function of manually plugging and switching pins. The multi-interface interrupt request automatic test of the chip to be tested can be realized.

An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

The invention belongs to the field of electronic equipment communication, and discloses an SPI bus active hang-up prevention method and device based on a clock line state, and the method comprises the steps: presetting a first level signal of an SPI clock line in an idle state, and presetting a hang-up prevention counting threshold; the SPI controller monitors a second level signal of the clock line in real time; when the condition that the second level signal is inconsistent with the first level signal continues, an internal counter is started for counting; when the count value of the counter reaches an anti-hanging counting threshold value, the SPI controller judges that the clock line is hung and sets an internal hanging state flag; if the SPI is enabled to hang the interrupt function through the software configuration, the SPI controller sends an interrupt request signal to the processor; and the processor responds to the interrupt request signal and executes a corresponding fault recovery operation. The state of the clock line is monitored in real time through the SPI controller and compared with the preset idle level, and the recognition process can be started at the moment that the clock line is pulled dead.

The invention provides an abnormal event processing method, electronic equipment and a storage medium, and relates to the technical field of communication. The electronic device detects a first interrupt request from a touch chip. In response to the first interrupt request, judging whether the touch chip has an interrupt abnormal event or not; and if the interruption abnormal event occurs in the touch chip, the electronic equipment sends first notification information to an upper system process, and shields an interruption request of the touch chip. The first notification information is used for notifying the system process not to indicate to start the interrupt response. By means of the mode, in the process that the interruption abnormal event happens to the touch control chip, the electronic device does not start the interruption response of the interruption request again, and the influence of the interruption abnormal event is reduced.

The invention relates to the technical field of computers, and discloses a method, device and equipment for hot plugging of PF equipment, a medium and a program product, and the method comprises the following steps: configuring at least one hot-pluggable PF equipment for a data processing unit; the PF equipment supports multiple equipment types, and the initial state is invisible to the host; in response to a first hot plug instruction for hot plug of the first device type, determining a first PF device which is invisible to the host at present; the identification information of the first PF equipment is configured to be first identification information corresponding to the first equipment type, and the state of the first PF equipment is updated to be visible to the host; sending a first interrupt request to the host; the first interrupt request is used for notifying the host to scan equipment. According to the method and the device, the PF equipment of the specified equipment type can be hot-plugged in the corresponding PF slot position according to the hot-plugging instruction of the user, and is presented to the host for use, so that flexible configuration of different equipment types can be realized, and various requirements of the user are met.

An interrupt processing method includes when a first interrupt request is triggered, determining a target CPU that responds to the first interrupt request; determining a first target interrupt running entity in the target CPU; scheduling a target thread from a user mode to a kernel mode; replacing a running entity in the target thread with the first target interrupt running entity; and scheduling the target thread including the first target interrupt running entity to the user mode, and running the first target interrupt running entity by using the target CPU.

The invention discloses a network flow processing method, device and equipment and a storage medium, and relates to the technical field of system resource management, and the method comprises the steps: monitoring a current network load of a computer system, and determining a to-be-isolated processor core from the computer system when the current network load is judged to meet a preset high load condition; binding the network data packet buffer area and the network protocol stack data structure to a high-speed cache of the processor core to be isolated, and distributing a target buffer pool for the processor core to be isolated in a memory area of a computer system to obtain a target processor core; the network data packet buffer area is used for storing a data packet related to an interrupt request in the current network flow of the computer system, and the network protocol stack data structure is a data structure related to the data packet; and respectively processing the interrupt request and other network flows through the target processor core and other processor cores. Therefore, high-intensity load change can be coped with in a mode of isolating the processor cores.

The embodiment of the invention provides an interrupt source processing method and device, a storage medium and electronic device.The method comprises the steps that in the process that an interrupt processing service responds to a target interrupt request to execute target interrupt processing, interrupt processing information is obtained, and the target interrupt request is a request transmitted to the interrupt processing service in advance; under the condition that it is determined that target interrupt processing executed by the interrupt processing service is abnormal from the interrupt processing information, a target interrupt source is determined, and the target interrupt source is an event or a signal which is sent by the simulation solid state disk and can trigger an interrupt request; a disable operation is performed on the target interrupt source to instruct the interrupt processing service to stop the target interrupt processing. Through the method and the device, the problem of relatively low test efficiency of interrupt processing in related technologies is solved, and the effects of improving the test efficiency and ensuring the test safety and the system stability are achieved.

The invention discloses a resource binding method, electronic equipment and a storage medium. The method comprises the steps that in response to an interrupt request to be processed of a target instance, a target binding strategy is determined, and the target binding strategy is used for determining that a network card interface corresponding to the interrupt request and processor resources to be bound with the interrupt request are located in the same resource node of a processor architecture; and carrying out resource binding processing on the interrupt request according to the target binding strategy to obtain a binding processing result. The technical problem of poor network performance caused by sequential binding of processor resources only according to the interrupt number in the prior art is solved.

The invention discloses an SSE streaming output interruption control method and device, a server and a medium. The present invention relates to the technical field of data transmission, and the method comprises: obtaining a data transmission interruption request sent by a client, the data transmission interruption request comprising a unique identifier of the client; querying a stored corresponding data transmission control field according to the unique identifier of the client, and updating the data transmission control field, wherein the data transmission control field is used for identifying whether streaming output of current data is interrupted or not; and judging whether the streaming output of the current data is interrupted or not according to the query result of the data transmission control field. According to the method and the device, the streaming output of the server can be actively interrupted, and network disconnection abnormity cannot be generated in the whole process of actively interrupting the streaming output, so that the performance of the server cannot be influenced.

The present invention discloses a data transmission system, method, device and storage medium, and relates to the field of chip technology. The system includes: a protocol conversion module, which is used to perform communication protocol conversion processing on access requests issued by an access source end, and send it to an interconnection arbitration module; an interruption crossing module, which is used to summarize and process interruption requests issued by an interruption source end, and send it to an interconnection arbitration module; an interconnection arbitration module, which is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to a communication interface module; a communication interface module, which is used to send the target request to the opposite end chip. The technical solution of the embodiment of the present invention not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

The invention relates to the technical field of chips, and provides an interrupt module verification method and device, a medium and a program product, the method comprises the following steps: when it is monitored that an interrupt module generates an external observable behavior, comparing monitored behavior information with a reference value of the external observable behavior, and verifying the correctness of the external observable behavior; performing state calculation on the interrupt request input to the interrupt module, and determining an internal processing state of the interrupt request; an internal register state of the interrupt module is verified based on an internal processing state of the interrupt request. According to the invention, through a mode of combining black box verification of external observable behaviors with white box verification based on an internal processing state, comprehensive, deep and efficient function verification of a complex interrupt module is realized.

The invention discloses a task scheduling method and device for a target operating system and a storage medium, and the method comprises the steps: searching a first interrupt task in a ready task queue if the target operating system receives a clock interrupt request; the first interrupt task is a periodic scheduling task obtained based on the clock interrupt request, and the priority of the first interrupt task is higher than that of the first remaining task; scheduling the first interrupt task to start execution; in the execution process of the first interrupt task, if the priority of the second interrupt task is higher than that of the first interrupt task, the state of the first interrupt task is updated to be a suspended state; the second interrupt task is a scheduling task acquired in real time; updating the state of the second interrupt task into a running state, and scheduling the second interrupt task to start execution; and if the execution of the second interrupt task is completed, obtaining an executable task in the ready task queue. The real-time performance, safety and flexibility of the target operating system are improved.

A transmission device according to an aspect of the present disclosure communicates with a reception device via a control data bus. The transmission device includes a generation unit that generates an interrupt request, and a transmission section that transmits data to the reception device via the control data bus. The interrupt request includes at least an identification bit to identify a type of transmission data, an information bit for the transmission data, and the transmission data.

The invention discloses an interrupt controller, a chip and electronic equipment. The interrupt controller comprises at least one interrupt domain module and an output module, each interrupt domain module is configured to receive a line interrupt request, obtain a target line interrupt request matched with the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request; and the output module is configured to receive the message interruption request sent by the at least one interruption domain module and control the output of the message interruption request. The interrupt controller processes a line interrupt request in an interrupt system based on message interrupt.

The invention discloses a network performance optimization method and device, and is applied to a server system of a multi-non-uniform memory access node architecture, and the network performance optimization method comprises the steps: obtaining non-uniform memory access node information loaded by an operating system kernel and non-uniform memory access node information where a network card is located; if it is judged that the non-uniform memory access node loaded by the operating system kernel is the same as the non-uniform memory access node where the network card is located, checking the interrupt request binding condition of the network card; according to the interrupt request binding condition of the network card, if the interrupt request of the network card is not bound to the CPU core of the non-uniform memory access node where the network card is located, binding the interrupt request of the network card to the CPU core of the non-uniform memory access node where the network card is located.

The present application discloses a monitoring system, method, device, medium and equipment for the state of a drop-out fuse. The system includes a gravity acceleration sensor, a processing unit and a communication terminal; at least two gravity acceleration sensors are configured to collect the acceleration change amount and the gravity component of the drop-out fuse, and the acceleration change amount and the gravity component are collected in sequence; when any acceleration change amount exceeds a preset threshold, an interrupt request is generated; the processing unit is configured to receive the interrupt request, obtain the gravity components of all the gravity acceleration sensors and perform consistency verification; if the gravity components of all the gravity acceleration sensors are consistent, the opening and closing state information of the drop-out fuse is sent to the communication terminal; if the gravity components of all the gravity acceleration sensors are inconsistent, all the gravity acceleration sensors are restarted. The embodiments of the present application can not only capture the fuse action in time, but also avoid resource waste and misjudgment.

The invention discloses an interrupt request processing method, device and equipment and a storage medium, and relates to the technical field of computer system optimizing.The method comprises the steps that according to monitored real-time interrupt loads of a plurality of processor cores of a server, a low-load core and a high-load core are divided; generating a migration decision result representing that the target interrupt request corresponding to the high-load core is migrated to the target processor core; the target processor core is a processor core, corresponding to the same NUMA domain as the high-load core, in the low-load cores; updating the affinity file corresponding to the target processor core by using the migration decision result, and adjusting the target mapping table in combination with the updated affinity file, so as to execute the target interrupt request based on the adjusted mapping table; the affinity file represents a binding relationship between the interrupt request and the processor core, and the target mapping table represents a data transmission relationship between a processing queue of a network card related to the interrupt request and the processor core. Therefore, the interrupt request can be dynamically migrated, and the problem of interrupt overload is relieved.

The invention discloses an integrated circuit and a method and system for processing an interrupt request, and belongs to the technical field of computers. An integrated circuit includes one or more processor clusters, and coupled interrupt circuitry. Wherein the interrupt circuit is used for receiving an interrupt request through a first interrupt node in the multiple levels of interrupt nodes, and querying the first memory according to an interrupt identifier of the interrupt request to obtain a first identifier corresponding to the interrupt identifier. And sending an interrupt request to the target processor cluster through the first interrupt node and the second interrupt node under the condition that the first identifier indicates the second interrupt node in the multiple levels of interrupt nodes, or sending the interrupt request to the target processor cluster through the first interrupt node under the condition that the first identifier indicates the target processor cluster, and processing the interrupt request by the target processor cluster. The first interrupt node quickly and flexibly routes the interrupt request according to the first memory, so that the processing efficiency of the interrupt request is improved.

The present disclosure relates to a method and system for managing a meeting session. In accordance with one example, there is provided a method of managing a meeting session on a server that manages the meeting session, the meeting session comprising one or more participant devices and a presenter device. The method comprises receiving one or more break request messages from the participant devices, and sending a break message to the participant devices, the break message causing a break notification to be displayed on a display of the participant devices.

The invention relates to the technical field of equipment control, and discloses a control method and system for ultrasonic cleaning equipment, and the method comprises the steps: obtaining parameters in an interruption controller and an MCU of the ultrasonic cleaning equipment, and determining an instruction upper limit value N; dividing interrupt instruction priorities, constructing an interrupt instruction matrix, calculating an interrupt risk value, and generating a risk analysis signal according to the risk value; a high-risk data set is constructed, to-be-sorted instructions with the same priority are sorted through a TOPSIS method, and an instruction distribution data set is constructed; based on the instruction distribution data set, the CPU occupancy rate, the interrupt upper limit value and the average processing time are combined to calculate an interrupt evaluation value Gz and output the interrupt evaluation value Gz to the MCU, the interrupt evaluation value Gz is used for measuring the load and risk degree of the system for processing the interrupt request, interrupt instruction distribution of the ultrasonic cleaning equipment can be optimized, and the system stability and reliability are improved.