23 results about "Interrupt request" patented technology

The application relates to the technical field of interrupt control, and discloses an interrupt control method, an interrupt controller, computer equipment and a storage medium, the method is applied to an interrupt controller, the method comprises the following steps: receiving a plurality of interrupt requests; determining the current priority of each interrupt request in the plurality of interrupt requests according to the N-time historical processing time length of each interrupt request in the plurality of interrupt requests, wherein N is a positive integer; and sending the plurality of interrupt requests to a processor according to the sequence of the current priorities of the plurality of interrupt requests. The application can flexibly adjust the priorities of the plurality of interrupt requests according to actual application scenes, and improves the performance of a system.

A touch circuit includes a micro control circuit and a readout integrated circuit configured to communicate with the micro control circuit though a selection signal line, a clock signal line, a master output slave input (MOSI) signal line, and a master input slate output (MISO) signal line. In a first period, the readout integrated circuit generates a first interrupt request signal representing completion of touch sensing, and transfers the first interrupt request signal to the micro control circuit through the MISO signal line. In a second period which differs from the first period, the readout integrated circuit generates a second interrupt request signal, representing a kind of error and whether an operation state thereof is normal, and transfers the second interrupt request signal to the micro control circuit through the MOSI signal line.

The application discloses a method for transmitting external interruption of a vehicle display screen end by using a DP extension protocol, and comprises the following steps: an Aux GPIO suspension identifier is predefined as a special identifier bit in an AUX register for judging external GPIO interruption, and a receiving end feeds back external interruption to a source end; when the remote device gives an interruption, the receiving end identifies the interruption request through a local GPIO, writes an interruption effective identifier into a DPCD SINK SPECIFIC IRQ address through a DP module, sets the Aux GPIO suspension identifier to 1, pulls down an HPD pin, and notifies the source end; the source end reads corresponding and judges whether there is additional interruption after detecting the pull-down; if yes, the source end reads an interruption judgment identifier bit to judge whether it is external GPIO interruption; and the source end calls an external GPIO interruption processing function after clearing the identifier. The application can complete interruption notification and data interaction without a serializer, a deserializer, and without relying on an external interruption signal.

The embodiment of the invention provides a calling method and device for an interrupt communication system between para-virtualization processors, electronic equipment and a readable storage medium. The method comprises the steps that interrupt characteristics between the para-virtualization processors are configured for virtual processors; if the virtual processor starts the interrupt characteristic between the para-virtualization processors, setting an interrupt call function for the virtual processor so as to call the interrupt call function when an interrupt request is sent; and in response to calling of the interrupt calling function, directly updating the interrupt descriptor corresponding to the target virtual processor so as to enable the target virtual processor to process the interrupt request. According to the embodiment of the invention, by setting the interrupt calling function, when the interrupt request is subsequently transmitted, the interrupt descriptor of the target virtual processor is directly updated so as to process the interrupt request without intervention of a virtual machine monitor, so that the number of times that the virtual machine returns to the host machine state from the client machine state is reduced, and the performance of the virtual machine is improved.

This invention discloses a design method for a RISC-V AIA interrupt-configurable multi-privilege-level IMSIC controller, comprising: setting a programmable configuration register MS_CUT_CFG in the IMSIC to dynamically allocate interrupt file resources for machine mode (M-mode) and supervisor mode (S-mode) at runtime; controlling the allocation ratio of the actual physical storage space of interrupt files in machine mode (M-mode) and supervisor mode (S-mode) through the configuration register MS_CUT_CFG to achieve dynamic reuse of interrupt file resources; physically sharing the same hardware register array for the interrupt enable register group (IE) and interrupt suspend register group (IP) of machine mode (M-mode) and supervisor mode (S-mode); and mapping suspended but executable interrupt requests to the corresponding privilege level and submitting them to the processor core through an interrupt arbitration circuit based on the current value of the configuration register. This invention overcomes the limitations of the static resource configuration strategy for IMSIC interrupt files, significantly enhancing the flexibility and dynamic scenario adaptability of RISC-V AIA interrupt applications.

Embodiments of the present application provide a kind of interrupt source switching method, device, electronic equipment and computer readable storage medium, when operating system kernel starts, parse interrupt command line parameter, obtain analysis result, the value of the interrupt command line parameter includes the identification of at least one interrupt source, the analysis result is the identification of target interrupt source in at least one the identification of the interrupt source;According to the identification of target interrupt source in the analysis result, the initialization of target interrupt controller is executed, and the target interrupt controller is the interrupt controller corresponding to the identification of target interrupt source specified by user;In response to initiating inter-core interrupt request operation, switch to the target interrupt controller that has completed initialization to send corresponding inter-core interrupt request signal, can be implemented under different platform architecture and different firmware version to the flexible configuration of multiple interrupt sources, to meet IPI interrupt demand, to improve system performance and enhance scalability.

An interrupt request balancing method and apparatus, and a computing device are provided. The computing device includes a plurality of processors, to obtain operating statuses of the plurality of processors. The computing device may set a processor that is in a non-idle state, whose operating frequency is within a preset frequency range, or whose load rate is less than a specified load rate in the plurality of processors to be used to process an IRQ other than a designated IRQ, and set a processor in another state to be used to process the designated IRQ.

A virtual processor is provided that can be mapped to a plurality of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with additional interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines whether to route the interrupt request to one of the subset of physical processors or to one of the additional interrupt distributors based on cached virtual processor mapping information. When a rejection response is received in response to the interrupt request being routed to one of the additional interrupt distributors, an update to the cached virtual processor mapping information is requested based on shared virtual processor mapping information and the re-sent interrupt request is sent to another interrupt distributor determined based on the shared virtual processor mapping information.

The application discloses a kind of RISCV system memory debugging method and system, its method includes: the interrupt request function of RISCV kernel is configured, enter debugging action and exit debugging action do not trigger the exception mechanism of RISCV processor;With host computer connection RISCV system, enter debugging state;The single-cycle valid signal triggered by host computer execution enter debugging action is converted into long-time valid signal;When long-time valid signal is valid, judge whether RISCV kernel has read-write, if yes, determine that the read-write signal of debugging module is invalid, set the state flag bit of interactive register, notify host computer system busy;If no, determine that the read-write signal of debugging module is valid, debugging module executes read-write to memory;Debugging module completes memory read-write and receives host computer exit debugging signal after exit debugging action, and make long-time valid signal invalid.The application utilizes the gap that RISCV kernel does not read nor write, realizes the read-write of debugging module to memory, realizes no interrupt memory debugging.

The application provides a FIFO interrupt management-based method, which comprises the following steps: obtaining a plurality of interrupt requests sent internally or externally by an FPGA, wherein the interrupt requests comprise priority information and port number information; determining a FIFO corresponding to the priority information and a synchronization module corresponding to the port number information; each of the interrupt requests is configured with an independent synchronization module; the synchronization modules of the same priority FIFO adopt the same interrupt synchronization clock; the interrupt requests are synchronized through the interrupt synchronization clock; the interrupt requests are written into the FIFO of the corresponding priority; and the interrupt vectors corresponding to the interrupt requests stored in each FIFO are read out by the interrupt enable module according to the priority. The application can realize the management function of multiple priorities and multiple interrupts internally or externally by the FPGA, and overcome the problems of interrupt loss and interrupt coverage of common integrated circuits.

This invention relates to the field of artificial intelligence chip technology, providing an interrupt control method, an artificial intelligence chip, a system, a device, a medium, and a program product. The method includes: receiving interrupt request information initiated by a target user; performing a first-stage verification on the interrupt request information; if the first-stage verification passes, performing a second-stage verification on the interrupt request information; and distributing the interrupt request information or corresponding generated abnormal interrupt information to the corresponding interrupt storage area of ​​the host based on the combined verification results of the first and second stages. This invention, by performing multi-level verification of the legality and security attributes of each user-initiated interrupt request at the source end, and combining the verification results with physical isolation-level distribution, not only achieves bidirectional defense from the source end to the underlying target storage end, but also allows for independent checking of the security of each user-initiated interrupt, thereby maximizing the data security and operational compliance of the entire chip system.

This invention relates to the field of communication protocol optimization technology, specifically to a communication method and system for LED devices based on protocol stack optimization, comprising the following steps: a physical layer data frame acquisition module, a protocol path intelligent decision-making module, a cross-layer instruction direct mapping module, and a dynamic stack parameter optimization module. In this invention, the physical layer data frame acquisition module acquires the raw signal bitstream and converts it into physical layer data frames. The protocol path intelligent decision-making module determines and triggers zero-copy processing logic based on the protocol type identifier, blocking network interruption requests. The cross-layer instruction direct mapping module directly writes the payload data segment to the target video memory address through a memory mapping mechanism, significantly reducing the context switching latency and CPU load caused by data unpacking. Simultaneously, the dynamic stack parameter optimization module adjusts the sliding window size parameter according to the communication quality evaluation matrix, effectively solving the timing jitter problem existing in traditional protocol stacks when processing high-frequency LED control instructions.

This invention discloses a method, apparatus, device, and medium for optimizing interrupt handling in a virtualization system, relating to the field of virtualization technology. The method includes configuring the Virtual Machine Monitor (HMGM) to configure MSI interrupt routing; the Virtual Machine Provider (VE) receives requests from the Virtual Machine (VM) or the Virtual Machine Interrupt Service (SPI) and, based on the current state, initiates an MSI interrupt request to the HMGM; the Message Interrupt Handling Component (ITS) in the HMGM receives the MSI interrupt request and converts it into an LPI interrupt, which is then sent to the VM or the HMGM. The HMGM configuration of the HMGM specifies the MSI and LPI interrupts sent to the VM, and specifies the MSI interrupts sent to the HMGM. This application enables communication between virtual machines and between a virtual machine and the host without additional computing power loss, effectively optimizing interrupt handling in automotive processors.

The application provides a network state detection method and device, which is applied to a device containing a system on chip (SOC), and an interrupt input pin of the SOC is electrically connected with an interrupt request pin of a physical layer chip. When the physical layer chip is initialized, a change of a physical layer link state is mapped to the interrupt request pin, an interrupt processing flow is executed in response to an interrupt trigger signal of the interrupt request pin, a current physical layer link state is acquired, and the current physical layer link state is transmitted to a preset application program based on an inter-process communication mechanism, so that the preset application program reports the current physical layer connection state information to an external controller. Through the introduction of a hardware interrupt trigger mechanism and efficient communication between a kernel and an application layer, real-time detection and rapid reporting of the network state are realized, the network state detection time is greatly shortened, system resource consumption is reduced, and the real-time detection and reporting capability of the network state can be significantly improved.

The application relates to the computer technical field and provides a virtual interrupt mapping method and device. The method comprises the following steps: receiving and extracting a target physical interrupt source identifier according to a physical interrupt request of an external device; performing hardware mapping retrieval according to the target physical interrupt source identifier to obtain a target virtual machine identifier, a target virtual processor identifier and a target virtual interrupt number corresponding to the target virtual processor identifier; performing address offset calculation according to the target virtual machine identifier and the target virtual processor identifier to obtain a physical address of a target virtual machine interrupt file; and writing the target virtual interrupt number into the target virtual machine interrupt file according to the physical address of the target virtual machine interrupt file. Based on the application scheme, the fast mapping of a physical interrupt to a virtual interrupt is realized without the intervention of a virtualization management program, so that the interrupt processing time delay and system overhead in the virtualization environment are effectively reduced.

This invention describes an interrupt handling method for a sensing device and its integrated circuit, wherein the integrated circuit includes a processor, a general-purpose interrupt controller, and a bus master. The bus controller includes a bus control circuit and a polling circuit, wherein the polling circuit is used to detect whether an interrupt signal of the sensing device has been asserted. In response to the polling circuit detecting that the interrupt signal has been asserted, the bus control circuit sequentially retrieves each of a plurality of tasks stored in a task queue in memory and executes one or more data transmission operations corresponding to each task to obtain sensor data from the one or more sensors of the sensing device. In response to a task completion signal generated by the bus control circuit, the general-purpose interrupt controller generates an interrupt request signal to be sent to the processor.

This application discloses a server fault data acquisition system, method, and electronic device, relating to the field of server technology. Through the collaborative design of a target processor and a baseboard management controller group, it solves the problem of incomplete server fault data acquisition in related technologies. Specifically, the target processor, based on an interrupt request sent by the fault detection circuit, determines the target baseboard management controller from among the various baseboard management controllers, and sends a control command to the switching circuit so that the switching circuit controls the target baseboard management controller to have access to the storage unit. The target processor is also used to send fault data acquisition commands to the target baseboard management controller to control the target baseboard management controller to acquire fault data from the server motherboard and to control the target baseboard management controller to store the fault data in the storage unit.

The application discloses a kind of involving computer technical field processor and interruption control method, device.The device includes: hardware interruption control circuit when receiving high priority new hardware interruption request, determine the hardware interruption processing program being executed and the estimated completion time of new hardware interruption processing program, according to task time limit demand generation control signal.Software and hardware interruption association processing circuit is predicted to hardware interruption request in future preset time period, in the software interruption request generated, select target software interruption request corresponding to hardware interruption prediction information same processing task and by same processing core execution, and send to corresponding processing core.Resource regulation circuit adjusts the hardware operating parameter of processor according to the control signal forwarded by processing core cluster.The application can solve the problem of large task processing delay in related technology, can effectively improve the real-time processing performance of processor, meet the user demand of high real-time application scenario.

A computer device is disclosed. In a virtualization I / O procedure, a redirection apparatus in a processor is used to implement privilege level switching in a synchronization processing procedure, to directly switch from a virtualization privilege level of a VM to a user mode of a host, and perform corresponding exception processing. In an asynchronous processing procedure, an interrupt request may be asynchronously transferred by using a virtual event notification apparatus and an interrupt controller in the processor without passing through a kernel mode of the host. In both of a synchronous processing procedure and the asynchronous processing procedure of the device, overheads generated during switching are reduced, and performance of the computer device is improved.

The application discloses a storage body self-test system and method with extensible programming, which comprises the following steps: a CPU is connected to a configurable storage body test controller through a CPU configuration interface and a configuration bus for bidirectional transmission of configuration instructions and parameters; the configurable storage body test controller is connected to each group of SRAM and ROM through a storage body access bus; test results of the measured storage body are written into a state register through an internal bus, and the state register is connected to a CPU data reading port for output; a fault signal output end of the configurable storage body test controller is connected to an interrupt module, and the interrupt module sends an interrupt request to the CPU; and an ATE test multiplexing interface reserved in the configurable storage body test controller is directly connected to MBIST logic of chip factory test for multiplexing. The method is implemented based on the system. The application has the advantages of simple principle, lower cost, better responsiveness, stronger compatibility, wider application range and the like.