232 results about "Interrupt request" patented technology

The invention relates to the field of energy-saving computing, and discloses a low-power-consumption control method and system of a controller, which are used for realizing prediction-sleep-wake-up-response full-link hardware in the controller. Time sequence state data of a controlled object is collected in real time, and a predictive sleep window value is dynamically generated by utilizing a predictive cooperative computing unit, so that intelligent scheduling of sleep and awakening is realized, and the power consumption of a controller is effectively reduced. Meanwhile, in combination with the technologies of threshold comparison, DMA data transmission optimization and the like, the data processing efficiency is improved, and invalid data transmission is reduced. And on the awakening mechanism, an asynchronous awakening circuit and an interrupt request mechanism are adopted to ensure that power supply is quickly recovered and control response is executed when an effective instruction is received, so that the real-time performance of the system is guaranteed. According to the invention, a prediction algorithm, hardware acceleration and an intelligent scheduling technology are fused, the performance of the controller is ensured, the power consumption is obviously reduced, and the endurance time of equipment is prolonged.

The invention aims to provide a communication method of a multi-core system and the multi-core system, and relates to the technical field of computers. The method applied to the Mailbox hardware module in the multi-core system comprises the following steps: receiving an operation configuration instruction of a processor core to the Mailbox hardware module; under the condition that an interrupt trigger signal of the processor core corresponding to the source address is received, sending an interrupt request signal to the processor core corresponding to the destination address according to a communication channel expected to be used so as to transmit the data to be sent until a first preset condition is met, and sending a source interrupt signal to the processor core corresponding to the source address; the first preset condition is that the communication channels of the mailbox source registers recording the source addresses are all used, and the destination addresses recorded by the mailbox target registers of the communication channels are all transmitted. Therefore, the communication concurrency and throughput of the multi-core system can be improved. And meanwhile, the communication reliability of the multi-core system can be improved.

The invention discloses a direct memory access (DMA) communication device for a computing network convergence computing architecture and a working method of the DMA communication device. The DMA communication device comprises a DMA transaction processing module and a protocol conversion module; the DMA transaction processing module is used for analyzing related DMA read-write requests, realizing processing of the DMA read-write requests and receiving of response data of the DMA read requests and completing processing of interrupt requests at the same time, and the protocol conversion module is used for completing conversion of read-write requests between a DMA interface and an AXI interface and mapping of response states. The invention aims to realize efficient protocol conversion between AXI and DMA interfaces, avoid the problem of DMA read request starvation caused by resource competition and ensure the consistency of DMA data access so as to improve the performance of an accelerator in high-performance calculation and artificial intelligence application, reduce transmission delay and improve data transmission bandwidth and energy efficiency.

The invention discloses an ARMv8-based virtual machine interrupt through routing method, which comprises the following steps that: a Hypervisor directly routes a physical interrupt to an EL1 through configuration, sets a top page table address of a vCPU (Virtual Central Processing Unit) and a Hypervisor control register at the same time, and sets a vcpudid flag bit for indicating whether the vCPU adopts a virtual interrupt injection mechanism or a physical interrupt through routing mechanism; and judging whether an interrupt through routing condition is met or not so as to determine whether an interrupt through routing mechanism or a virtual interrupt injection mechanism is adopted, periodically judging whether a switching condition is met or not when the interrupt through routing mechanism is adopted, and switching from the interrupt through routing mechanism to the virtual interrupt injection mechanism if the switching condition is met. The method is compatible with two interrupt controller specifications of GICv2 and GICv3, supports the virtual machine and the hypervisor to respectively and independently respond to respective corresponding interrupt requests, and meanwhile, the method has the capability of dynamically switching an interrupt routing mechanism during the system operation period, so that the flexibility of interrupt processing and the expandability of the system are improved.

The invention provides a data transmission method and system, a chip, electronic equipment and a storage medium, the method is applied to a processing module of the data transmission system, and the method comprises the following steps: under the condition that an interrupt request is received, obtaining a data transmission instruction, and performing data analysis on the data transmission instruction to obtain an interrupt request; obtaining a data operation type, an interface type and a data transmission parameter; acquiring register configuration data corresponding to the interface type, and performing configuration corresponding to the register configuration data and the data transmission parameters on the configuration register through the internal bus; under the condition that configuration of the configuration register is completed, data to be transmitted are obtained through a transmission interface corresponding to the register configuration data, and data transmission corresponding to the data operation type and the data transmission parameter is conducted on the data to be transmitted based on the control register and the encryption and decryption unit. The transmission interface is one of a bus master interface, a bus slave interface and a private interface.

The invention relates to a user mode interruption processing method and device, equipment and a program product. Through the interrupt information carried by the user mode interrupt request, the operating system can quickly and accurately determine the source and the processing path of the target user mode interrupt in numerous possible interrupt situations. Meanwhile, the context switching time in the interrupt processing process can be effectively shortened by obtaining the current process and the current stack frame thereof, matching the current process and the current stack frame thereof with the target process and determining a mechanism of the target stack frame in combination with the interrupt address information, so that the context switching time in the interrupt processing process can be effectively shortened when the interrupt occurs. The target stack frame can be quickly determined to provide an accurate execution environment recovery basis for subsequent switching between the kernel mode and the user mode and execution of the interrupt service program, and the interrupt processing speed can be increased by switching the kernel mode to the user mode to run the interrupt service program of the user mode. And the overall performance and resource utilization rate of the operating system are improved.

An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

The invention belongs to the field of electronic equipment communication, and discloses an SPI bus active hang-up prevention method and device based on a clock line state, and the method comprises the steps: presetting a first level signal of an SPI clock line in an idle state, and presetting a hang-up prevention counting threshold; the SPI controller monitors a second level signal of the clock line in real time; when the condition that the second level signal is inconsistent with the first level signal continues, an internal counter is started for counting; when the count value of the counter reaches an anti-hanging counting threshold value, the SPI controller judges that the clock line is hung and sets an internal hanging state flag; if the SPI is enabled to hang the interrupt function through the software configuration, the SPI controller sends an interrupt request signal to the processor; and the processor responds to the interrupt request signal and executes a corresponding fault recovery operation. The state of the clock line is monitored in real time through the SPI controller and compared with the preset idle level, and the recognition process can be started at the moment that the clock line is pulled dead.

The invention relates to the technical field of computers, and discloses a method, device and equipment for hot plugging of PF equipment, a medium and a program product, and the method comprises the following steps: configuring at least one hot-pluggable PF equipment for a data processing unit; the PF equipment supports multiple equipment types, and the initial state is invisible to the host; in response to a first hot plug instruction for hot plug of the first device type, determining a first PF device which is invisible to the host at present; the identification information of the first PF equipment is configured to be first identification information corresponding to the first equipment type, and the state of the first PF equipment is updated to be visible to the host; sending a first interrupt request to the host; the first interrupt request is used for notifying the host to scan equipment. According to the method and the device, the PF equipment of the specified equipment type can be hot-plugged in the corresponding PF slot position according to the hot-plugging instruction of the user, and is presented to the host for use, so that flexible configuration of different equipment types can be realized, and various requirements of the user are met.

An interrupt processing method includes when a first interrupt request is triggered, determining a target CPU that responds to the first interrupt request; determining a first target interrupt running entity in the target CPU; scheduling a target thread from a user mode to a kernel mode; replacing a running entity in the target thread with the first target interrupt running entity; and scheduling the target thread including the first target interrupt running entity to the user mode, and running the first target interrupt running entity by using the target CPU.

The invention discloses a network flow processing method, device and equipment and a storage medium, and relates to the technical field of system resource management, and the method comprises the steps: monitoring a current network load of a computer system, and determining a to-be-isolated processor core from the computer system when the current network load is judged to meet a preset high load condition; binding the network data packet buffer area and the network protocol stack data structure to a high-speed cache of the processor core to be isolated, and distributing a target buffer pool for the processor core to be isolated in a memory area of a computer system to obtain a target processor core; the network data packet buffer area is used for storing a data packet related to an interrupt request in the current network flow of the computer system, and the network protocol stack data structure is a data structure related to the data packet; and respectively processing the interrupt request and other network flows through the target processor core and other processor cores. Therefore, high-intensity load change can be coped with in a mode of isolating the processor cores.

The invention discloses a resource binding method, electronic equipment and a storage medium. The method comprises the steps that in response to an interrupt request to be processed of a target instance, a target binding strategy is determined, and the target binding strategy is used for determining that a network card interface corresponding to the interrupt request and processor resources to be bound with the interrupt request are located in the same resource node of a processor architecture; and carrying out resource binding processing on the interrupt request according to the target binding strategy to obtain a binding processing result. The technical problem of poor network performance caused by sequential binding of processor resources only according to the interrupt number in the prior art is solved.

The present invention discloses a data transmission system, method, device and storage medium, and relates to the field of chip technology. The system includes: a protocol conversion module, which is used to perform communication protocol conversion processing on access requests issued by an access source end, and send it to an interconnection arbitration module; an interruption crossing module, which is used to summarize and process interruption requests issued by an interruption source end, and send it to an interconnection arbitration module; an interconnection arbitration module, which is used to arbitrate each request obtained according to the arbitration priority, and send the arbitrated target request to a communication interface module; a communication interface module, which is used to send the target request to the opposite end chip. The technical solution of the embodiment of the present invention not only reduces the hardware cost of the data transmission system in the chip, meets the high-bandwidth data transmission requirements of the chip interconnection, but also realizes the orderly scheduling of different types of function requests, improves the data transmission efficiency, and avoids the transmission delay in the data transmission process.

The invention relates to the technical field of chips, and provides an interrupt module verification method and device, a medium and a program product, the method comprises the following steps: when it is monitored that an interrupt module generates an external observable behavior, comparing monitored behavior information with a reference value of the external observable behavior, and verifying the correctness of the external observable behavior; performing state calculation on the interrupt request input to the interrupt module, and determining an internal processing state of the interrupt request; an internal register state of the interrupt module is verified based on an internal processing state of the interrupt request. According to the invention, through a mode of combining black box verification of external observable behaviors with white box verification based on an internal processing state, comprehensive, deep and efficient function verification of a complex interrupt module is realized.

The invention discloses an interrupt controller, a chip and electronic equipment. The interrupt controller comprises at least one interrupt domain module and an output module, each interrupt domain module is configured to receive a line interrupt request, obtain a target line interrupt request matched with the current interrupt domain module from the received line interrupt request, and generate a corresponding message interrupt request according to the target line interrupt request; and the output module is configured to receive the message interruption request sent by the at least one interruption domain module and control the output of the message interruption request. The interrupt controller processes a line interrupt request in an interrupt system based on message interrupt.

The invention discloses a network performance optimization method and device, and is applied to a server system of a multi-non-uniform memory access node architecture, and the network performance optimization method comprises the steps: obtaining non-uniform memory access node information loaded by an operating system kernel and non-uniform memory access node information where a network card is located; if it is judged that the non-uniform memory access node loaded by the operating system kernel is the same as the non-uniform memory access node where the network card is located, checking the interrupt request binding condition of the network card; according to the interrupt request binding condition of the network card, if the interrupt request of the network card is not bound to the CPU core of the non-uniform memory access node where the network card is located, binding the interrupt request of the network card to the CPU core of the non-uniform memory access node where the network card is located.

The present application discloses a monitoring system, method, device, medium and equipment for the state of a drop-out fuse. The system includes a gravity acceleration sensor, a processing unit and a communication terminal; at least two gravity acceleration sensors are configured to collect the acceleration change amount and the gravity component of the drop-out fuse, and the acceleration change amount and the gravity component are collected in sequence; when any acceleration change amount exceeds a preset threshold, an interrupt request is generated; the processing unit is configured to receive the interrupt request, obtain the gravity components of all the gravity acceleration sensors and perform consistency verification; if the gravity components of all the gravity acceleration sensors are consistent, the opening and closing state information of the drop-out fuse is sent to the communication terminal; if the gravity components of all the gravity acceleration sensors are inconsistent, all the gravity acceleration sensors are restarted. The embodiments of the present application can not only capture the fuse action in time, but also avoid resource waste and misjudgment.

The invention discloses an interrupt request processing method, device and equipment and a storage medium, and relates to the technical field of computer system optimizing.The method comprises the steps that according to monitored real-time interrupt loads of a plurality of processor cores of a server, a low-load core and a high-load core are divided; generating a migration decision result representing that the target interrupt request corresponding to the high-load core is migrated to the target processor core; the target processor core is a processor core, corresponding to the same NUMA domain as the high-load core, in the low-load cores; updating the affinity file corresponding to the target processor core by using the migration decision result, and adjusting the target mapping table in combination with the updated affinity file, so as to execute the target interrupt request based on the adjusted mapping table; the affinity file represents a binding relationship between the interrupt request and the processor core, and the target mapping table represents a data transmission relationship between a processing queue of a network card related to the interrupt request and the processor core. Therefore, the interrupt request can be dynamically migrated, and the problem of interrupt overload is relieved.

The present disclosure relates to a method and system for managing a meeting session. In accordance with one example, there is provided a method of managing a meeting session on a server that manages the meeting session, the meeting session comprising one or more participant devices and a presenter device. The method comprises receiving one or more break request messages from the participant devices, and sending a break message to the participant devices, the break message causing a break notification to be displayed on a display of the participant devices.

The invention relates to the technical field of equipment control, and discloses a control method and system for ultrasonic cleaning equipment, and the method comprises the steps: obtaining parameters in an interruption controller and an MCU of the ultrasonic cleaning equipment, and determining an instruction upper limit value N; dividing interrupt instruction priorities, constructing an interrupt instruction matrix, calculating an interrupt risk value, and generating a risk analysis signal according to the risk value; a high-risk data set is constructed, to-be-sorted instructions with the same priority are sorted through a TOPSIS method, and an instruction distribution data set is constructed; based on the instruction distribution data set, the CPU occupancy rate, the interrupt upper limit value and the average processing time are combined to calculate an interrupt evaluation value Gz and output the interrupt evaluation value Gz to the MCU, the interrupt evaluation value Gz is used for measuring the load and risk degree of the system for processing the interrupt request, interrupt instruction distribution of the ultrasonic cleaning equipment can be optimized, and the system stability and reliability are improved.

An interrupt processing method. The method comprises: acquiring a first interrupt request; processing the first interrupt request by means of a first interrupt processing method; acquiring a second interrupt request; and processing the second interrupt request by means of a second interrupt processing method, wherein the first interrupt request and the second interrupt request are different interrupt requests, and the first interrupt processing method is different from the second interrupt processing method. In the present application, different interrupt processing methods may be used to process different interrupt requests. Since various types of interrupt requests are not processed by means of a fixed interrupt processing method, a corresponding interrupt request may be configured on the basis of a service scenario corresponding to the interrupt request.

Systems or methods of the present disclosure may provide for interrupt migration using a processor and / or system on a chip. The system includes multiple processing cores and an interrupt controller. The interrupt controller includes an input terminal configured to receive an interrupt request and an interrupt controller timer. The interrupt controller also includes an output terminal configured to output an interrupt based on the interrupt request. Furthermore, the interrupt controller includes an interface configuration and status circuitry configured to track a period of time that the interrupt is transmitted to a first processing core of the multiple processing cores.

The invention relates to a low-pin I2C serial transmission method and a low-pin I2C transmission system using the same. The low-pin I2C serial transmission method comprises the steps that a plurality of I2C serial transmission slave devices and an I2C serial transmission master device are provided, and the I2C serial transmission slave devices and the I2C serial transmission master device are electrically connected to an I2C serial transmission flat cable; coupling an interrupt request pin of each I2C serial transmission slave device to an interrupt input pin of the I2C serial transmission master device; when a specific I2C serial transmission slave device in each I2C serial transmission slave device proposes an interrupt request, the interrupt request pin of the specific I2C serial transmission slave device outputs a voltage corresponding to the specification of the specific I2C serial transmission slave device; and according to the voltage of the interrupt input pin of the I2C serial transmission master device, judging whether each of the I2C serial transmission slave devices meets the interrupt requirement or not.

The invention discloses a communication method, electronic equipment, a computer program product and a storage medium, which are applied to the technical field of communication, and comprise the following steps: when an interrupt request generated by a slave is detected, analyzing a slave address and taking the slave address as an index of an interrupt control table, and reading response information from the interrupt control table; the interrupt control table comprises response information corresponding to all slave addresses; the first equipment address table and the second equipment address table jointly form equipment information of all slaves, the second equipment address table and the interrupt control table are both stored in host hardware, and the first equipment address table is stored in a memory; when the data needs to be read from the slave, inquiring whether the slave address exists in the first equipment address table or not; and if yes, performing table item exchange, otherwise, receiving communication information issued by the host program and realizing communication with the slave. By applying the scheme of the invention, the problem of frequent replacement of slave equipment information can be effectively solved, and excessive host hardware resources cannot be consumed.

This invention discloses a master-slave task synchronization method, device, controller, and rail train, relating to the field of rail transit technology. The method includes: the current controller identifying the master-slave presence status on the rail train's chassis; determining the system master control status corresponding to the current controller based on the master-slave presence status; if the system master control status is in master control mode, generating an interrupt request at a first preset time interval, performing synchronization task processing according to the interrupt request, and sending the interrupt request to other present controllers. This invention achieves automatic master-slave controller identification by determining the system master control status corresponding to the current controller based on the identified master-slave presence status; by having one controller acting as the system master controller generate and send an interrupt request to other controllers acting as system slave controllers, all controllers can perform strict master-slave task synchronization according to the interrupt request of the system master controller, thus improving the accuracy of master-slave task synchronization.

The utility model proposes an inertial device data communication system based on FPGA and DSP, comprising an FPGA module, a DSP module, a FIFO cache module and an EMIF communication module; the FPGA module is responsible for reading the data of the inertial device in parallel through a serial port, and writing the data into the FIFO cache module of an IP core after completing the reading task, and is also responsible for monitoring the data volume in the FIFO, and when the data volume reaches a preset value, sending an interrupt request to the DSP module; the FIFO cache module adopts a non-read and write address line mode to perform a process of writing and reading data; the DSP module communicates with the FPGA module through the EMIF communication module, and when receiving the interrupt request of the FPGA module, the DSP module starts EMIF transmission, reads the cache data of the target address from the FPGA module, and the DSP module reads the data using an external interrupt mechanism, and performs corresponding processing, and after the processing is completed, transmits the processed data back to the FPGA module through the EMIF bus.

The embodiment of the invention discloses a task processing method and device based on a virtual processor, a medium and equipment, and the method comprises the steps: generating an interrupt request signal by a virtual timer under the condition that a physical processor corresponding to a virtual machine is in a first mode; the physical processor obtains the interrupt request signal and injects virtual interrupt information corresponding to the interrupt request signal into a virtual processor corresponding to the virtual machine; the virtual processor responds to the virtual interrupt information and executes a processing task corresponding to the virtual interrupt information, and the virtual processor represents processor resources distributed for the virtual machine in the physical processor. According to the embodiment of the invention, the performance overhead generated by storing and recovering the context information of the system timer can be avoided or reduced.

The invention provides an abnormal event processing method, electronic equipment and a storage medium, and relates to the technical field of communication. The electronic device detects a first interrupt request from a touch chip. In response to the first interrupt request, judging whether the touch chip has an interrupt abnormal event or not; and if the interruption abnormal event occurs in the touch chip, the electronic equipment sends first notification information to an upper system process, and shields an interruption request of the touch chip. The first notification information is used for notifying the system process not to indicate to start the interrupt response. By means of the mode, in the process that the interruption abnormal event happens to the touch control chip, the electronic device does not start the interruption response of the interruption request again, and the influence of the interruption abnormal event is reduced.

The application relates to the technical field of interrupt control, and discloses an interrupt control method, an interrupt controller, computer equipment and a storage medium, the method is applied to an interrupt controller, the method comprises the following steps: receiving a plurality of interrupt requests; determining the current priority of each interrupt request in the plurality of interrupt requests according to the N-time historical processing time length of each interrupt request in the plurality of interrupt requests, wherein N is a positive integer; and sending the plurality of interrupt requests to a processor according to the sequence of the current priorities of the plurality of interrupt requests. The application can flexibly adjust the priorities of the plurality of interrupt requests according to actual application scenes, and improves the performance of a system.

This application discloses an interrupt control device and method based on a RISC-V architecture, relating to the field of interrupt handling technology. The device includes a processor, an interrupt controller, and a data preparation module. The interrupt controller is used to acquire a first interrupt request and enable information sent by a first interrupt source; based on the enable information and the interrupt source ID corresponding to the first interrupt source, it queries the data load address information and data load length information corresponding to the interrupt handler; and generates a first interrupt signal based on the acquired first interrupt request. The data preparation module is used to load the target data corresponding to the interrupt handler from memory into the data preparation module based on the enable information, data load address information, and data load length information. The processor is used to suspend the general program after executing the current instruction of the general program; and respond to the first interrupt signal, execute the interrupt handler, and acquire the target data corresponding to the interrupt handler from the data preparation module.