113 results about "Process (computing)" patented technology

The invention discloses a computing power distribution method based on a dynamic window and multi-version correction, and relates to the technical field of intelligent resource scheduling, the method comprises the following steps: constructing a scheduling state set by monitoring a to-be-scheduled task set and a platform resource state of a cloud platform resource scheduling system in real time; based on time window dynamic judgment, extracting a stable and effective task set; calculating a scheduling priority coefficient in combination with task resource intensity, urgency and historical completion performance, determining a priority scheduling set and executing a first version scheduling scheme; the difference between the current scheduling version and the historical optimal scheme is evaluated through the residual vector and the offset coefficient, and whether version correction needs to be carried out or not is judged; and based on resource use feedback in the scheduling execution process, calculating a feedback change rate and judging whether a scheduling execution state is stable or not, and if the scheduling execution state is unstable, dynamically adjusting scheduling parameters. According to the method, accurate allocation of computing power resources, adaptive scheduling optimization and abnormal risk control are realized.

Disclosed herein are embodiments of systems, methods, and products for modernizing and optimizing legacy software. A computing device may perform an automated runtime performance profiling process. The performance profiler may automatically profile the legacy software at runtime, monitor the memory usage and module activities of the legacy software, and pinpoint / identify a subset of inefficient functions in the legacy software that scale poorly or otherwise inefficient. The computing device may further perform a source code analysis and refactoring process. The computing device may parse the source code of the subset of inefficient functions and identify code violations within the source code. The computing device may provide one or more refactoring options to optimize the source code. Each refactoring option may comprise a change to the source code configured to correct the code violations. The computing device may refactor the source code based on a selected refactoring option.

A system (100) or method (500) for preventing or mitigating malicious processes in a computing environment having one or more processors (204) and memory (202) operatively coupled to the one or more processors can include computer instructions which when executed causes the one or more processors to perform certain operations. The operations can include intercepting (502) all file system input and output paths using a kernel driver (103), analyzing (504) for suspect behaviors in real time on data being processed through the input and output paths and data access patterns on a live system implemented in a kernel of an operating system for the computing environment, flagging (512) the data for any suspect behaviors, and preventing (514) further processing upon detection of the suspect behaviors.

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention provides a method, a system and equipment for improving the computing performance stability of a hardware platform and a medium, and belongs to the technical field of computer system performance optimization. The method comprises the following steps: acquiring architecture characteristic data of a bottom hardware platform through a hardware detection tool, and generating and loading a first-stage system kernel parameter configuration based on the architecture characteristic data; reading the architecture characteristic data, carrying out behavior analysis and type identification on the running process based on the architecture characteristic data, and generating a second-level process scheduling strategy according to the behavior analysis and type identification; reading cache structure information in the architecture characteristic data, and driving a file system to intelligently prefetch and reconstruct a storage layout of memory data based on the cache structure information; and continuously collecting performance index flow data when the system runs, performing real-time analysis on the performance index flow data by using a performance degradation model, generating a feedback control instruction according to an analysis result, and dynamically correcting the kernel parameter configuration of the first-stage system and the scheduling strategy of the second-stage process.

The invention provides a multi-modal basic model convolution operation optimization framework method suitable for a GPU / DCU. The method is used for solving the technical problems that the optimization process of an existing convolution operator optimization method is time-consuming and cross-layer operator fusion is difficult to capture. The method comprises the following steps: receiving a convolution operator through a parameterized input interface; collecting shape features of each convolution operator in the structured parameter set by using a shape analyzer to realize convolution feature analysis; judging whether batch normalization and nonlinear activation function fusion calculation is started or not; a heuristic optimizer dynamically selects a calculation graph optimization strategy based on convolution parameter characteristics; a calculation task is adapted to a physical architecture of the GPU / DCU, so that hardware resources are utilized to the maximum extent; a convolution calculation kernel function oriented to DCU / GPU architecture optimization is generated based on the convolution parameter features; kernel function assembly line execution is achieved through a DCU / GPU hardware task queue; gradient synchronization among multiple computing units is realized by adopting atomic operation at an equipment end. According to the method, the execution efficiency of the convolution operation in the multi-modal basic model can be remarkably improved.

The invention discloses a detection and correction device and method based on an RISC-V architecture, belongs to the technical field of processor micro-architectures, and aims to solve the technical problem of how to carry out error detection and correction on an instruction execution process, hardware resources, system reliability, instruction storage, a data path and related system performance in the RISC-V architecture. Comprising a computing core, a cross validation module, a dynamic voting module, a lock step execution module and a hardware multiplexing module, the processor is used for comparing and checking the instruction execution results output by the three calculation cores based on a triple modular redundancy technology and a dynamic voting fault-tolerant technology, and determining the instruction execution result with correct voting through a two-out-of-three voting mode; the lock step execution module is used for controlling lock step execution and assembly line rollback operation of the calculation core; and the hardware multiplexing module is used for multiplexing the same RISC-V pipeline to process normal execution, lock step and rollback operations.

An example computing device includes a storage device, a random-access memory, a read only memory, and a processor. The processor is to determine, during a booting process, whether an operating system being booted is a primary operating system, in response to a determination that the operating system being booted is different from the primary operating system, determine whether the operating system being booted satisfies a first criteria, and, in response to a determination that the operating system being booted fails to satisfy the first criteria, disable software persistence.

The invention provides a task processing method, system, device and equipment based on a large model and a medium, and relates to the technical field of large language models.The method comprises the steps that a first prompt text is generated according to a reasoning task request from a user side; generating a first script based on the first prompt text through a large language model; executing the first script through a script executor to obtain a first execution result; generating a second prompt text according to the first execution result and the reasoning task request; reasoning is carried out based on the second prompt text through the large language model, reasoning task response of the reasoning task request is obtained, and calculation tasks of the large language model can be outsourced to a script executor so that the calculation amount can be reduced; and the reasoning process of the system is iteratively optimized by adopting a bidirectional feedback mechanism between the large language model and the script executor, so that the calculation efficiency, the accuracy and the reliability of the task are improved.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention discloses a node distribution method and system for a GPU (Graphics Processing Unit) use process in an NUMA (Non Uniform Memory Access) environment, and the method comprises the following steps: in a kernel mode, capturing an event that the process executes a new program and collecting meta-information of the process through an eBPF program mounted at a system call entry tracking point, and judging whether the process is a target GPU process or not based on the collected meta-information of the process; if the process is the target GPU process, transmitting meta-information of the process to a user mode, and if the process is not the target GPU process, ending and exiting; and for the meta-information transmitted to each target GPU process of the user mode, reading the meta-information of the target GPU process through the user mode daemon process, evaluating each node in the NUMA environment based on a preset node allocation rule, selecting an optimal NUMA node, and binding the target GPU process to a CPU of the optimal NUMA node for execution. The GPU computing efficiency and the resource utilization rate can be improved.

One disclosed method involves receiving, at a first application programming interface (API) endpoint of a computing system, a first API call requesting performance of a first type of operation; invoking, by the computing system and based on the first API call, a first process to send at least a second API call to a second API endpoint of a first system of record; receiving, by the computing system and from the first system of record, a first response to the second API call; and sending, from the computing system to a source of the first API call, a second response that is based at least in part on the first response.

A computing system comprising one or more computing devices can access a file comprising documentation that includes a textual description and a source code snippet written to comply with a programming language syntax. The computing system can identify the source code snippet. The computing system can generate an executable based on the source code snippet. The computing system can initiate a test process that accesses the executable, the test process causing the executable to cause an event. The computing system can determine that the event is a valid event or an invalid event.

The invention belongs to the technical field of cloud computing heterogeneous resource scheduling, and particularly provides a multi-architecture virtualization environment integration and unified operation and maintenance method and system, and the method comprises the steps: detecting the underlying hardware characteristics of a source architecture and a target architecture; generating a hardware semantic abstract model based on the underlying hardware characteristics; carrying out compatibility analysis on the cross-architecture virtual machine instruction stream, and identifying atomic operation semantic conflicts and interrupt routing logic conflicts; generating an instruction translation rule and a micro-architecture cleaning strategy; converting an instruction stream and cleaning a branch predictor of a source architecture and a residual state of an out-of-order execution buffer area; and synchronizing the cleaned micro-architecture state and the conversion instruction stream to the target virtual machine. According to the method and the system, instruction stream conversion in a virtual machine migration process can be dynamically matched with micro-architecture characteristics of a target architecture, seamless connection of execution environments in a cross-architecture migration process is realized, cross-architecture conflicts can be prevented, and the problems of migration conflicts and performance degradation of the virtual machine of a virtualization platform are solved.

The invention discloses a kernel process scheduling associated information monitoring method and device, a medium and a product, which are applied to the field of cloud computing, and the method comprises the following steps: tracking a related function of kernel process scheduling to determine a calling condition of the related function; when the process awakening function or the new process awakening function is called, recording awakened process information according to the called related function; and when the process scheduling switching function is called, respectively generating a scheduling time delay record and a preemption event record according to the process scheduling switching function. By tracking the calling condition of the related function, the key event of kernel process scheduling can be obtained in real time, and the system overhead caused by kernel modification or additional tool deployment is avoided. By recording the waken process information, a foundation is laid for the subsequent calculation of the scheduling time delay. By generating the time delay record and the preemption event, the scheduling time delay of the container process can be directly quantified, the resource preemption relationship between the containers can be positioned, and the event record can be directly used for subsequent interference source positioning and automatic disposal.

In multi-threaded or multi-processor computing systems, a deadlock may occur when two or more processes or threads are unable to proceed because they are each waiting for a resource that the other holds. As a result, progress is halted because conflicting entities are stuck in a circular dependency, and none can release the resources they hold to let the others continue. Systems and methods are provided wherein a resource reservation is carried out in two steps. The first step causes query nodes to add an identifier to a queue and, upon a request and the identifier being in a first position, a non-sharable resource is reserved. As a result, non-sharable resources are reserved in order and when needed, thereby preventing deadlocks.

The embodiment of the invention discloses a data interaction method, system and device based on a trusted execution environment, a medium and a program. The method comprises the steps that a trusted application generates an original request instruction according to request data and sends the original request instruction to a target TEE SE API; the target TEE SE API converts the original request instruction to obtain a conversion request instruction and sends the conversion request instruction to an SE protocol stack entry API; the SE protocol stack entry API carries out SE protocol stack data unification processing on the conversion request instruction to obtain a unified request instruction and sends the unified request instruction to an SE protocol stack; the SE protocol stack sends the unified request instruction to an SE hardware unit; and the SE hardware unit processes the unified request instruction to generate an original response instruction. According to the technical scheme, the adaptation cost, the maintenance cost and the memory computing space in the data interaction process based on the trusted execution environment can be reduced, and the efficiency and maintainability of data interaction based on the trusted execution environment are improved.

The invention requests to protect a multi-machine system synchronization method based on a CXL shared cache consistent memory. Relates to the technical field of high-performance computing and memory interconnection, at present, a plurality of synchronization mechanisms are provided in a Linux system, and the synchronization mechanisms are designed to face a multi-core and multi-process environment of a stand-alone system and are used for guaranteeing concurrent access of a plurality of processes to shared data. However, the action range of an existing synchronization mechanism is limited in a single system, and for the situation that multiple processes belonging to multiple independent host systems concurrently access data in a CXL shared memory, the cross-host concurrent access requirement exceeds the application range of the existing Linux synchronization mechanism, data competition and inconsistent access are possibly caused by direct use, and the data access efficiency is improved. Even if the system crashes, the cross-host access security on the CXL shared memory cannot be ensured. The invention aims to construct a safe and efficient synchronization mechanism oriented to multi-system parallel access CXL shared memory data so as to realize cross-host multi-process synchronous access to the data in the CXL shared memory.

The embodiment of the application relates to the computer technical field, and provides a task execution log processing method and system and a computing device, the method is applied to the computing device carrying an operation and maintenance system, the method comprises the following steps: in response to that a task execution request is received by an execution engine unit, a callback event in a task execution process is monitored through a log processing plug-in; when the callback event is monitored, task execution data is recorded; the task execution data is encapsulated as structured log information; the structured log information is output in real time through a log output unit to replace output content of the log output unit. Based on the scheme, the computing device can embed the log processing plug-in in the operation and maintenance system, capture the callback event generated in the task execution process in real time, obtain the data in the task execution process as the log in the task running, so that the operation and maintenance system can realize the real-time structured output of the log without modifying the architecture, and blind areas of the operation and maintenance system in the task execution process are avoided.

In some aspects, a method can be performed by a processor of a computing device. The method includes generating a non-executable code template that includes code that defines a set of operations. Additionally, the method includes accessing data about a particular project. Further, the method includes determining a set of project variables that pertain to the particular project and determining a set of project logic that pertains to the particular project. Furthermore, the method includes generating an executable code by integrating the set of project variables and the set of project logic into the non-executable code template. Moreover, the method includes compiling the executable code and generating a result by executing the compiled executable code.

The invention discloses a graph structure force guided dynamic spring effect acceleration method based on GPU parallel computing. The method comprises the following steps: dividing three independent GPU kernel functions; a resource allocation strategy is adopted under the Ada architecture, and execution configuration is generated; introducing a thread coarsening method to generate an optimized kernel execution result; generating a node position calculation result by using a shared memory privatization method and a reduce operator fusion method in combination with an improved KIFMM algorithm; in the iterative updating stage, an iterative updating result of the node position is obtained; performing cooling processing on the node position updating process by using a simulated annealing algorithm; the real-time visualization and analysis requirements are met, the calculation efficiency of large-scale graph data can be remarkably improved, the convergence time is shortened, and the method has the advantages of being high in calculation speed, high in convergence stability and wide in application range.

The invention relates to the technical field of computer compiling, and discloses a method and a device for simultaneously compiling multiple architectures, computer equipment and a storage medium. According to the method for simultaneously compiling the multiple architectures, the code files input by the user are processed through the user-defined linker, the multiple code files are analyzed, and therefore analysis operation in the compiling process in all the architectures can be advanced, and a unified intermediate file is generated. And continuing to compile the generated unified intermediate file in each architecture, and finally obtaining an executable file or a library file corresponding to each architecture. According to the embodiment of the invention, the analysis operation is advanced, and the unified intermediate file is generated, so that the analysis operation does not need to be executed for multiple times when compiling is continued under each framework, and the effects of shortening the compiling time and saving computing resources can be achieved.

The invention discloses an SIMD instruction arrangement method based on an RISC-V architecture, and belongs to the field of processor instruction arrangement. The method comprises the following steps: identifying and analyzing an SIMD applicable part in a calculation process as a calculation task for SIMD optimization; designing a basic code template according to the calculation task, and abstractly expressing the calculation task; mapping the operation in the basic code to an SIMD calculation structure; designing an SIMD (Single Instruction Multiple Data) instruction according to the vector extension characteristic of the RISC-V architecture; the SIMD instruction sequence is rearranged, so that the instructions of the loop body are expanded, the same instructions are executed in a centralized mode, the idle period between the instructions is shortened, and the parallelism degree and throughput of instruction execution are improved. According to the method, the execution cycles of all types of instructions are shortened, so that the overall computing performance is greatly improved, the energy consumption is reduced, the resource utilization rate is improved, and the GPU is more efficient when processing large-scale parallel computing tasks.

The invention provides an instruction generation method and device, a computing system and computing equipment, and relates to the technical field of AI.In the method, cue words are input into a large language model to generate an instruction set related to a document fragment by utilizing the generation capacity of the large language model, then the instruction set is evaluated, and when an evaluation result does not meet a preset condition, the document fragment is generated. And the cue word is adjusted in time according to the evaluation result to determine a target instruction set related to the document fragment. Thus, the feedback relation between instruction generation and instruction evaluation is established, the cue word can be adjusted in time according to the instruction evaluation result in the process of efficiently generating the instruction set, namely, the strategy of generating the instruction set by the large language model is adjusted, and therefore the quality of the finally obtained instruction set is improved.

A method and system for threat detection and analysis is disclosed herein. The method includes monitoring at least one thread associated with at least one process on a computing system. The method further includes detecting specific system calls associated with at least one process at kernel level. The specific system calls are analyzed by applying a filter to the system calls sequence feature set associated with the specific system calls for detecting one or more events of interest. A full stack trace capture of at least one process is requested if the system calls sequence feature set is filtered and the one or more events of interest are detected. A first level monitoring is provided to the computing system, which includes processing and analyzing the captured full stack trace by a machine learning (ML) stack trace analyzer to generate a first verdict for threat detection and analysis.

The application discloses a method for obtaining a call stack when simulating running an application program and a computing device. The computing device comprises a first architecture processor and runs a first operating system. A second application program running a second operating system is simulated and run through a simulator. The method comprises the following steps: converting second architecture instructions of the compatibility layer and the second application program into first architecture instructions through the simulator and executing the first architecture instructions; in response to an interruption of the first architecture processor, debugging the simulator and obtaining an input extended command; executing the extended command to obtain current second architecture registers of a second architecture site from an interruption site of the first architecture processor; and obtaining a call stack of the second architecture instructions of the compatibility layer or the second application program based on the current second architecture registers. According to the technical scheme of the application, in the debugging process of the simulator, an error site of the second architecture instructions can be intuitively observed in the interruption site.

A computing device executing a kernel-based operating system, during a boot process of the operating system, can start a first system and service manager that is configured to start processes from unit files stored in a predetermined directory on a first root volume. The computing device can start, by the first system and service manager, a process from a first unit file that causes generation of a first restricted container environment that includes a second system and service manager, and a second root volume can be mounted to the first restricted container environment. The computing device can start, by the second system and service manager, a process from a second unit file stored in a predetermined directory on the second root volume and the process can execute inside the first restricted container environment.

The present application relates to a method for completing a programmable atomic transaction. In some examples, methods, systems, computing devices, and machine-readable media are disclosed for defining instructions for a programmable atomic transaction. These instructions, when executed as the last instruction, terminate the executing thread, wait for all outstanding store operations to complete, clear a programmable atomic lock, and send a completion response back to the issuing process. This ensures that the programmable atomic lock is cleared upon completion of the transaction. By coupling thread termination with clearing the lock bit, this ensures that the thread cannot terminate without clearing the lock.

In mutation testing, source code is mutated at various positions, and test suites are run against the original object code and each version of the mutated object code, to determine the quality of test suites against arbitrary changes in the object code. The present disclosure provides a mutation test manager configured to initialize multiple computing threads configuring a computing host to perform parallel computation; mutate class files within context of each computing thread; recompile mutated class files independently in each respective computing thread to generate heterogeneous mutants; and execute pending unit tests against heterogeneous mutants independently in each respective computing thread. Consequently, the mutation testing process is decoupled from computational bottlenecks which would result from linear, sequential generation, compilation, and testing of each mutation, especially in the context of JVM® programming languages configured to generate class-rich object code.

The invention relates to secure verification of firmware. A computing system is described for securely verifying system firmware and recovering firmware to ensure system integrity without relying on a proprietary verification process of manufacture, hardware-specific keys, or intrinsic write protection features of system memory. In one embodiment, a computing system relies on a security processor that maintains firmware management parameters that define a process for verifying and recovering firmware independent of a mask ROM (Read Only Memory) verification process of an integrated circuit manufacturer. The security processor ensures that the firmware or recovery firmware is properly signed and coincides with a previously executed version, or if different, generates a verification result (e.g., a generated hash value) that coincides with an expected result embedded in the firmware at the time of compilation. In this manner, the computing system improves availability, customization, and user control on firmware executing within the computing system and restoring firmware.