148 results about "Process (computing)" patented technology

Techniques for identifying malware based on system API function pointers are disclosed. In some embodiments, a system / process / computer program product for identifying malware based on system API function pointers includes monitoring changes in memory during execution of a malware sample in a computing environment; detecting a dynamic evasion behavior using an Application Programming Interface (API) vector comprising a plurality of system API function pointers identified in the memory during execution of the malware sample in the computing environment; and generating a signature based on the API vector for automatically detecting the malware during execution in the memory, wherein the malware sample was determined to be malicious.

The invention discloses a computing power distribution method based on a dynamic window and multi-version correction, and relates to the technical field of intelligent resource scheduling, the method comprises the following steps: constructing a scheduling state set by monitoring a to-be-scheduled task set and a platform resource state of a cloud platform resource scheduling system in real time; based on time window dynamic judgment, extracting a stable and effective task set; calculating a scheduling priority coefficient in combination with task resource intensity, urgency and historical completion performance, determining a priority scheduling set and executing a first version scheduling scheme; the difference between the current scheduling version and the historical optimal scheme is evaluated through the residual vector and the offset coefficient, and whether version correction needs to be carried out or not is judged; and based on resource use feedback in the scheduling execution process, calculating a feedback change rate and judging whether a scheduling execution state is stable or not, and if the scheduling execution state is unstable, dynamically adjusting scheduling parameters. According to the method, accurate allocation of computing power resources, adaptive scheduling optimization and abnormal risk control are realized.

Disclosed herein are embodiments of systems, methods, and products for modernizing and optimizing legacy software. A computing device may perform an automated runtime performance profiling process. The performance profiler may automatically profile the legacy software at runtime, monitor the memory usage and module activities of the legacy software, and pinpoint / identify a subset of inefficient functions in the legacy software that scale poorly or otherwise inefficient. The computing device may further perform a source code analysis and refactoring process. The computing device may parse the source code of the subset of inefficient functions and identify code violations within the source code. The computing device may provide one or more refactoring options to optimize the source code. Each refactoring option may comprise a change to the source code configured to correct the code violations. The computing device may refactor the source code based on a selected refactoring option.

The invention discloses a memory partition-based dynamic instruction conversion memory access conflict optimization method, which comprises the following steps of: allocating memory sub-regions for each computing core according to a load condition in an ARM (Advanced RISC Machines) many-core system to establish a first mapping relation table; when the executable file is loaded and executed in a dynamic instruction conversion mode, obtaining a second mapping relation table between the thread and the calculation core, and obtaining a thread and a memory address corresponding to a to-be-converted instruction of a memory access instruction class, obtaining a converted first ARM virtual address and a related first address space according to the first mapping relation table and the second mapping relation table, and determining an adjustment mode of the converted instruction according to the relation between the first ARM virtual address and the first address space to complete instruction conversion. The memory access conflict in the dynamic conversion process from the x86 instruction to the ARM instruction on an ARM many-core system is effectively reduced, and the execution performance of a program after dynamic instruction conversion is improved.

The invention provides an automatic test system and method capable of being arranged and executed in batches, and the system comprises a test case arrangement plan table which is used for customizing the starting time, the precondition and the dependency relationship of each test item, whether execution is terminated or not when the test item fails, grouping execution, result archiving, product dependency and user-defined labels; the default configuration management module is used for parameterizing execution and supporting simple configuration to realize visual operation of the test script; the software framework supports an object-oriented language and provides multi-process processing to improve execution efficiency; and the distributed structure is used for realizing concurrent parallel execution across a plurality of processors or machines and supporting synchronous import and concurrent asynchronous execution of a plurality of test items. Through the support of multi-process processing and a distributed structure, the advantages of a multi-core processor and computing resources of cross-network nodes can be fully utilized, multiple test items are executed in parallel, the execution efficiency of automatic testing is greatly improved, and the overall testing period is shortened.

A system (100) or method (500) for preventing or mitigating malicious processes in a computing environment having one or more processors (204) and memory (202) operatively coupled to the one or more processors can include computer instructions which when executed causes the one or more processors to perform certain operations. The operations can include intercepting (502) all file system input and output paths using a kernel driver (103), analyzing (504) for suspect behaviors in real time on data being processed through the input and output paths and data access patterns on a live system implemented in a kernel of an operating system for the computing environment, flagging (512) the data for any suspect behaviors, and preventing (514) further processing upon detection of the suspect behaviors.

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention provides a multi-thread beam debugging method and device and an artificial intelligence chip, and relates to the technical field of artificial intelligence, and the method comprises the steps: determining an expected thread beam to trigger debugging based on a comparison result of instruction information of executing an original program by each thread beam and instruction information stored in a target register group, and a thread beam identifier of each thread beam; sending debugging trigger information to a processor to enable the processor to send debugging enabling information to each thread bundle, and controlling the unexpected thread bundle to wait for the expected thread bundle to be debugged; based on the debugging enabling information, controlling the expected thread bundle to execute the debugging program based on an instruction address of the debugging program stored in the target register group; and sending debugging ending information to the processor to enable the processor to send debugging stopping information to each thread bundle, and controlling each thread bundle to continue to execute the original program. According to the method and the device provided by the invention, the debugging aiming at the specific thread beam can be realized in the multi-thread beam parallel computing process.

The invention provides a parallel computing method for supporting real-time data stream processing in parallel programming, which comprises the following steps of: dividing a real-time data stream into fragments through a parallel pipeline, and filtering specified fields by different threads to improve the efficiency; after filtering is completed, performing local aggregation on a result by using a local aggregation function of MapReduce to reduce the data volume; a distributed memory database based on Redis Cluster is established, and data are stored in a fragmented mode according to a time window; constructing a long-short-term memory recurrent neural network model, and performing parallel training through a parameter server architecture; if the long short-term memory recurrent neural network model needs incremental learning, a parameter interface is reserved for iterative updating, and repeated training is avoided; after training is completed, the model is deployed to a GPU server, and real-time data flow is predicted; through a task scheduler of a distributed memory computing framework, cooperation between threads and processes is automatically managed, and programming work is simplified.

The invention provides a method, a system and equipment for improving the computing performance stability of a hardware platform and a medium, and belongs to the technical field of computer system performance optimization. The method comprises the following steps: acquiring architecture characteristic data of a bottom hardware platform through a hardware detection tool, and generating and loading a first-stage system kernel parameter configuration based on the architecture characteristic data; reading the architecture characteristic data, carrying out behavior analysis and type identification on the running process based on the architecture characteristic data, and generating a second-level process scheduling strategy according to the behavior analysis and type identification; reading cache structure information in the architecture characteristic data, and driving a file system to intelligently prefetch and reconstruct a storage layout of memory data based on the cache structure information; and continuously collecting performance index flow data when the system runs, performing real-time analysis on the performance index flow data by using a performance degradation model, generating a feedback control instruction according to an analysis result, and dynamically correcting the kernel parameter configuration of the first-stage system and the scheduling strategy of the second-stage process.

The invention provides a multi-modal basic model convolution operation optimization framework method suitable for a GPU / DCU. The method is used for solving the technical problems that the optimization process of an existing convolution operator optimization method is time-consuming and cross-layer operator fusion is difficult to capture. The method comprises the following steps: receiving a convolution operator through a parameterized input interface; collecting shape features of each convolution operator in the structured parameter set by using a shape analyzer to realize convolution feature analysis; judging whether batch normalization and nonlinear activation function fusion calculation is started or not; a heuristic optimizer dynamically selects a calculation graph optimization strategy based on convolution parameter characteristics; a calculation task is adapted to a physical architecture of the GPU / DCU, so that hardware resources are utilized to the maximum extent; a convolution calculation kernel function oriented to DCU / GPU architecture optimization is generated based on the convolution parameter features; kernel function assembly line execution is achieved through a DCU / GPU hardware task queue; gradient synchronization among multiple computing units is realized by adopting atomic operation at an equipment end. According to the method, the execution efficiency of the convolution operation in the multi-modal basic model can be remarkably improved.

The invention discloses a Linux process code segment measurement enhancement method based on a dual-system architecture. The method comprises the following steps: S1, collecting a process reference value; and S2, adding a kernel key data monitoring mechanism. And S3, measuring the process in real time. Based on a trusted execution environment, a prototype system for measuring the process in real time when the Linux operating system runs is realized on the basis of trusted startup, and the prototype system provides a mechanism for immediately initiating real-time measurement when kernel key data operation is abnormal while periodically measuring a process code segment. Kernel key data comprises a system call table, an interrupt descriptor table and SELinux enabling and configuration information, and the scheme solves a certain TOCTTOU problem and enhances the security of the Linux system. According to the method, real-time measurement on the processes related to kernel key data operation during operation of the computing component operating system is completed, the safety of the system is enhanced in the operation process of the operating system, the credibility of a computing platform is guaranteed, and the method conforms to the active immune credible idea.

Methods and apparatus for real-time security monitoring on a computing device are presented. A system may define privileges to access hardware interfaces for each process of a plurality of processes executing on a computing device. The privileges may be defined in a privileged operating system level that controls root access to an operating system. In response to a determination that a process is attempting to access a hardware interface, the system may determine whether the process is privileged to access the hardware interface by checking the privileges. In response to determining that the process is not privileged to access the hardware interface, the intrusion detection agent may terminate the process.

The invention discloses a detection and correction device and method based on an RISC-V architecture, belongs to the technical field of processor micro-architectures, and aims to solve the technical problem of how to carry out error detection and correction on an instruction execution process, hardware resources, system reliability, instruction storage, a data path and related system performance in the RISC-V architecture. Comprising a computing core, a cross validation module, a dynamic voting module, a lock step execution module and a hardware multiplexing module, the processor is used for comparing and checking the instruction execution results output by the three calculation cores based on a triple modular redundancy technology and a dynamic voting fault-tolerant technology, and determining the instruction execution result with correct voting through a two-out-of-three voting mode; the lock step execution module is used for controlling lock step execution and assembly line rollback operation of the calculation core; and the hardware multiplexing module is used for multiplexing the same RISC-V pipeline to process normal execution, lock step and rollback operations.

An example computing device includes a storage device, a random-access memory, a read only memory, and a processor. The processor is to determine, during a booting process, whether an operating system being booted is a primary operating system, in response to a determination that the operating system being booted is different from the primary operating system, determine whether the operating system being booted satisfies a first criteria, and, in response to a determination that the operating system being booted fails to satisfy the first criteria, disable software persistence.

The invention provides a task processing method, system, device and equipment based on a large model and a medium, and relates to the technical field of large language models.The method comprises the steps that a first prompt text is generated according to a reasoning task request from a user side; generating a first script based on the first prompt text through a large language model; executing the first script through a script executor to obtain a first execution result; generating a second prompt text according to the first execution result and the reasoning task request; reasoning is carried out based on the second prompt text through the large language model, reasoning task response of the reasoning task request is obtained, and calculation tasks of the large language model can be outsourced to a script executor so that the calculation amount can be reduced; and the reasoning process of the system is iteratively optimized by adopting a bidirectional feedback mechanism between the large language model and the script executor, so that the calculation efficiency, the accuracy and the reliability of the task are improved.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The embodiment of the invention provides a container engine of a computing node and a container arrangement method, and the container engine is realized based on C language operation, and comprises a CRI interface which is used for providing a CR I standard interface for the container engine to an external container management node; the mirror image management unit is used for carrying out mirror image management on each container on the computing node based on an OC I mirror image standard; during container operation, the container operation module is used for providing container operation time based on an OCI mirror image standard for each container; when the ubiquitous system runs, the system is used for providing running environments with mutually isolated resources for the containers through the ubiquitous system, and when the containers run according to the running environments, the ubiquitous system comprises a thread-based operating system, a process-based operating system, a partition operating system and a virtual machine operating system. According to the technical scheme, the container engine is achieved through the C language, standard container arrangement is supported, and various embedded real-time container scenes such as tasks, processes, partitions and virtual machines are supported.

The invention discloses a program debugging method, a debugger and computing equipment. The debugger determines a next program code entering in a single step as a first glue code, the first glue code is a first-layer code in glue codes between a first function and a second function, the first function calls the second function, and the first function and the second function are obtained by compiling through different compiling languages; the debugger determines that the second function is a breakpoint of the program; and the debugger continuously executes the program to the breakpoint. For the operation steps of a developer, after entering the first function, the developer can reach the second function, and because the glue code between the first function and the second function is automatically operated in the program, the developer does not sense the operation process of the glue code and does not need to manually operate each function for operating the glue code, so that the operation efficiency is improved. And the program debugging efficiency is improved.

The invention discloses a node distribution method and system for a GPU (Graphics Processing Unit) use process in an NUMA (Non Uniform Memory Access) environment, and the method comprises the following steps: in a kernel mode, capturing an event that the process executes a new program and collecting meta-information of the process through an eBPF program mounted at a system call entry tracking point, and judging whether the process is a target GPU process or not based on the collected meta-information of the process; if the process is the target GPU process, transmitting meta-information of the process to a user mode, and if the process is not the target GPU process, ending and exiting; and for the meta-information transmitted to each target GPU process of the user mode, reading the meta-information of the target GPU process through the user mode daemon process, evaluating each node in the NUMA environment based on a preset node allocation rule, selecting an optimal NUMA node, and binding the target GPU process to a CPU of the optimal NUMA node for execution. The GPU computing efficiency and the resource utilization rate can be improved.

One disclosed method involves receiving, at a first application programming interface (API) endpoint of a computing system, a first API call requesting performance of a first type of operation; invoking, by the computing system and based on the first API call, a first process to send at least a second API call to a second API endpoint of a first system of record; receiving, by the computing system and from the first system of record, a first response to the second API call; and sending, from the computing system to a source of the first API call, a second response that is based at least in part on the first response.

A method for performing a technical process in which application programs are executed redundantly in a plurality N of computing instances and, on the basis of an MooN system, wherein M is at least two and N is at least three, a comparison of the plurality N of results of the redundant execution of the application programs is performed in a voting. When a minority of the results is different from a majority of the results with identical content, the minority is excluded during the performance of the technical process, is repaired with a state copy of one of the intact computing instances and reintegrated into the process. There is also described a computer program product and a provisioning apparatus.

A computing system comprising one or more computing devices can access a file comprising documentation that includes a textual description and a source code snippet written to comply with a programming language syntax. The computing system can identify the source code snippet. The computing system can generate an executable based on the source code snippet. The computing system can initiate a test process that accesses the executable, the test process causing the executable to cause an event. The computing system can determine that the event is a valid event or an invalid event.

The invention relates to an efficient execution optimization method for an embedded operating system based on an MIPS instruction set, and belongs to the field of computer operating systems. The method comprises the following measures: improving the parallelism of instructions: maximizing the parallel execution of the instructions through the intelligent analysis and dynamic scheduling strategy of an operating system; enhancing branch prediction capability: based on process and thread affinity, adding an intelligent scheduling strategy, cache consistency optimization and affinity strategy dynamic adjustment; the context switching efficiency is optimized; and through an improved context switching mechanism, the overhead during task switching of the operating system is reduced. According to the method, the instruction parallelism is enhanced, so that the processor can more efficiently execute a plurality of instructions; the branch prediction accuracy is improved, and the performance loss caused by wrong prediction is reduced; by improving the context switching efficiency, the overhead during task switching is reduced. These measures collectively ensure smoother computing and more efficient management.

The invention belongs to the technical field of cloud computing heterogeneous resource scheduling, and particularly provides a multi-architecture virtualization environment integration and unified operation and maintenance method and system, and the method comprises the steps: detecting the underlying hardware characteristics of a source architecture and a target architecture; generating a hardware semantic abstract model based on the underlying hardware characteristics; carrying out compatibility analysis on the cross-architecture virtual machine instruction stream, and identifying atomic operation semantic conflicts and interrupt routing logic conflicts; generating an instruction translation rule and a micro-architecture cleaning strategy; converting an instruction stream and cleaning a branch predictor of a source architecture and a residual state of an out-of-order execution buffer area; and synchronizing the cleaned micro-architecture state and the conversion instruction stream to the target virtual machine. According to the method and the system, instruction stream conversion in a virtual machine migration process can be dynamically matched with micro-architecture characteristics of a target architecture, seamless connection of execution environments in a cross-architecture migration process is realized, cross-architecture conflicts can be prevented, and the problems of migration conflicts and performance degradation of the virtual machine of a virtualization platform are solved.

The invention discloses a kernel process scheduling associated information monitoring method and device, a medium and a product, which are applied to the field of cloud computing, and the method comprises the following steps: tracking a related function of kernel process scheduling to determine a calling condition of the related function; when the process awakening function or the new process awakening function is called, recording awakened process information according to the called related function; and when the process scheduling switching function is called, respectively generating a scheduling time delay record and a preemption event record according to the process scheduling switching function. By tracking the calling condition of the related function, the key event of kernel process scheduling can be obtained in real time, and the system overhead caused by kernel modification or additional tool deployment is avoided. By recording the waken process information, a foundation is laid for the subsequent calculation of the scheduling time delay. By generating the time delay record and the preemption event, the scheduling time delay of the container process can be directly quantified, the resource preemption relationship between the containers can be positioned, and the event record can be directly used for subsequent interference source positioning and automatic disposal.

The invention provides a man-machine collaborative program repairing method based on a large language model, relates to the technical field of automatic program repairing, and remarkably improves the accuracy and success rate of program repairing. According to the method, a large language model is guided through preliminary analysis of manual teaching, errors in a program can be more accurately positioned and repaired by combining a repairing process of multiple iterations and more information introduced step by step, misjudgment and omission are reduced, and the program repairing efficiency is greatly improved. Compared with a traditional method, blind exploration of a large language model on complex problems is avoided through a man-machine cooperation mode, time and computing resources are saved, and adaptability of program repair is enhanced. According to the method, program defects of various types and complexity can be handled, and simple grammar errors or complex logic errors can be effectively handled through a step-by-step deep repair process.

In multi-threaded or multi-processor computing systems, a deadlock may occur when two or more processes or threads are unable to proceed because they are each waiting for a resource that the other holds. As a result, progress is halted because conflicting entities are stuck in a circular dependency, and none can release the resources they hold to let the others continue. Systems and methods are provided wherein a resource reservation is carried out in two steps. The first step causes query nodes to add an identifier to a queue and, upon a request and the identifier being in a first position, a non-sharable resource is reserved. As a result, non-sharable resources are reserved in order and when needed, thereby preventing deadlocks.

The embodiment of the invention discloses a data interaction method, system and device based on a trusted execution environment, a medium and a program. The method comprises the steps that a trusted application generates an original request instruction according to request data and sends the original request instruction to a target TEE SE API; the target TEE SE API converts the original request instruction to obtain a conversion request instruction and sends the conversion request instruction to an SE protocol stack entry API; the SE protocol stack entry API carries out SE protocol stack data unification processing on the conversion request instruction to obtain a unified request instruction and sends the unified request instruction to an SE protocol stack; the SE protocol stack sends the unified request instruction to an SE hardware unit; and the SE hardware unit processes the unified request instruction to generate an original response instruction. According to the technical scheme, the adaptation cost, the maintenance cost and the memory computing space in the data interaction process based on the trusted execution environment can be reduced, and the efficiency and maintainability of data interaction based on the trusted execution environment are improved.

The invention requests to protect a multi-machine system synchronization method based on a CXL shared cache consistent memory. Relates to the technical field of high-performance computing and memory interconnection, at present, a plurality of synchronization mechanisms are provided in a Linux system, and the synchronization mechanisms are designed to face a multi-core and multi-process environment of a stand-alone system and are used for guaranteeing concurrent access of a plurality of processes to shared data. However, the action range of an existing synchronization mechanism is limited in a single system, and for the situation that multiple processes belonging to multiple independent host systems concurrently access data in a CXL shared memory, the cross-host concurrent access requirement exceeds the application range of the existing Linux synchronization mechanism, data competition and inconsistent access are possibly caused by direct use, and the data access efficiency is improved. Even if the system crashes, the cross-host access security on the CXL shared memory cannot be ensured. The invention aims to construct a safe and efficient synchronization mechanism oriented to multi-system parallel access CXL shared memory data so as to realize cross-host multi-process synchronous access to the data in the CXL shared memory.