63 results about "Process (computing)" patented technology

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention provides a method, a system and equipment for improving the computing performance stability of a hardware platform and a medium, and belongs to the technical field of computer system performance optimization. The method comprises the following steps: acquiring architecture characteristic data of a bottom hardware platform through a hardware detection tool, and generating and loading a first-stage system kernel parameter configuration based on the architecture characteristic data; reading the architecture characteristic data, carrying out behavior analysis and type identification on the running process based on the architecture characteristic data, and generating a second-level process scheduling strategy according to the behavior analysis and type identification; reading cache structure information in the architecture characteristic data, and driving a file system to intelligently prefetch and reconstruct a storage layout of memory data based on the cache structure information; and continuously collecting performance index flow data when the system runs, performing real-time analysis on the performance index flow data by using a performance degradation model, generating a feedback control instruction according to an analysis result, and dynamically correcting the kernel parameter configuration of the first-stage system and the scheduling strategy of the second-stage process.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention discloses a node distribution method and system for a GPU (Graphics Processing Unit) use process in an NUMA (Non Uniform Memory Access) environment, and the method comprises the following steps: in a kernel mode, capturing an event that the process executes a new program and collecting meta-information of the process through an eBPF program mounted at a system call entry tracking point, and judging whether the process is a target GPU process or not based on the collected meta-information of the process; if the process is the target GPU process, transmitting meta-information of the process to a user mode, and if the process is not the target GPU process, ending and exiting; and for the meta-information transmitted to each target GPU process of the user mode, reading the meta-information of the target GPU process through the user mode daemon process, evaluating each node in the NUMA environment based on a preset node allocation rule, selecting an optimal NUMA node, and binding the target GPU process to a CPU of the optimal NUMA node for execution. The GPU computing efficiency and the resource utilization rate can be improved.

The embodiment of the application relates to the computer technical field, and provides a task execution log processing method and system and a computing device, the method is applied to the computing device carrying an operation and maintenance system, the method comprises the following steps: in response to that a task execution request is received by an execution engine unit, a callback event in a task execution process is monitored through a log processing plug-in; when the callback event is monitored, task execution data is recorded; the task execution data is encapsulated as structured log information; the structured log information is output in real time through a log output unit to replace output content of the log output unit. Based on the scheme, the computing device can embed the log processing plug-in in the operation and maintenance system, capture the callback event generated in the task execution process in real time, obtain the data in the task execution process as the log in the task running, so that the operation and maintenance system can realize the real-time structured output of the log without modifying the architecture, and blind areas of the operation and maintenance system in the task execution process are avoided.

The invention discloses a graph structure force guided dynamic spring effect acceleration method based on GPU parallel computing. The method comprises the following steps: dividing three independent GPU kernel functions; a resource allocation strategy is adopted under the Ada architecture, and execution configuration is generated; introducing a thread coarsening method to generate an optimized kernel execution result; generating a node position calculation result by using a shared memory privatization method and a reduce operator fusion method in combination with an improved KIFMM algorithm; in the iterative updating stage, an iterative updating result of the node position is obtained; performing cooling processing on the node position updating process by using a simulated annealing algorithm; the real-time visualization and analysis requirements are met, the calculation efficiency of large-scale graph data can be remarkably improved, the convergence time is shortened, and the method has the advantages of being high in calculation speed, high in convergence stability and wide in application range.

The invention relates to the technical field of computer compiling, and discloses a method and a device for simultaneously compiling multiple architectures, computer equipment and a storage medium. According to the method for simultaneously compiling the multiple architectures, the code files input by the user are processed through the user-defined linker, the multiple code files are analyzed, and therefore analysis operation in the compiling process in all the architectures can be advanced, and a unified intermediate file is generated. And continuing to compile the generated unified intermediate file in each architecture, and finally obtaining an executable file or a library file corresponding to each architecture. According to the embodiment of the invention, the analysis operation is advanced, and the unified intermediate file is generated, so that the analysis operation does not need to be executed for multiple times when compiling is continued under each framework, and the effects of shortening the compiling time and saving computing resources can be achieved.

The invention provides an instruction generation method and device, a computing system and computing equipment, and relates to the technical field of AI.In the method, cue words are input into a large language model to generate an instruction set related to a document fragment by utilizing the generation capacity of the large language model, then the instruction set is evaluated, and when an evaluation result does not meet a preset condition, the document fragment is generated. And the cue word is adjusted in time according to the evaluation result to determine a target instruction set related to the document fragment. Thus, the feedback relation between instruction generation and instruction evaluation is established, the cue word can be adjusted in time according to the instruction evaluation result in the process of efficiently generating the instruction set, namely, the strategy of generating the instruction set by the large language model is adjusted, and therefore the quality of the finally obtained instruction set is improved.

A method and system for threat detection and analysis is disclosed herein. The method includes monitoring at least one thread associated with at least one process on a computing system. The method further includes detecting specific system calls associated with at least one process at kernel level. The specific system calls are analyzed by applying a filter to the system calls sequence feature set associated with the specific system calls for detecting one or more events of interest. A full stack trace capture of at least one process is requested if the system calls sequence feature set is filtered and the one or more events of interest are detected. A first level monitoring is provided to the computing system, which includes processing and analyzing the captured full stack trace by a machine learning (ML) stack trace analyzer to generate a first verdict for threat detection and analysis.

The application discloses a method for obtaining a call stack when simulating running an application program and a computing device. The computing device comprises a first architecture processor and runs a first operating system. A second application program running a second operating system is simulated and run through a simulator. The method comprises the following steps: converting second architecture instructions of the compatibility layer and the second application program into first architecture instructions through the simulator and executing the first architecture instructions; in response to an interruption of the first architecture processor, debugging the simulator and obtaining an input extended command; executing the extended command to obtain current second architecture registers of a second architecture site from an interruption site of the first architecture processor; and obtaining a call stack of the second architecture instructions of the compatibility layer or the second application program based on the current second architecture registers. According to the technical scheme of the application, in the debugging process of the simulator, an error site of the second architecture instructions can be intuitively observed in the interruption site.

Disclosed herein is a computer implemented method of operating a computing environment to perform a live migration of a running process from a current computing node to an alternative computing node. The current computing node is configured for executing an application binary using a sandboxed runtime environment that comprises an application binary interface. The alternative computing node is configured for executing the application binary using the sandboxed runtime environment that comprises the application binary interface. The application binary interface has a node hardware independent instruction set. The method comprises: monitoring the running process on the current computing node to see if it meets a predetermined transfer criterion; adding the running process to a workload queue if the predetermined transfer criterion is detected; and migrating the running process from the current computing node to the alternative computing node. The migration of the running process comprises a transfer of stateful network connections.

A method for updating a computer program includes receiving a computer program hosted on and configured to be executed by a first computing system. The method includes analyzing the computer program to obtain characterization of a lineage, an architecture, and an operation of the computer program. The lineage includes relationships among elements of the computer program, the architecture includes a characteristic of the data source, the data target, and one or more processors configured to process the data contained in data records, and the operation includes processes that are executed to process the data from the data records. The method includes receiving a characterization of an update to be made to the computer program, in which when the computer program is modified according to the update, at least some of the modified computer program is configured to be hosted on and executed by a second computing system; and modifying the computer program to implement the update to generate the modified computer program.

A system (100) or method (500) for preventing or mitigating malicious processes in a computing environment having one or more processors (204) and memory (202) operatively coupled to the one or more processors can include computer instructions which when executed causes the one or more processors to perform certain operations. The operations can include intercepting (502) all file system input and output paths using a kernel driver (103), analyzing (504) for suspect behaviors in real time on data being processed through the input and output paths and data access patterns on a live system implemented in a kernel of an operating system for the computing environment, flagging (512) the data for any suspect behaviors, and preventing (514) further processing upon detection of the suspect behaviors.

The invention discloses an auto-regression and mask diffusion double-normal-form fusion language model hardware acceleration system based on an FPGA (Field Programmable Gate Array), and relates to the field of FPGA and machine learning. The invention provides a model core calculation process-oriented hardware acceleration architecture by aiming at a language model fusing double normal forms of an autoregression model and a mask diffusion model and adopting the characteristics of revising an attention mechanism and parallel generation of a KV cache. The method disclosed by the invention is implemented by taking an Eso-LMs (Esolic Language Models) model as an example. The system comprises a layer normalization and adaptive layer normalization modulation module, a QKV projection module, a rotation position coding application module, a KV cache management module, a multi-head attention calculation module, an output projection and residual connection module and a multi-layer perceptron module. By optimizing the calculation sequence and the data flow of each module in the model calculation process and adopting the pipeline parallel and resource reuse technology, the efficient reasoning acceleration of the language model fusing the autoregression and mask diffusion double normal forms on the FPGA platform is realized, and the model reasoning speed is obviously improved. According to the system, the advantage of FPGA customizable hardware acceleration is fully exerted, the utilization efficiency of hardware resources is improved, data pipeline blockage is eliminated, calculation delay and storage overhead are reduced by reconstructing the data flow direction and constructing a whole-process pipeline processing architecture, and the system is suitable for the deployment requirement of an edge calculation scene.

An efficient multi-core processor is provided, with processor instructions and an operating method associated with lock competition of a shared computing resource. A lock-application instruction is provided. Accordingly, the different processes executed by the different central processing unit (CPU) cores stand in a queue for right-of-access to the shared computing resources. The execution of the lock-application instruction is accompanied by the monitoring of a competition-level indicator. Based on the competition-level indicator, the lock of the shared computing resource is switched from a primitive lock mode that follows the first-in and first-out rule, to a Non-Uniform Memory Access (NUMA) lock mode.

The invention discloses a process-level power consumption analysis method and device, electronic equipment and a storage medium, and relates to the technical field of computers.According to the process-level power consumption analysis method and device, due to the fact that an event-driven monitoring mechanism deployed in an operating system kernel is adopted to achieve accurate capture and time metering of process execution events, the process-level power consumption analysis efficiency is improved; therefore, delay and sampling omission caused by a polling mechanism are avoided, extra overhead caused by frequent system calling is remarkably reduced, and therefore the technical problems that an existing process-level power consumption monitoring method is poor in real-time performance and large in data updating delay, and short-life-cycle processes are omitted in a sampling interval can be solved. The technical effects of high real-time performance and high-precision monitoring of process energy consumption and meeting of the requirements of edge computing and other scenes for refined management of system energy efficiency are achieved.

The application belongs to the technical field of computer memory management and heterogeneous computing scheduling, and discloses a KV cache anti-jitter asynchronous offloading scheduling method and system for large language model inference, which performs semantic isolation and real attention score on the key-value cache on the basis of the block type KV Cache management structure, selects recoverable redundant physical blocks based on the score results, acquires a basic pressure signal, establishes an I / O jitter quantization model based on a sliding time window, and calculates the recent average bus jitter rate of the system in real time; when the safe threshold is broken and the crisis state is entered, the candidate pool with decreasing priority is extracted to perform asynchronous offloading, and the maximum active concurrency limit is reduced; when the danger is removed, the number of concurrent is smoothly increased. Through the logical mapping update and physical block logout mechanism, the application reduces the underlying data handling in the redundant block recycling process, realizes block-level memory recycling, and guarantees the stability of the throughput; through high-precision hot and cold isolation, the offloading loss is minimized, and the OOM robustness is improved.

The application discloses a WebAssembly application hot migration runtime model method for a serverless scene, relates to the technical field of cloud computing and edge computing, and designs a WASM runtime mechanism supporting seamless hot migration across architectures, including designing a unified compilation model to realize unified memory space layout of compilation products of different architectures; and proposing a software-implemented, lightweight dirty page tracking memory migration strategy, which can avoid the burden of process-level migration and maintain the lightweight characteristics of WASM.

The execution of the instructions includes obtaining the software objects and loading the instructions into memory, and storing a workload type attribute for each software object. The execution includes deploying first hardware instructions during runtime to trigger operations of a firmware process to sample instructions from a set of instructions of one or more software objects executed by one or more processors of the computing system at each of a plurality of timed preconfigured intervals. The operations include deploying second hardware instructions to obtain the samples from the firmware process and store them in memory. The operations include generating execution parameters associated with each sample based on analyzing the stored samples. The operations include determining access to a software library in the computing system by the workload type attribute. The operations automatically implement actions related to at least one software object in the computing system.

Execution of an instruction includes obtaining software objects and loading instructions into a memory and storing the workload type attribute for each software object. The execution includes operations that during runtime, deploy a first hardware instruction to trigger a firmware process to sample, at each interval of timed pre-configured intervals, instructions from the sets of instructions of the one or more software objects being executed during the interval by one or more processors of the computing system. The operations include deploying a second hardware instruction to obtain and store samples from the firmware process in the memory. The operations include generating, based on analyzing the stored samples, execution parameters associated with each sample. The operations include determining accesses to the software libraries in the computing system, by workload type attribute. The operations automatically implement an action related to at least one software object in the computing system.

Systems, methods, and machine-readable media are disclosed for enabling high-performance programming via a composite programming language that gives programmers complete control over the compilation process. The composite programs include two language levels: an object program level (source code), and a metaprogram level that describes how a compiler should be customized in order to optimize the source code for a target hardware environment. When an augmented compiler receives a composite program, it recognizes the metaprogram and implements the one or more parameters specified within the composite program to optimize the compiler for a given target. Once the augmented compiler has been, it proceeds with compiling the source code included in the composite program. The compiled code is then output as machine language and may be executed by one or more computing systems.

The present disclosure relates to reusable barriers for synchronization between multiple processes. In one aspect, a system and method for facilitating synchronization between processes is provided. During operation, the system can execute multiple processes in parallel on one or more computing nodes. In response to a first process calling a barrier function, the system can suspend execution of the first process, and in response to determining that the first process has gained access to a variable shared by at least a subset of the multiple processes, the system can update the shared variable. The system can release the shared variable to a second process in the subset to update the shared variable when the second process calls the barrier function, and determine whether all processes in the subset have updated the shared variable. In response to the shared variable having been updated by all processes in the subset, the system can resume execution of all processes in the subset.

The invention provides a runtime program optimization method and device oriented to pipeline parallelism, and the method comprises the steps: recognizing a time window in a heterogeneous parallel computing process, the time window being an idle time period generated between accelerator equipment and a host processor due to task dependence or data synchronization; within the time window, collecting runtime information in a computing process from an accelerator device; dynamically selecting a compilation optimization strategy according to the characteristics of the time window and the runtime information; and based on the selected compilation optimization strategy, executing compilation optimization in the time window and generating an optimization code. According to the method, the idle time window in the calculation process can be effectively identified and utilized, and real-time performance optimization is achieved.

In some embodiments, the method may be carried out by the processor of a computing device. The method includes generating a non-executable code template containing code that defines a set of behaviors. Additionally, the method includes accessing data relating to a particular project. Furthermore, the method includes determining a set of project variables and a set of project logic relating to a particular project. Furthermore, the method includes generating executable code by integrating the set of project variables and the set of project logic into a non-executable code template. Moreover, the method includes compiling the executable code and producing results by executing the compiled executable code.

The application provides a script program credibility measurement method and system for an interpretive language, and is used in the technical field of network security. The method comprises the following steps: scanning and traversing script program files in a credibility measurement terminal to obtain a list of expected measurement values; in the process of normal operation of the credibility measurement terminal, for two execution modes of command line parameter execution and runtime dynamic loading, the dynamic hook technology is used to intercept before the execution of the script program, the content of the script program is obtained, and the current measurement value is calculated; the current measurement value is compared with the expected measurement value, and the execution of the script program is blocked or allowed according to the comparison result, so that the credibility measurement of the script program is realized without modifying system files and compiler program files. The application can solve the problem that malicious script programs are difficult to be detected and intercepted, and improve the security of the trusted computing environment.

Processes operating in a computing system are tracked. The tracking data includes or identified child processes, parent processes, and / or files associated with operation of the processes. When a process is determined to be a malware process, protective operations are performed. Protective operations may include removing or purging the malware process and all processes / files associated with the malware process in the tracking data. An infected snapshot may also be generated such that characteristics, operating procedures, and other aspects of the malware can be determined by recovering the infected snapshot to a sandbox environment and allowing the malware to execute therein.

The embodiment of the invention provides a source code compiling method, a compiler and computing equipment. The method comprises the steps of obtaining an initial intermediate representation of a source code; generating a target intermediate representation based on the initial intermediate representation; wherein the target intermediate representation indicates a storage address of the target structure body in a shared storage space of the computing device based on the target offset; the target structural body is a structural body written into the shared storage space in a program running stage; the target offset is an offset between a storage address of the target structural body in the shared storage space and a preset address of the shared storage space; the shared storage space is a storage space commonly accessed by a plurality of processes; and compiling the target intermediate representation to obtain a compiled running program. According to the scheme, a plurality of processes can operate the same variable in the shared area.

The embodiment of the application provides a compiling processing method and device, equipment and medium, and relates to the technical field of data processing. The original to-be-compiled file and original tool configuration information from different front-end construction tools are respectively converted into standard file objects and standard configuration information, so that the compiling process is completely separated from the running environment of the specific front-end construction tool, thereby saving the computing resources. Moreover, when the core syntax or core algorithm needs to be upgraded, only one place of the compiling core needs to be modified to complete the upgrade, thereby avoiding the step of synchronously modifying the code in multiple different compiling plug-ins, and thus avoiding the vulnerability of different versions.

Embodiments describe a data synchronization mechanism, focusing on efficient management of a circular buffer between producer and consumer processes. In one embodiment, a method uses a round-robin technique to facilitate parallel processing without requiring locking mechanisms, ensuring continuous data flow and real-time responsiveness. Furthermore, the method uses a pinning technique to record the state of the buffer before a round is converted to accurately determine buffer fullness, without ambiguity even if the producer and consumer pointers coincide. Additionally, a reset technique enables the system to mitigate loss of production entries by allowing the producer to overwrite outdated data when the buffer is full while the consumer lags behind. The mechanism is hardware-agnostic, operating system-agnostic, and can be implemented across a variety of programming languages, making it highly adaptable for a wide range of applications in computing systems.

In one embodiment, a method for automatic construction of attack graphs using large language models includes sending, by a computing system comprising one or more processors configured to execute one or more processes, vulnerability information to at least one large language model in order to extract structured information and building, by the computing system comprising the one or more processors configured to execute the one or more processes, a natural language query based on the structured information. The method further comprises sending, by the computing system comprising the one or more processors configured to execute the one or more processes, the natural language query to the at least one large language model to generate at least a portion of an attack graph from the vulnerability information.