40 results about "Process migration" patented technology

The invention discloses a task load balanced distribution system and method based on a node resource state, and relates to the technical field of distributed computing, and the method comprises the steps: collecting and associating multi-dimensional node resource data and dependency relationship data between tasks; establishing a virtual synaptic connection for each pair of tasks with data interaction, and constructing a task-dependent neural network model; the node resource state is monitored in real time, and the synaptic connection strength is adjusted; dynamically generating an optimal task allocation strategy; when the node resource saturation is continuously too high or the task execution efficiency is obviously reduced, starting a task migration process; and in the migration process, a synaptic cache region is created in the intermediate node, interaction data is cached, a dependency task node mapping relation is updated, data is synchronized, and the collaboration efficiency is verified. According to the method, CPU and GPU resource states and task dependency are considered at the same time, accurate matching and cooperative scheduling are achieved, overload or idling of a single resource is avoided, and the resource utilization rate is increased.

A process migration method includes a source host that copies a memory page of the to-be-migrated process to storage space of a first component of the source host in response to a received first migration indication; the source host sends the memory page of the to-be-migrated process to the destination host via a remote access system of the first component; and the destination host restores the to-be-migrated process based on the received memory page of the to-be-migrated process, to implement live migration of the to-be-migrated process. The remote access system is configured to perform data access on a remote host.

The embodiment of the invention provides a method, equipment and device for chip design, a medium and a program product, and relates to the field of chip design tools. The method includes determining at least one confinement circuit structure among a plurality of devices designed for a chip of a first process. Dimensions of a set of devices in each of the at least one confinement circuit structure have a dimensional constraint between the dimensions of the set of devices in each of the at least one confinement circuit structure. The method further includes determining device parameter values of the plurality of devices under a second process different from the first process based on the size constraint; and determining that the chip design for the second process satisfies a circuit performance condition by the device parameter value. The method further includes migrating the chip design from the first process to the second process based on determining that the circuit performance condition is satisfied. In this way, by using the size constraint contained in the constraint circuit structure in the chip design of the first process, the device parameter optimization process under the second process can be accelerated, and thus the process migration efficiency is improved.

The invention provides a process GPU-oriented real-time fault tolerance and task migration system and method, and relates to the technical field of distributed computation.The method comprises the steps that a training task state in a GPU video memory is captured, difference data is generated through an incremental difference algorithm, and the difference data is stored in a multi-level storage system after being subjected to lightweight compression; meanwhile, GPU node health indexes are collected in real time, node states are analyzed through a time sequence prediction model, and a migration process is triggered when fault risks are predicted or preemption early warning is received; during migration, the task is paused, a final increment check point is generated, check point data is quickly transmitted to a target healthy GPU node through an RDMA network, a complete context state is reconstructed, task execution is recovered, and real-time fault tolerance and seamless migration of the GPU task are achieved. According to the method, the continuous operation reliability and the resource utilization efficiency of the GPU cluster in the long-time training task are improved.

The invention provides a source database storage process migration method and device, electronic equipment and a storage medium, and the method comprises the steps: carrying out the grammar analysis of an original storage process in a source database, and generating a corresponding abstract syntax tree; based on a preset rewriting rule set, performing semantic equivalent transformation on the flow control syntax structure in the abstract syntax tree to generate a transformed abstract syntax tree; and generating a target script in a target execution environment from the converted abstract syntax tree, executing the target script in a script running engine, dynamically generating a standard SQL statement corresponding to the business logic defined by the original storage process, and submitting the standard SQL statement to one or more target data platforms for execution. And the business logic of the original storage process is reproduced. By introducing the target script as the intermediate execution layer, the flexibility of the migration scheme is greatly improved, so that the migration scheme is suitable for various big data platforms without the native storage process capability.

The invention provides an AI-based multi-node rapid disaster recovery switching method and system, and the method comprises the steps: obtaining multi-dimensional monitoring indexes of the CPU usage rate, the memory occupancy rate, the network IO, the disk IO, the application response time and the error rate of each node, and constructing a time sequence feature matrix; extracting space correlation features among nodes by using a graph convolutional network, extracting time sequence features through a long-short-term memory network, constructing a deep space-time graph neural network to identify a fault precursor, and predicting a node fault 30-120 seconds in advance; generating a node health score based on a node fault prediction result and capacity estimation, executing a target node optimization algorithm, and selecting an optimal disaster recovery backup node; the method comprises the following steps: constructing a hot backup by adopting a CRI U-based lightweight process migration technology, and generating a check point and an incremental snapshot of a source container; and automatic disaster recovery switching is executed before the node fails, the service flow is redirected, and the service is ensured not to be interrupted. According to the method, the disaster recovery switching time can be shortened to a millisecond level, and the system availability is remarkably improved.

The invention discloses an inter-host process migration method and system, computer equipment and a medium. The inter-host process migration method comprises the steps of obtaining a memory snapshot, file descriptor information, network state information and register state information of a target process in a source host; determining memory mapping information based on the memory snapshot; sending the memory mapping information, the file descriptor information, the network state information and the register state information to a target host; and performing target process reconstruction in the target host by utilizing the memory mapping information, the file descriptor information, the network state information and the register state information. According to the scheme provided by the invention, the memory copying and recovery of the running process can be realized, the resource continuity and the migration reliability are ensured by combining the file descriptor information, the network state information and the register state information, and the method is suitable for dynamic load balancing and fault recovery scenes in cloud computing and distributed systems.

The invention provides a distributed performance test method and system based on dynamic load prediction, and the method comprises the steps: periodically collecting the resource utilization data of a current slave node as the data of a current time point, and predicting the resource utilization data of a next time point; judging whether the resource utilization data at the next time point is abnormal or not based on a dynamic threshold verification algorithm, and starting a process migration mechanism based on a priority migration strategy; a bidirectional buried point probe is deployed at the slave node and the tested system, a density clustering algorithm is adopted to analyze and cluster the associated flow and resource data, and an abnormal problem mode is identified according to a clustering result; and displaying the relationship between the pressure request quantity of each test interface and the resource index as well as the abnormal problem mode in real time, and forming a full-link diagnosis view of pressure input-system response. According to the method, the response speed of the distributed performance test and the slave node resource scheduling efficiency are greatly improved, second-level time alignment is carried out on the flow data and the resource data, and bottom layer data support is provided for upstream evaluation analysis.

The invention relates to the technical field of virtual machines, in particular to a virtual machine live migration protocol authentication and data protection method which comprises a migration end configuration process, a migrated end configuration process and a migration process. The migration end carries out a migration end configuration process to obtain strategy configuration data of the migration end; the migrated end carries out a migrated end configuration process to obtain strategy configuration data of the migrated end; based on the strategy configuration data of the migration end and the strategy configuration data of the migrated end, the migration end and the migrated end enter a migration process so as to carry out double-end protocol authentication of the migration end and the migrated end, and after the double-end protocol authentication is passed, the migration data is migrated from the migration end to the migrated end, so that the safety protection of the migration data is realized. And the data migration performance is improved.

The utility model relates to a memory and an electronic device, the memory comprises a memory chip and a logic chip, the memory chip and the logic chip are packaged by adopting a three-dimensional packaging technology, the memory further comprises an interface circuit, the interface circuit is used for realizing communication between the memory and an external system, and the interface circuit is used for realizing communication between the memory and the external system. The interface circuit is arranged on the storage chip. Compared with an implementation mode that an interface circuit is generally arranged in a logic chip in the prior art, the memory provided by the utility model has the advantages that the interface circuit is arranged in the memory chip, and the interface circuit is a standard memory interface, so that the design based on the memory chip does not need process migration; the design complexity and design difficulty caused by interface circuit process migration can be avoided, and the architecture iteration speed is greatly increased.

A migration method includes: downgrading, by a source node, a physical page in a local memory corresponding to a process to a physical page of a compute express link (CXL) memory pool having a first physical address; reconstructing, by a target node, a first virtual address space as a second virtual address space; determining, by the target node, a second physical address of the physical page in the CXL memory pool; and mapping, by the target node, the second physical address to the second virtual address space, wherein the CXL memory pool is shared by the source node and the target node, the first physical address is based on a physical address encoding rule of the source node, and the second physical address is based on a physical address encoding rule of the target node.

The invention discloses a process migration control method and device for flexible assembly task switching, and relates to the technical field of flexible assembly. The method comprises the following steps: acquiring original total data in a first process; taking the minimum sample loss function as an optimization target, and obtaining a distillation candidate subset from the original total data; the sample loss function is used for measuring the retention degree of the distillation candidate subset on the behavior distribution of the original total data; calculating a comprehensive score of each action in the distillation candidate subset through a distribution consistency score and an action border-crossing punishment, filtering out sample data with relatively large comprehensive scores of the actions in combination with a gating mechanism, and storing the sample data meeting the gating mechanism into a small-capacity buffer area; and finally, training the initial strategy network according to the sample data of the small-capacity buffer area and the observation data of the second process to obtain a new strategy network. The method can give consideration to both online speed and stability under the condition of limited resources.

The invention provides a parameter processing method and device.The method comprises the steps that a circuit topological structure and a target manufacturing process under an original manufacturing process are obtained, and the circuit topological structure comprises circuit devices and the connection relation between the circuit devices; the target manufacturing process comprises N process corners of the circuit topological structure, M standard indexes and P candidate parameters of the circuit device; determining N1 representative process corners according to the N process corners; according to the circuit topological structure, the N1 representative process corners, the M1 standard indexes and the P1 candidate parameters, determining a target device parameter, 0 lt, meeting the target manufacturing process, of the circuit topological structure; m1 < = M, 0lt; p1 < = P. According to the method provided by the invention, the design parameter tuning work of the analog circuit device during process migration can be automatically completed, and the chip design quality and efficiency are improved.

The invention discloses a process migration method and device of an embedded system. The method comprises the steps that real-time operation state parameter values corresponding to at least two CPU cores and a preset process migration threshold value are obtained; determining a to-be-migrated CPU core according to the real-time running state parameter value and a preset process migration threshold value; screening the CPU cores in the same processor cluster with the CPU core to be migrated from the at least two CPU cores to obtain candidate CPU cores; determining a target CPU core according to the real-time running state parameter value corresponding to the candidate CPU core and a preset process migration threshold value; obtaining a current process snapshot corresponding to a current process in the to-be-migrated CPU core and a target historical process snapshot, and determining a target incremental snapshot corresponding to the to-be-migrated CPU core according to the current process snapshot and the target historical process snapshot; and sending the target incremental snapshot to the target CPU core. According to the method and the device, the process migration efficiency in the multi-core embedded system is improved.

Apparatuses, systems, and techniques for testing processing units of a computing system are disclosed herein. A request to initiate a testing process for each of a set of processing units is received. A first processing unit includes a first virtual processor executing first operations. A second processing unit includes a second virtual processor executing second operations. Execution of the first operations is transferred from the first virtual processor to the second virtual processor. Execution of the testing process is initiated at the first processing unit while the second virtual processor executes the first and second operations. In response to a detection that the execution of the testing process is completed, execution of the first and second operations is transferred to the first virtual processor. Execution of the testing process is initiated at the second processing unit while the first virtual processor running executes the first and second operations.

The invention relates to online fault detection in safety critical systems using isolation and process migration. Apparatuses, systems, and techniques for testing a processing unit of a computing system are disclosed herein. A request to initiate a test procedure for each of a set of processing units is received. The first processing unit includes a first virtual processor that performs a first operation. The second processing unit includes a second virtual processor that performs a second operation. Execution of the first operation is transferred from the first virtual processor to the second virtual processor. When the second virtual processor performs the first operation and the second operation, execution of the test process is initiated at the first processing unit. In response to detecting that execution of the test process has been completed, execution of the first operation and the second operation is transferred to the first virtual processor. When the running first virtual processor performs the first operation and the second operation, execution of the test process is initiated at the second processing unit.

This document discloses devices, systems, and techniques for testing the processing units of a computer system. A request is received to initiate a test process for each set of processing units. A first processing unit contains a first virtual processor that performs first operations. A second processing unit contains a second virtual processor that performs second operations. The execution of the first operations is transferred from the first virtual processor to the second virtual processor. The execution of the test process is initiated at the first processing unit while the second virtual processor performs the first and second operations. Upon detection that the execution of the test process is complete, the execution of the first and second operations is transferred back to the first virtual processor.The execution of the test process is initiated on the second processing unit, while the first virtual processor performs the first and second operations.

The present invention proposes a front-end process migration optimization method and system for digital integrated circuits. By simulating a limited number of specific circuit device size parameters as training samples for a neural network, a model of key indicators versus circuit device size parameters is constructed, and the device size parameters are quickly designed based on the model to complete the front-end process migration under the new process. The model parameters are trained using a deep neural network method to obtain the relationship between the optimization target and the device size. Compared with the brute force exhaustive method, the optimization target model can be obtained in a very short time; then the geometric programming method is used to obtain the global optimal solution in the size parameter design space. The front-end process migration of customized digital integrated circuits can be completed in the shortest possible time.

The cross-process simulation integrated circuit behavior modeling method based on transfer learning and self-enhancement optimization belongs to the technical field of electronic design automation and artificial intelligence, and first, the circuit simulation data of a source process and a target process are subjected to feature engineering processing and alignment based on physical characteristics; a forward performance prediction model is constructed, a transfer learning strategy of source domain pre-training combined with target domain partial layer fine-tuning is adopted, and a mapping from circuit parameters to performance indicators is established; secondly, a reverse parameter backstepping model is constructed, and self-enhancement closed-loop optimization is performed, the forward model is used as a verifier to perform performance evaluation on the samples generated by the reverse model, high-confidence samples are selected to iteratively update the reverse model, and process rule hard constraints are introduced in the output layer to perform parameter boundary clipping; finally, the circuit design parameters meeting the requirements of the target process are output. The present application significantly improves the design efficiency and physical reliability of the simulation IP cross-process migration, and effectively solves the model generalization problem in the small sample scene.

The application discloses a CPU scheduling method and system for a hybrid memory architecture, and can be widely applied to the technical field of CPU processing. In the application, the CPU resource usage degree is periodically collected during the application of the hybrid architecture, the busy degree of each physical core under a NUMA node is analyzed according to the CPU resource usage degree, the task scheduling queue attribute of the busy core in the physical core is analyzed, and then the process migration strategy and the process scheduling strategy are executed according to the task scheduling queue attribute, so that the reasonable scheduling of the process can be realized, and the utilization rate of the CPU resource is improved.

The application discloses a Go language library migration method based on semantic dependency graph and complexity scheduling, and comprises the following steps: S1, source code is acquired, and a unified semantic dependency graph is generated; S2, a minimum migration unit is generated; S3, multi-dimensional complexity quantification and risk modeling calculation are carried out on each minimum migration unit, a risk score is generated, all minimum migration units are sorted according to the risk score from low to high, and a migration priority queue is constructed; S4, according to the migration priority queue, the migration unit with lower risk is preferentially executed, and a migration state is recorded; S5, a test verification process is carried out; and S6, migration scheduling is carried out. The application realizes automatic migration planning based on program analysis, graph theory structure and complexity scheduling algorithm, does not depend on model training or external knowledge enhancement mechanism, and has high engineering applicability.

The invention discloses a method and a device for designing a stateless ubiquitous operating system supporting a decoupling service. The device comprises a hardware layer, a macro-kernel base layer, a platform abstraction layer and a LibOS user process layer, by designing a decentralized process state, the state of a user process in a computer system is separated from a system kernel, and system service is decoupled into the user process to obtain a decoupled user process, so that the degree of dependence of the user process on a host system is reduced; a stateless cross-device migration method is designed, and the decoupled user processes are efficiently migrated on different heterogeneous hardware platforms, so that the system service has continuity; and realizing heterogeneous resource integration and resource optimization of a computer system through a dynamic service and resource management method of a hardware resource list for heterogeneous device collaboration and process seamless migration.

The invention provides a two-workshop distributed comprehensive scheduling method based on an improved bipartite graph. According to the method, an improved bipartite graph cyclic decomposition strategy is provided; secondly, establishing a multi-substring weight calculation scheme based on substring structure characteristics generated by decomposition; and finally, proposing a workshop virtual-real allocation strategy, and realizing dual optimization of shorter processing time and higher equipment efficiency by pre-allocating a process set to a virtual equipment simulation scheduling process and disassembling a substring to dynamically adjust a resource allocation scheme. The method provided by the invention effectively solves the problem of heavy transverse and light longitudinal or heavy longitudinal and light transverse in a traditional scheduling method, avoids a process migration phenomenon and additional time consumption caused by the process migration phenomenon, and improves the scheduling efficiency and equipment utilization level of symmetric two-workshop distributed scheduling; and a solution with theoretical value and practical significance is provided for the field of complex product production scheduling.

The invention provides a layout processing method and device, electronic equipment and a storage medium, and is applied to the technical field of computers. According to the method, after a source layout of a target module designed based on a source process is obtained, target parameter calibration is conducted on the source layout, so that the source layout is matched with a design rule of the target process; according to the method, source layers of a source layout are mapped to target layers corresponding to the same function in a target process, the target layers are calibrated according to a DRC rule of the target process, and a target layout meeting a target process design rule is obtained. The target parameters of the source layout are calibrated, so that the source layout is matched with the design rule of the target process; in addition, layer mapping can be carried out based on the principle of the same function, the possibility of data errors caused by the layer function is reduced, DRC rule verification can be carried out after mapping, it is ensured that a large number of DRC violation problems do not occur in the migrated target layout, and the cross-process migration efficiency of the layout is improved.

The present invention discloses an industrial automation process export and reconstruction method and an electronic device, belonging to the technical field of software development. The method includes: obtaining process objects to be exported on a canvas and generating unique identifiers for the process objects; generating process configuration files, canvas resource files and process layout images for the process objects based on the unique identifiers; embedding the process configuration files and canvas resource files into the process layout images to form picture files containing metadata of the process objects. The industrial automation process export and reconstruction method and the electronic device provided by the present invention realize the integrated encapsulation of the process logic structure and the visual layout by embedding the process configuration files and canvas resource data into pictures. The picture files support import and automatic reconstruction, overcome the cumbersome traditional manual copying and pasting and the limitation of poor compatibility of dedicated plug-ins, and greatly simplify the process migration and sharing operations.

The invention provides a digital circuit design system, a digital circuit full-automatic design method and a related product, and the digital circuit design system converts a metal layer rule into a process parameter template represented by a coefficient of a process minimum line width unit through a process abstract interface module, so that the process migration cost is reduced. The full-automatic design method of the digital circuit can automatically start from the function description of the target digital circuit, the physical implementation result of the target digital circuit is obtained, the full-process automatic design of the chip is realized, and the design difficulty of the digital circuit is reduced.

The application proposes a two-machine distributed comprehensive scheduling method based on improved bipartite graph. The method proposes an improved bipartite graph cycle decomposition strategy; secondly, based on the sub-string structure characteristics generated by decomposition, a multi-sub-string weight calculation scheme is established; finally, a virtual and real distribution strategy of workshop is proposed, the scheduling process is simulated by pre-distributing the process set to the virtual device, the resource allocation scheme is dynamically adjusted by disassembling the sub-string, and the dual optimization of "shorter processing time and higher equipment efficiency" is realized. The method effectively solves the problem of heavy horizontal and light vertical or heavy vertical and light horizontal in the traditional scheduling method, avoids the process migration phenomenon and the additional time consumption caused thereby, improves the scheduling efficiency and equipment utilization level of the symmetric two-machine distributed scheduling, and provides a solution with theoretical value and practical significance for the field of complex product production scheduling.

The invention discloses a parameter prediction and process migration method for an analog circuit of an adaptive network, and the method comprises the steps: obtaining a network training data set based on the feature vector and target performance index data of the analog circuit, and enabling the network training data set to be divided into a deep network training data set and a shallow network training data set based on the distribution density; activation function data are adaptively acquired based on the target performance index data, the activation function data comprise a deep activation function and a shallow activation function, the deep activation function is used for an activation function of a deep network, and the shallow activation function is used for an activation function of a shallow network; based on the network training data set and the activation function data, respectively updating and verifying hyper-parameters of the deep network and the shallow network; and obtaining a prediction result based on the test data set. Not only are the problems of size-performance prediction and cross-process migration of the analog circuit solved, but also the method has wide universality and expansibility.

The application discloses a process migration method, which is executed in a computing device and comprises the following steps: when a first process wakes up a second process, it is determined whether a CPU where the first process is located is in an idle state, the first process is a process for executing a wake-up flow, and the second process is a process woken up by the first process; if the CPU where the first process is located is not in the idle state, the second process is migrated into a target CPU of the computing device based on affinity between the first process and the second process. The process migration method improves the performance of program running.

The invention provides a heterogeneous database storage process migration method based on dynamic rule learning. According to the heterogeneous database storage process migration method based on dynamic rule learning, the expansibility and accuracy of migration from an Oracle storage process to a GaussDB function are effectively improved, automatic processing of a complex migration scene and traceability of a modification record are achieved by dynamically learning a user-defined rule and combining a text analysis technology, and the migration efficiency of the Oracle storage process to the GaussDB function is improved. And the manual intervention cost is obviously reduced.