9 results about "Physics processing unit" patented technology

The embodiment of the invention provides a prefetching parameter configuration and cache prefetching method, a physical machine and a processor. In the embodiment of the invention, the physical processor can perform hardware prefetching operation in the running process of the virtualization instance. Furthermore, the virtualization manager applies for a prefetch register access permission from a firmware program of the prefetch register, and the prefetch register is accessed under the condition that the prefetch register access permission is successfully applied; the operation of configuring the prefetching strategy parameter by the virtualization instance is perceived, and the prefetching strategy parameter is configured to a prefetching register in a physical processor to which the virtualization instance is scheduled instead of the virtualization instance, so that the configuration capability of the prefetching register is transmitted to the virtualization instance through a bottom layer virtualization technology; therefore, the prefetching strategy can be flexibly and dynamically configured for different virtualization instances according to the scheduling condition of the virtualization instances, and the problem that the performance of a plurality of applications cannot be considered due to the fact that the prefetching strategy cannot be flexibly and dynamically configured in the prior art is solved.

The embodiment of the invention discloses a task processing method and device based on a virtual processor, a medium and equipment, and the method comprises the steps: generating an interrupt request signal by a virtual timer under the condition that a physical processor corresponding to a virtual machine is in a first mode; the physical processor obtains the interrupt request signal and injects virtual interrupt information corresponding to the interrupt request signal into a virtual processor corresponding to the virtual machine; the virtual processor responds to the virtual interrupt information and executes a processing task corresponding to the virtual interrupt information, and the virtual processor represents processor resources distributed for the virtual machine in the physical processor. According to the embodiment of the invention, the performance overhead generated by storing and recovering the context information of the system timer can be avoided or reduced.

Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.

The disclosed system may include a user device with (1) a first module, which performs a first functionality, and (2) a second module, which performs a second functionality, (3) a physical processor, and (4) physical memory including computer-executable instructions that cause the physical processor to (i) determine that a change in a range of frequency, being used by the first module, has resulted, or will result, in interference between the first module's changed range of frequency and a range of frequency being used by the second module, and (ii) in response to the determining that the change in the range of frequency has resulted in the interference, change the range of the frequency being used by the second module to a new range of frequency that does not interfere with the first module's changed range of frequency. Various other wearable devices, apparatuses, and methods of manufacturing are also disclosed.

The present invention provides a mutual simulation method between heterogeneous processors, including: setting the value of the MIDR_EL1 bit in the register HFGRTR_EL2 contained in the physical processor to 1 in the kernel space; using a hardware acceleration module to add the register MIDR_EL1 of the simulated virtual processor to the kernel space, and writing the value of the register MIDR_EL1 contained in the physical processor to be simulated; adding the model of the physical processor to be simulated in the virtualization management program, and transferring the value of the register MIDR_EL1 contained in the physical processor to be simulated to the simulated register MIDR_EL1 contained in the virtual processor added to the kernel space. The present invention realizes the shielding of differentiated hardware information in a heterogeneous scenario, realizes the mutual simulation between heterogeneous processors in the heterogeneous scenario and improves the user experience.

Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.

The disclosed system may include a user device with (1) a first module, which performs a first functionality, and (2) a second module, which performs a second functionality, (3) a physical processor, and (4) physical memory including computer-executable instructions that cause the physical processor to (i) determine that a change in a range of frequency, being used by the first module, has resulted, or will result, in interference between the first module's changed range of frequency and a range of frequency being used by the second module, and (ii) in response to the determining that the change in the range of frequency has resulted in the interference, change the range of the frequency being used by the second module to a new range of frequency that does not interfere with the first module's changed range of frequency. Various other wearable devices, apparatuses, and methods of manufacturing are also disclosed.

The disclosed computer-implemented method may include (1) transferring control of a display of a computing device from a high-power physical processor of the computing device to a low-power physical processor of the computing device, (2) animating, using the low-power physical processor, the display at a first frame rate during a first time period, (3) animating, using the low-power physical processor, the display at a second frame rate during a second time period, (4) transferring control of the display from the low-power physical processor to the high-power physical processor, and (5) animating, using the high-power physical processor, the display. Various other methods, systems, and computer-readable media are also disclosed.

Method, systems, and computer program products for managing a processor power management feature on behalf of a virtual machine (VM). A device may determine that a VM operating at a computer system possesses a power management entitlement. The device may identify an architectural power management feature available at a physical processor core of a processor system. The physical processor core is associated with a virtual processor core of the VM. Based on the VM possessing the power management entitlement, the device may present an interface to the VM. The interface exposes the architectural power management feature to the VM. The device may identify a request from the VM to modify a state of the architectural power management feature. Based on the request, the device may modify the state of the architectural power management feature at the physical processor core.