3 results about "Physics processing unit" patented technology

Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.

Interpretative execution is performed by a physical processor of a computing environment for a virtual processor executing on the physical processor. The performing interpretative execution includes obtaining an order code indicating an action to be taken for the virtual processor and accessing a shadow state description of the virtual processor to obtain an original state description origin. The original state description origin indicates the location of an original state description of the virtual processor, and the original state description includes state information of the virtual processor. An action is performed using an indicator of the state information of the virtual processor. The indicator is selected based on the order code, and the action is performed by the physical processor on behalf of the virtual processor.

Method, systems, and computer program products for managing a processor power management feature on behalf of a virtual machine (VM). A device may determine that a VM operating at a computer system possesses a power management entitlement. The device may identify an architectural power management feature available at a physical processor core of a processor system. The physical processor core is associated with a virtual processor core of the VM. Based on the VM possessing the power management entitlement, the device may present an interface to the VM. The interface exposes the architectural power management feature to the VM. The device may identify a request from the VM to modify a state of the architectural power management feature. Based on the request, the device may modify the state of the architectural power management feature at the physical processor core.