61 results about "Binary translation" patented technology

The invention discloses a context-aware-based gap containerization TLS compatible method, which comprises the following steps of: distinguishing a simple TLS variable and a complex TLS variable in a source gap system, and establishing a TLS variable source feature; the method comprises the following steps: constructing a dynamic telescopic TLS memory pool matched with a variable access permission in a target system, expanding a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and a memory pool address, and optimizing and constructing a clustering structure aligned with a CPU cache line for a hotspot variable to improve the access efficiency; tLS variable access tracks are recorded through a dynamic binary translation engine, TLS segment descriptors are updated, the descriptors are read during thread switching to recover TLS context and refresh cache to guarantee consistency, address and offset conversion is completed according to target system alignment requirements by combining source features and a bidirectional mapping table for TLS variables of nested structures, pointers and array types, and the TLS variables of the nesting structures, the pointers and the array types are aligned. And completing dynamic conversion execution of the source system application program in the target system.

The invention provides a binary translation system applied to an X86 program, which is used for translating a source program following X86 semantics into a target program following other semantics, and comprises a data acquisition module used for acquiring the source program; the disassembling module is used for dividing a source program into a plurality of basic blocks and analyzing subsequent basic blocks corresponding to each basic block; the backward data flow analysis module is used for sequentially analyzing each instruction in each basic block from back to front so as to obtain a target definition set and a target subsequent use set corresponding to each instruction in the source program; and the translation module is used for eliminating redundant instructions of high-order zero clearing or high-order retention of the general register generated in translation. According to the technical scheme, the register state of the general register corresponding to each instruction of the source program is analyzed through the backward data flow analysis module so as to eliminate redundant instructions generated in the translation process.

The invention provides a dynamic binary translation optimization method and system based on regional granularity. The method comprises the following steps: S1, initializing a program entry; s2, acquiring and analyzing an instruction; s3, performing cache query; s4, hot spot judgment; s5, performing interpretive execution; s6, initiating a compiling request; s7, compiling mode selection; s8, compiling and caching the code blocks; s9, skipping to a local code for execution; and S10, returning to the main cycle. According to the invention, the technical problems of limited optimization space, high context switching overhead and high code expansion rate are solved.

The invention relates to the technical field of code caching, and provides a dynamic binary translation caching method and system based on hotspot discovery, and the dynamic binary translation caching method comprises the following steps: S1, taking a virtual address of a client as a key value of a Hash conflict ring structure; s2, in a certain detection, if it is detected that the same translation block is hit for the second time according to the virtual address of the client and the program counter, and the number of hit translation blocks reaches a hit threshold value, triggering a hotspot transfer thread to update a hotspot counter corresponding to translation block information, pointing a head pointer of the hash bucket to the translation block information with the highest hotspot counter value; and S3, two groups of alternately used continuous memory spaces are adopted, translation codes of the old memory space are recovered through copy-on-write, new translation codes are written into the new memory space, and the translation codes of the old memory space are asynchronously migrated to the new memory space.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: carrying out binary translation on a first code block to obtain a first translated code block, and determining a target state tag corresponding to the first code block during translation; when an indirect jump instruction in the first translation code block is executed, querying a quick lookup table according to a jump target address of the indirect jump instruction; when the quick lookup table is not hit, querying a first hash table corresponding to the target state tag according to a jump target address of the indirect jump instruction; the first hash table is used for recording a pointer of the translation code block matched with the target state tag, and the pointer points to an entry address of the translation code block. According to the embodiment of the invention, the code block searching efficiency can be improved, so that the execution efficiency of the indirect jump instruction is improved, and the performance of the system-level binary translator is improved.

The embodiment of the invention provides an exception processing method and device, electronic equipment and a readable storage medium. If a target exception is triggered when a target platform executes a target instruction, a target exception signal is generated, and an exception processing function corresponding to the target platform is called; the target instruction is obtained by performing binary translation on a current instruction in the source platform; based on the exception handling function, determining an exception type corresponding to the target exception signal; and under the condition that the exception type is a specified type, correcting an instruction operation result corresponding to the target instruction, and continuing to execute a subsequent instruction of the target instruction. Therefore, when floating point exceptions occur, the target exception signal is generated on the target platform, and the exception handling function is called for checking and handling, and compared with the prior art, the method and the device have the advantages that by changing the triggering mode of floating point exception checking, the number of times of executing exception checking is reduced, the program running overhead is reduced, and the program running efficiency is improved. And meanwhile, the program running efficiency is improved.

The embodiment of the invention provides an address mapping method and device, electronic equipment and a readable storage medium, and the method comprises the steps: determining a target state tag corresponding to a physical address of a to-be-accessed client based on a state tag region in a virtual memory space of a host machine under the condition of binary translation of a source access instruction of the client; under the condition that the target state mark is matched with a target memory access operation indicated by the source memory access instruction, determining a host machine virtual mapping address corresponding to the to-be-accessed client physical address in a host machine virtual memory space based on a direct address mapping rule; and executing a target memory access operation on a target host machine physical address corresponding to the host machine virtual mapping address. Therefore, the host machine virtual mapping address corresponding to the physical address of the to-be-accessed client is directly determined through the direct address mapping rule, retrieval traversal is not needed, the overhead in the address mapping process can be reduced, the address conversion efficiency is improved, and meanwhile the number of times of interaction between the client and the host machine is reduced.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, in the process of performing binary translation on a binary file of a source platform, if a current instruction is a memory access instruction, based on corresponding target address information after performing binary translation on the current instruction, the memory access instruction is accessed to the source platform; determining a target access address corresponding to the target platform; based on the target memory access address, generating a binary translated target check instruction corresponding to the current instruction; executing the target checking instruction to perform address checking on the target memory access address, and executing a target memory access operation corresponding to the current instruction under the condition that the target memory access address does not belong to a preset address constraint range; the preset address constraint range comprises a memory area which does not allow the target check instruction to access in the target platform. On the premise of ensuring the binary translation performance, the security of the binary translation process and the security and isolation of the resource data in the target platform are improved.

The invention discloses a dynamic binary translation acceleration method and system, a medium and a product, and the method comprises the steps: analyzing an ELF file of a target program before executing the target program, and extracting an external dependency library and function symbol information thereof; combining function information in a function library to generate an ELF function symbol information file containing function names of all function symbols and meta information of the function names, and mapping the ELF function symbol information file into a memory; when external function search calling is carried out in the process of binary translation execution of a target program in the target architecture, hash retrieval is carried out on ELF function symbol information in the memory; and according to the retrieved function type, realizing pointer mapping from the function type to a corresponding wrapper function, and according to the retrieved packaging type, obtaining an address of a local function to be executed actually so as to realize actual calling and parameter returning of the external function. The invention aims to reduce the symbol analysis and package matching overhead in the dynamic translation initialization process and improve the starting efficiency and the overall operation performance.

The invention discloses an operating system containerized kernel compatibility method based on mixed binary translation, which comprises the following steps of: constructing a container kernel data structure feature library containing field access frequency through static source code analysis and dynamic runtime tracking, generating a unique identifier consisting of a structure name and a high-frequency field offset sequence for a target structure, and generating a container kernel data structure feature library containing field access frequency; establishing an association graph between the system call and the target field; in a host machine, a static translation service is adopted to decompile a binary code of a container application, instrumentation is performed on a high-frequency site and a low-frequency site respectively, and an intermediate operation code sequence containing an operation code, a field name and double-end offset is pre-generated for the high-frequency site and stored in a cache; during operation, a pre-translation result is preferentially loaded from the cache for a high-frequency site, the pre-translation result is processed by the dynamic translation engine if the pre-translation result is not hit, and the pre-translation result is processed by the dynamic translation engine as required for a low-frequency site, so that efficient conversion combining field-level static preprocessing and on-demand dynamic conversion is realized.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first code block is translated, if it is determined that a jump target has a cross-page condition, recording jump target cross-page information, the jump target cross-page information being used for indicating a cross-page type; executing a target link strategy on the first translation code block and the second translation code block according to the jump target cross-page information; the target link strategy is used for judging whether the direct jump instruction meets an optimization condition or not according to a cross-page type indicated by the jump target cross-page information; and if the optimization condition is met, establishing a direct jump link for the first translation code block and the second translation code block. According to the embodiment of the invention, on the basis of ensuring the correct execution, the optimizable condition when the target page is skipped is identified, the link optimization operation is further executed, the code block search operation in the program running process is reduced, and the program running efficiency is improved.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The invention discloses a method and device for optimizing basic block jumping in a binary translation super block and computing equipment. The method for optimizing the basic block jump in the binary translation super block comprises the following steps: constructing a basic block in the super block; obtaining the current basic block and starting translation; if a direct jump instruction is encountered, jumping to a target basic block, combining the current basic block and the target basic block into a new basic block, and continuing to translate; if an indirect jump instruction is encountered, the current basic block which is translated at present points to the scheduling basic block, and translation is ended; if a privilege or abnormal instruction is encountered, the basic block which is translated currently points to the scheduling basic block, and translation is ended; and if the counter in the corresponding basic block exceeds a set threshold value, the translation is ended, otherwise, the translation is continued. According to the method, the times of quitting the super block when the super block is translated can be reduced, so that the overall execution performance of the super block is improved.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

This invention discloses a method, apparatus, device, and medium for dynamic library mapping execution in binary translation, comprising: translating and executing the instructions of an x86 executable program; determining whether it is a dynamic library function call instruction; if it is a dynamic library function call instruction, parsing the call instruction to obtain the called function; using the called function as a lookup index key to query a pre-established dynamic library mapping allocator to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining the starting address of the RISC-V dynamic library in memory, and using the first value as an offset value to calculate the absolute address of the function in memory; determining the parameter address of the function based on the second value; performing calculations on the function using the parameter address and the absolute address, and returning the calculation result. This reduces the system overhead during the translation process.

The invention discloses a dynamic library mapping execution method and device in binary translation, equipment and a medium. The method comprises the steps that translation execution is conducted on an instruction of an X86 executable program, whether the instruction is a dynamic library function calling instruction or not is judged, and when the instruction is the dynamic library function calling instruction, the calling instruction is analyzed, and a called function is obtained; querying in a pre-established dynamic library mapping distributor by taking the called function as a query index key to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining a first address of the RISC-V dynamic library in the memory, and calculating to obtain an absolute address of the function in the memory by taking the first value as an offset value; determining a parameter address of the function according to the second value; and calculating the function by using the parameter address and the absolute address, and returning a calculation result. And the system overhead in the translation process is reduced.

The invention discloses an application program running method and device, electronic equipment and a storage medium, and the method comprises the steps: translating a code of an application program into a first instruction and / or a second instruction; the first instruction is based on a first instruction set architecture and a data model is the same as a data model of a code of the application program; the second instruction is obtained based on the first instruction set architecture and through binary translation; compiling the code of the first shared library into a third instruction; the first shared library is a shared library of an operating system of the electronic equipment, the third instruction is based on a first instruction set architecture, and a data model is the same as a data model of a code of the application program; and executing the first instruction and / or the second instruction, and executing the third instruction to run the application program. According to the method, the binary translation range of the application program is reduced, the resource occupation of instruction expansion and instruction translation is reduced, and the compatibility of the translated instruction is improved.

The present invention provides a dynamic binary translation method and apparatus based on neural network-assisted simulated annealing. The dynamic binary translation method includes: generating an optimization option for a running command; predicting an optimal optimization option value vector corresponding to the running command; using the optimal optimization option value vector as the starting input for a simulated annealing exploration task to explore the best optimization option for binary translation of the running command; and performing binary translation on the running command based on the best optimization option. Through a highly automated process, the present invention ensures seamless connection from data flow to control flow, automatically transfers data and collaborates among modules, avoids possible errors and delays caused by manual intervention, and improves the efficiency and stability of the optimization process. At the same time, it can automatically monitor and adjust parameters to ensure that the whole process has both wide-area exploration ability and can accurately converge in the later stage to achieve the optimization goal.

The present invention proposes an instruction translation method and device for dynamic binary translation. The instruction translation method first analyzes the differences between the source instruction set architecture and the target instruction set architecture to find a specific instruction sequence in the source instruction set architecture instructions, and then designs translation rules for the specific instruction sequence based on the characteristics of the target instruction set architecture. During dynamic binary translation, the specific instruction sequence in the source instruction set architecture binary file is scanned and translated using the translation rules of the present invention; otherwise, conventional translation methods are still used. The present invention translates the binary instructions of the source instruction set architecture according to customized translation rules, reducing the number of instructions of the translated target instruction set architecture, improving translation quality, and thus improving binary translation efficiency.

The invention provides a dynamic binary translation method and device based on neural network assisted simulated annealing. The dynamic binary translation method comprises the following steps: generating an optimization option of a running command; predicting an optimal optimization option value vector corresponding to the operation command; exploring an optimal optimization option for binary translation of a running command by taking the optimal optimization option value vector as initial input of simulated annealing exploration operation; and performing binary translation on the running command based on the optimal optimization option. According to the method, seamless connection from a data flow to a control flow is ensured through a highly automatic process, data are automatically transmitted among the modules, the modules work cooperatively, possible errors and delay caused by manual intervention are avoided, and the efficiency and stability of an optimization process are improved; meanwhile, parameters can be automatically monitored and adjusted, it is ensured that the whole process has the wide-area exploration capacity, and precise convergence can be achieved in the later period, so that the optimization target is achieved.

The embodiment of the present application provides a kind of instruction jump method, processor and electronic equipment, it is applied to binary translation system, and the binary translation system is used to translate source program in client into target program in host computer, and the method comprises: when the source program is translated into target program, obtain first jump instruction, the first jump instruction is the instruction of target program in the host computer, and the first jump instruction includes first operation code register identifier;The first jump instruction is executed, to record the running number and the number of times of missing of the first jump instruction in the table entry of corresponding jump refill table according to the first register identifier.The embodiment of the present application can provide jump tendency information about program running for binary translator, improve the running efficiency of binary translator, and additional hardware structure is not needed, which reduces the optimization cost and difficulty of binary translation.

The embodiment of the present invention provides a binary translation method, device, electronic device and program product, which relates to the field of computer technology. In the method, the target system information and / or historical operation file of the target program are obtained; the target program is the client program that the binary translator is running this time, the target system information is used to characterize the operating system adapted to the target program, and the historical operation file is used to record the historical operation results of the target program and the risk level information of the enabled historical optimization strategy. Based on the target system information and / or the historical operation file, the optimization strategy adapted to the target program is selected from the selected optimization strategies to obtain the target optimization strategy; the selected optimization strategy is the optimization strategy provided by the binary translator. The binary translator is configured to enable the target optimization strategy. In this way, the operation threshold can be lowered and the configuration efficiency can be improved.

The application relates to a QEMU-based floating point calculation optimization method, which comprises the following steps: obtaining an executable file of a target platform architecture; extracting a floating point calculation instruction in the executable file; parsing the floating point calculation instruction, reading an operand and an operation code; judging whether the operand and the operation code belong to a preset classification range; if the operand and the operation code belong to the preset classification range, selecting a floating point calculation mode according to the type of a local platform architecture to replace the floating point calculation instruction for floating point calculation; and if the operand and the operation code do not belong to the preset classification range, still adopting an ALU floating point calculation unit for floating point calculation. The application adopts a method of replacing a floating point calculation with a SIMD instruction, so as to improve the dynamic binary translation efficiency and simplify functions.

Embodiments of the present application provide a data processing method, device and equipment, readable storage medium and program product, the method comprises: obtaining the starting address of the data block to be translated; determining the starting address of the target data block based on the starting address of the data block to be translated, the target data block is the data block obtained by translating the data block to be translated; if it is determined that the target data block is not stored in the preset special memory based on the starting address of the target data block, the data block to be translated is translated into the target data block; the target data block is stored in the preset special memory, and the target data block is executed in the preset special memory; in this way, dynamic binary translation is performed based on the preset special memory, and the cache hit rate of the target data block in dynamic binary translation is improved.

The invention discloses an avionics system software simulation and bus excitation simulation method, and the method comprises the steps: employing a unified integrated development environment based on an Eclipse framework, and achieving the development, integration and deployment of multi-product software; the method comprises the following steps of: simulating original embedded target files of two heterogeneous platforms, namely a PowerPC architecture and an ARMv8-A architecture, by adopting a dynamic binary translation technology; a GPU para-virtualization and remote rendering method is adopted; driving-stage bus behavior simulation and single-port data excitation are carried out; and remote deployment, cloud management and continuous integration collaboration mechanism. The development efficiency is improved, a unified integration development environment and a simulation operation environment without hardware dependence are combined, the problems of hardware dependence and environment building repeatability are solved, rapid prototype design and one-key deployment are supported, and the development efficiency of display software is improved.

The application discloses a binary code translation service system based on a client / server architecture for a restricted system, which comprises a client and a server; the client and the server have the same architecture; the client refers to a terminal user equipment including a mobile phone and a tablet computer, and supports a dynamic binary translator; the server is deployed on a server, supports a static binary translator and a dynamic binary translator, and can execute multiple request tasks simultaneously; the binary translation is changed into a service provided to a user, and the implementation details of the back end are shielded from the user. The application further discloses a binary code translation service method realized by using the binary code translation service system. The method can execute a complex application program on the restricted system, improves the execution range of the application program, and saves the reconstruction cost of the application program on a new architecture.

The present invention discloses a multi-threaded dynamic binary translation method, apparatus, device and product, including: respectively establishing a cache table and a prediction table; the execution thread searches whether the address of the code block to be translated is recorded in the cache table, if it is recorded, the corresponding translated code block is executed, if it is not recorded, after the translation thread translates the code block to be translated, the execution thread executes it; further, according to preset conditions, the target code block recorded in the prediction table is selected for translation. The present invention can realize multi-threaded binary translation through the mutual cooperation of the execution thread and the translation thread; by means of the instantaneously updated cache table, it avoids repeated translation of the same code block and reduces the waste of computing resources; by means of the instantaneously updated prediction table, it can pre-translate the target code block with a high jump frequency, thereby improving the overall efficiency of binary translation, reducing the program startup time, and better meeting the requirements of different hardware platforms.

An embodiment of the present invention provides a binary translation method, a translator, an electronic device, and a readable storage medium. The method includes: when translating a direct jump instruction in a first code block, if it is determined that the jump target has a cross-page situation, then recording the jump target cross-page information, wherein the jump target cross-page information is used to indicate the cross-page type; according to the jump target cross-page information, executing a target link strategy for the first translation code block and the second translation code block; the target link strategy is used to determine whether the direct jump instruction meets the optimization condition based on the cross-page type indicated by the jump target cross-page information; if the optimization condition is met, then establishing a direct jump link between the first translation code block and the second translation code block. On the basis of ensuring correct execution, the embodiment of the present invention identifies the situation where the jump target crosses pages and can be optimized, further performs a link optimization operation, reduces the code block search operation during program execution, and improves program operation efficiency.

Systems and methods for performing binary translation include a system that is capable of translating binaries written for use in a source execution environment to binaries compatible with a target execution environment. Consistent with some embodiments, a binary translation system includes a system service and a runtime code module that exists in an application memory address space. The binary translation system translates object-level binaries corresponding to executables, linkers, libraries, and the like and stores the translation in a translation cache that is cryptographically secured to ensure that only a system having a specific key is able to access the translations. If the application or application binary has been modified since the translation was performed, the system service will ensure that the translation is removed from the cache, a new translation is performed, and all threads accessing that translation are updated to the new translation.