22 results about "Binary translation" patented technology

The invention discloses a context-aware-based gap containerization TLS compatible method, which comprises the following steps of: distinguishing a simple TLS variable and a complex TLS variable in a source gap system, and establishing a TLS variable source feature; the method comprises the following steps: constructing a dynamic telescopic TLS memory pool matched with a variable access permission in a target system, expanding a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and a memory pool address, and optimizing and constructing a clustering structure aligned with a CPU cache line for a hotspot variable to improve the access efficiency; tLS variable access tracks are recorded through a dynamic binary translation engine, TLS segment descriptors are updated, the descriptors are read during thread switching to recover TLS context and refresh cache to guarantee consistency, address and offset conversion is completed according to target system alignment requirements by combining source features and a bidirectional mapping table for TLS variables of nested structures, pointers and array types, and the TLS variables of the nesting structures, the pointers and the array types are aligned. And completing dynamic conversion execution of the source system application program in the target system.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

The invention discloses an application program running method and device, electronic equipment and a storage medium, and the method comprises the steps: translating a code of an application program into a first instruction and / or a second instruction; the first instruction is based on a first instruction set architecture and a data model is the same as a data model of a code of the application program; the second instruction is obtained based on the first instruction set architecture and through binary translation; compiling the code of the first shared library into a third instruction; the first shared library is a shared library of an operating system of the electronic equipment, the third instruction is based on a first instruction set architecture, and a data model is the same as a data model of a code of the application program; and executing the first instruction and / or the second instruction, and executing the third instruction to run the application program. According to the method, the binary translation range of the application program is reduced, the resource occupation of instruction expansion and instruction translation is reduced, and the compatibility of the translated instruction is improved.

The embodiment of the present application provides a kind of instruction jump method, processor and electronic equipment, it is applied to binary translation system, and the binary translation system is used to translate source program in client into target program in host computer, and the method comprises: when the source program is translated into target program, obtain first jump instruction, the first jump instruction is the instruction of target program in the host computer, and the first jump instruction includes first operation code register identifier;The first jump instruction is executed, to record the running number and the number of times of missing of the first jump instruction in the table entry of corresponding jump refill table according to the first register identifier.The embodiment of the present application can provide jump tendency information about program running for binary translator, improve the running efficiency of binary translator, and additional hardware structure is not needed, which reduces the optimization cost and difficulty of binary translation.

Embodiments of the present application provide a data processing method, device and equipment, readable storage medium and program product, the method comprises: obtaining the starting address of the data block to be translated; determining the starting address of the target data block based on the starting address of the data block to be translated, the target data block is the data block obtained by translating the data block to be translated; if it is determined that the target data block is not stored in the preset special memory based on the starting address of the target data block, the data block to be translated is translated into the target data block; the target data block is stored in the preset special memory, and the target data block is executed in the preset special memory; in this way, dynamic binary translation is performed based on the preset special memory, and the cache hit rate of the target data block in dynamic binary translation is improved.

The invention discloses an avionics system software simulation and bus excitation simulation method, and the method comprises the steps: employing a unified integrated development environment based on an Eclipse framework, and achieving the development, integration and deployment of multi-product software; the method comprises the following steps of: simulating original embedded target files of two heterogeneous platforms, namely a PowerPC architecture and an ARMv8-A architecture, by adopting a dynamic binary translation technology; a GPU para-virtualization and remote rendering method is adopted; driving-stage bus behavior simulation and single-port data excitation are carried out; and remote deployment, cloud management and continuous integration collaboration mechanism. The development efficiency is improved, a unified integration development environment and a simulation operation environment without hardware dependence are combined, the problems of hardware dependence and environment building repeatability are solved, rapid prototype design and one-key deployment are supported, and the development efficiency of display software is improved.

The application discloses a binary code translation service system based on a client / server architecture for a restricted system, which comprises a client and a server; the client and the server have the same architecture; the client refers to a terminal user equipment including a mobile phone and a tablet computer, and supports a dynamic binary translator; the server is deployed on a server, supports a static binary translator and a dynamic binary translator, and can execute multiple request tasks simultaneously; the binary translation is changed into a service provided to a user, and the implementation details of the back end are shielded from the user. The application further discloses a binary code translation service method realized by using the binary code translation service system. The method can execute a complex application program on the restricted system, improves the execution range of the application program, and saves the reconstruction cost of the application program on a new architecture.

The invention discloses a dynamic compilation queue optimization system and method based on reuse distance frequency. The system comprises the steps that a new stack temporarily stores code blocks which just reach a compilation heat threshold value and enter a compilation queue for the first time; the popularity information counter monitors and counts popularity information of each code block in real time; the priority stack calls a priority calculation engine to dynamically calculate and sort compilation priorities; the priority calculation engine dynamically calculates the priority of each code block in the priority stack and drives the priority stack to sort; the historical stack stores metadata information of code blocks which are not accessed within preset time in the priority stack and have priorities lower than a priority threshold; the method has the advantages that the scheduling efficiency of background compiling resources in the dynamic binary translation system is effectively improved, and the overall performance of the system is remarkably improved.

Embodiments of this application disclose an instruction translation method. The method includes: obtaining a return instruction of a function call instruction; obtaining a first address mapping result based on a second address indicated in the return instruction; storing the first address mapping result in a running stack space; and obtaining a first translation result of the return instruction, where the first translation result is a binary translation result of the return instruction, and the second translation result indicates to obtain, from a target location, an instruction indicated by the first address mapping result and execute the instruction. In this application, a running stack space of a source program is reused, thereby saving a storage space. In addition, an address of a return instruction does not need to be checked each time the return instruction is translated, thereby reducing overheads during translation and increasing program running efficiency.

The invention relates to the technical field of computer system architecture and cloud computing, and provides a one-cloud multi-core practical training system deployment adaptation platform in a credential environment. The platform comprises an instruction analysis module, a time sequence modeling module, a deployment engine, a self-adaptive execution module and a runtime regulation and control module. The method comprises the following steps: pre-scanning a target training system through an instruction analysis module to generate a high-risk instruction fingerprint database; establishing a standard time sequence model through a time sequence modeling module; when the system runs, the adaptive execution module adaptively selects a native execution strategy, a lightweight hot patch replacement execution strategy or an on-demand binary translation execution strategy according to the high-risk instruction fingerprint database so as to reduce the performance overhead; and the runtime regulation and control module monitors a key event time sequence index, compares the key event time sequence index with a standard time sequence model, sends a time sequence compensation command to the resource scheduler when detecting time sequence drift, and adjusts the resource quota of the target running container. According to the invention, the problems of poor compatibility, large performance loss and inconsistent operation time sequence of the practical training system under the heterogeneous CPU architecture are effectively solved.

This invention provides a dynamic binary translation method for stack-based floating-point architectures using rule-based translation, expanding the applicability of translation rules and improving the support of existing dynamic binary translation systems for stack-based floating-point instruction sets. The specific operation of this invention is as follows: During the translation rule matching process, the correctness of the translation rules is ensured by virtualizing stack registers, thereby generating the correct target architecture instruction sequence in the instantiation of translation rules; when generating target code, the characteristics of the floating-point register stack are considered, and register allocation constraints are used to allocate registers on the floating-point stack. By identifying the target register and performing pop operations, the source architecture registers and target architecture registers are synchronized, ultimately generating an efficient target architecture floating-point instruction sequence. Compared to software-simulated floating-point instruction translation methods, the method of this invention achieves efficient dynamic binary translation while ensuring correct translation.

The application belongs to the technical field of dynamic binary translation in computer architecture, and designs a system-level dynamic binary translation method based on translation rules, which proposes a new state saving and restoring mechanism to deal with conflicts in special scenarios of system-level dynamic binary translator. Specifically, it includes the following three steps: first, the instructions that will affect the system-level implementation are identified in the client instruction analysis stage, and are separated and identified for monitoring; then, in the translation rule application stage, the instructions related to system-level instruction problems, memory management problems and exception / interrupt problems are checked and processed; finally, two conditional code optimization schemes are proposed by analyzing the instruction flow information to improve the translation efficiency. The method realizes efficient dynamic binary translation while ensuring correct translation.

This specification provides a binary translation method. After obtaining the intermediate representation sequence corresponding to the basic block to be translated, a Pass optimization process is added to remove redundant instructions and reduce the performance loss of binary translation. Specifically, the optimization process may include: replacing the operand of the first intermediate representation with the target source operand of the first second intermediate representation preceding the first intermediate representation, so that the reference count of the second intermediate representation is zero. Based on the above optimization process, during the translation of multiple first instructions that read and write to the same destination register, the second instructions obtained based on multiple first intermediate representations can be processed continuously in the same register (e.g., a temporary register) without copying data to the destination register midway, which helps to reduce the number of second instructions obtained in the final translation, thereby reducing performance loss.

An electronic, digital data processor is adapted dynamically to develop for selected instructions received for execution in a pipelined execution unit a predetermined transform of the selected instructions. Depending on predetermined static or dynamic conditions that may exist in the pipelined execution unit, execution of the transform may be allowed or suppressed. The transform may be a fusion, a fracture or a binary transformation. A method is also disclosed for implementing this selective suppression of developed transforms.

The application discloses a context-aware-based hyperjump containerized TLS compatible method, which comprises the following steps: distinguishing simple TLS variables and complex TLS variables in a source hyperjump system, and establishing TLS variable source features; constructing a dynamic scalable TLS memory pool matching variable access authority in a target system, extending a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and memory pool address, and optimizing hot spot variable to construct a cluster structure body aligned with CPU cache lines to improve access efficiency; recording a TLS variable access track through a dynamic binary translation engine, updating a TLS segment descriptor, reading the descriptor to recover a TLS context when thread switching, refreshing a cache to guarantee consistency, and converting addresses and offsets according to target system alignment requirements in combination with source features and the bidirectional mapping table for TLS variables of nested structures, pointers and array types, so as to complete dynamic conversion and execution of a source system application in the target system.

The application discloses a hybrid binary translation-based operating system containerization kernel compatibility method, and the method is characterized in that: through static source code analysis and dynamic runtime tracking, a container kernel data structure feature library containing field access frequency is constructed, a unique identifier composed of a structure name and a high-frequency field offset sequence is generated for a target structure, and an association atlas between a system call and a target field is established; in a host computer, a static translation service is used to decompile container application binary code, high-frequency sites and low-frequency sites are respectively instrumented, and an intermediate operation code sequence containing an operation code, a field name and a double-end offset is pre-generated for the high-frequency sites and stored in a cache; in runtime, a pre-translation result is preferentially loaded from the cache for the high-frequency sites, and a dynamic translation engine is used to process the high-frequency sites when the pre-translation result is not hit, and the dynamic translation engine is used to process the low-frequency sites on demand, so that efficient conversion combining field-level static preprocessing and on-demand dynamic conversion is realized.

Embodiments of the present application provide a binary translation method, an electronic device, a readable storage medium and a program product. The method is applied to a translator. After translating a client instruction stream into a host instruction stream, a first type of instruction included in the host instruction stream is obtained. The first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction includes a stack pointer register and an immediate number operand. In a case where a number of the first type of instructions is M, the M first type of instructions are combined into N first type of instructions based on the source operand of each of the first type of instructions. The M is a positive integer greater than 1, and the N is a positive integer less than M. In this way, embodiments of the present application can process the host instruction after translation but before execution, combine the M first type of instructions into the N first type of instructions, reduce the number of the first type of instructions after translation, reduce the instruction inflation rate after translation, and thus improve the execution efficiency of the translator.

The application discloses a method for accelerating cross instruction set architecture simulation execution of a program, comprising the following steps: S1, in a compiling stage, generating an independent host side intermediate code file; meanwhile, generating a stub function same as a function signature in an original translation unit; S2, in a linking stage, generating a host code module corresponding to an original linking result file one by one according to a linking process of an original program and based on the host side target file, and generating module level data for each host code module; S3, summarizing all the host code modules to form a unified host program library; S4, based on the host program library, generating a stub module working at a guest side corresponding to the guest linking result one by one; S5, forwarding a guest side function call to a host side equivalent function execution, and returning to the guest side to continue execution after the execution is completed. The application bypasses inefficient instruction level binary translation, and realizes fundamental improvement of cross instruction set architecture simulation execution performance.

The embodiment of the present application provides a binary translation optimization method, a binary translator and an electronic device, wherein the method comprises: when a narrow write operation instruction is translated, updating a state mark of a first register in a preset state table according to a write bit width of the narrow write operation on the first register; the state mark is used for indicating whether high bits of a corresponding register need to be cleared and recording an effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to the read operation from the preset state table; if it is determined that a read bit width of the read operation is greater than the effective bit width indicated by the state mark of the second register, inserting a first clear instruction before a translation result of the read operation instruction; the first clear instruction is used for clearing specified high bits of the second register. The present application can simplify a target machine code sequence generated by translation, greatly reduce redundant operations, and improve execution efficiency of a translation system.

The invention discloses a method for accelerating program cross-instruction-set architecture simulation execution, which comprises the following steps of: S1, generating an independent host side intermediate code file in a compiling stage; meanwhile, generating a stub function which is the same as the function signature in an original translation unit; s2, in a linking stage, according to a linking process of an original program and based on the host side target file, generating host code modules in one-to-one correspondence with original linking result files, and generating module-level data for each host code module; s3, summarizing all the host code modules to form a unified host program library; s4, based on the host program library, generating stub modules which are in one-to-one correspondence with the object link results and work on the object side; and S5, forwarding the object side function call to the host side equivalent function for execution, and returning to the object side for continuous execution after the execution is finished. According to the method, low-efficiency instruction-level binary translation is bypassed, and the execution performance of cross-instruction-set architecture simulation is fundamentally improved.