85 results about "Binary translation" patented technology

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: calling a preset instruction if a current instruction is recognized as an indirect jump instruction; the instruction code of the preset instruction comprises a first operand and a second operand; the first operand points to the first register, and the second operand points to the second register; the target PC value is stored in the first register; the second register is used for storing a calculation result of the preset instruction; the preset instruction executes preset calculation logic to calculate a target index value corresponding to the target PC value in the hash table, and the target index value is written into a second register; the target index value is read from the second register, whether the target PC value hits the hash table or not is inquired through the target index value, and the next instruction is executed based on the inquiry result. According to the embodiment of the invention, the instruction translation number of the high-frequency instruction can be reduced, and the execution efficiency of the binary translator is improved.

The embodiment of the invention provides a binary translation method, a binary translator, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a thread mode of a client program when an indirect jump instruction in the client program is translated; generating a target search code sequence according to the thread mode; wherein different thread modes correspond to different target search code sequences; the target search code sequence is used for searching a target jump table based on a jump target address of the indirect jump instruction to obtain a cache initial address of a translated basic block corresponding to the jump target address; and if the target search code sequence is successfully searched, skipping to a cache initial address of the translated basic block corresponding to the skipping target address. According to the embodiment of the invention, the translation of the indirect jump instruction can be optimized, and the efficiency of searching the indirect jump table is improved, so that the running efficiency of a translated program is improved.

The invention discloses a context-aware-based gap containerization TLS compatible method, which comprises the following steps of: distinguishing a simple TLS variable and a complex TLS variable in a source gap system, and establishing a TLS variable source feature; the method comprises the following steps: constructing a dynamic telescopic TLS memory pool matched with a variable access permission in a target system, expanding a kernel state TLS segment descriptor, constructing a bidirectional mapping table of musl TLS offset and a memory pool address, and optimizing and constructing a clustering structure aligned with a CPU cache line for a hotspot variable to improve the access efficiency; tLS variable access tracks are recorded through a dynamic binary translation engine, TLS segment descriptors are updated, the descriptors are read during thread switching to recover TLS context and refresh cache to guarantee consistency, address and offset conversion is completed according to target system alignment requirements by combining source features and a bidirectional mapping table for TLS variables of nested structures, pointers and array types, and the TLS variables of the nesting structures, the pointers and the array types are aligned. And completing dynamic conversion execution of the source system application program in the target system.

The invention provides a binary translation system applied to an X86 program, which is used for translating a source program following X86 semantics into a target program following other semantics, and comprises a data acquisition module used for acquiring the source program; the disassembling module is used for dividing a source program into a plurality of basic blocks and analyzing subsequent basic blocks corresponding to each basic block; the backward data flow analysis module is used for sequentially analyzing each instruction in each basic block from back to front so as to obtain a target definition set and a target subsequent use set corresponding to each instruction in the source program; and the translation module is used for eliminating redundant instructions of high-order zero clearing or high-order retention of the general register generated in translation. According to the technical scheme, the register state of the general register corresponding to each instruction of the source program is analyzed through the backward data flow analysis module so as to eliminate redundant instructions generated in the translation process.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, and the method comprises the steps: if a translated current instruction is a memory access instruction, querying whether a reusable target cache register exists in distributed cache registers; the memory access address of the translated memory access instruction is stored in the allocated cache register; the memory access address in the reusable target cache register is the same as the memory access address of the current instruction in high order; if the reusable target cache register exists, obtaining a target difference value; the target difference value is a difference value between a memory access address of the current instruction and a memory access address in the target cache register; and translating the current instruction into a target instruction according to the target difference value and the target cache register. According to the embodiment of the invention, the number of translated instructions can be reduced, the execution efficiency of the translator is improved, and the program running speed of the translator is improved.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first basic block is translated, identifying whether a second basic block to which the direct jump instruction is to jump crosses pages or not; if it is determined that the second basic block crosses pages, a target instruction sequence is inserted in front of an unoptimized instruction sequence translated by the direct jump instruction, the target instruction sequence is used for detecting whether the direct jump instruction meets an optimization condition or not, and jumping is conducted through the link instruction sequence under the condition that the direct jump instruction is detected to meet the optimization condition; the optimization condition comprises that the virtual and real address mapping relation of the second basic block is not changed; the link instruction sequence is used for skipping to an initial address of the translated basic block corresponding to the second basic block in the code cache. According to the embodiment of the invention, the execution of the direct jump instruction is optimized under the condition that the optimization condition is satisfied, so that the program running efficiency can be improved.

The invention provides a dynamic binary translation optimization method and system based on regional granularity. The method comprises the following steps: S1, initializing a program entry; s2, acquiring and analyzing an instruction; s3, performing cache query; s4, hot spot judgment; s5, performing interpretive execution; s6, initiating a compiling request; s7, compiling mode selection; s8, compiling and caching the code blocks; s9, skipping to a local code for execution; and S10, returning to the main cycle. According to the invention, the technical problems of limited optimization space, high context switching overhead and high code expansion rate are solved.

The invention relates to the technical field of code caching, and provides a dynamic binary translation caching method and system based on hotspot discovery, and the dynamic binary translation caching method comprises the following steps: S1, taking a virtual address of a client as a key value of a Hash conflict ring structure; s2, in a certain detection, if it is detected that the same translation block is hit for the second time according to the virtual address of the client and the program counter, and the number of hit translation blocks reaches a hit threshold value, triggering a hotspot transfer thread to update a hotspot counter corresponding to translation block information, pointing a head pointer of the hash bucket to the translation block information with the highest hotspot counter value; and S3, two groups of alternately used continuous memory spaces are adopted, translation codes of the old memory space are recovered through copy-on-write, new translation codes are written into the new memory space, and the translation codes of the old memory space are asynchronously migrated to the new memory space.

A computing device receives an application start request for an application through a dispatching service. The computing device determines whether the application uses a first instruction set architecture (ISA) or a second ISA using the dispatching service. The computing device determines whether the application is compute-bound or non-compute-bound in response to determining that the application uses the second ISA. The computing device performs binary translation to convert instructions based on the second ISA from the application to instructions based on the first ISA in response to determining that the application is compute-bound. The computing device executes the instructions based on the first ISA on one or more cores supporting the first ISA.

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps of obtaining a translation result of each basic block from a cache of a translator; when an instruction in the translation result is executed, if it is determined that the currently executed instruction is a target instruction with memory access alignment abnormity, remapping is performed according to a first memory access address included in the target instruction, a second memory access address is generated, and a memory area corresponding to the first memory access address is configured to be inaccessible; and executing memory access operation aiming at the second memory access address to access data of the second memory access address. The problem that in the prior art, execution of all other threads is stopped unconditionally, and consequently the execution efficiency of source program instruction translation is affected can be solved.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: carrying out binary translation on a first code block to obtain a first translated code block, and determining a target state tag corresponding to the first code block during translation; when an indirect jump instruction in the first translation code block is executed, querying a quick lookup table according to a jump target address of the indirect jump instruction; when the quick lookup table is not hit, querying a first hash table corresponding to the target state tag according to a jump target address of the indirect jump instruction; the first hash table is used for recording a pointer of the translation code block matched with the target state tag, and the pointer points to an entry address of the translation code block. According to the embodiment of the invention, the code block searching efficiency can be improved, so that the execution efficiency of the indirect jump instruction is improved, and the performance of the system-level binary translator is improved.

The embodiment of the invention provides an exception processing method and device, electronic equipment and a readable storage medium. If a target exception is triggered when a target platform executes a target instruction, a target exception signal is generated, and an exception processing function corresponding to the target platform is called; the target instruction is obtained by performing binary translation on a current instruction in the source platform; based on the exception handling function, determining an exception type corresponding to the target exception signal; and under the condition that the exception type is a specified type, correcting an instruction operation result corresponding to the target instruction, and continuing to execute a subsequent instruction of the target instruction. Therefore, when floating point exceptions occur, the target exception signal is generated on the target platform, and the exception handling function is called for checking and handling, and compared with the prior art, the method and the device have the advantages that by changing the triggering mode of floating point exception checking, the number of times of executing exception checking is reduced, the program running overhead is reduced, and the program running efficiency is improved. And meanwhile, the program running efficiency is improved.

The embodiment of the invention provides an address mapping method and device, electronic equipment and a readable storage medium, and the method comprises the steps: determining a target state tag corresponding to a physical address of a to-be-accessed client based on a state tag region in a virtual memory space of a host machine under the condition of binary translation of a source access instruction of the client; under the condition that the target state mark is matched with a target memory access operation indicated by the source memory access instruction, determining a host machine virtual mapping address corresponding to the to-be-accessed client physical address in a host machine virtual memory space based on a direct address mapping rule; and executing a target memory access operation on a target host machine physical address corresponding to the host machine virtual mapping address. Therefore, the host machine virtual mapping address corresponding to the physical address of the to-be-accessed client is directly determined through the direct address mapping rule, retrieval traversal is not needed, the overhead in the address mapping process can be reduced, the address conversion efficiency is improved, and meanwhile the number of times of interaction between the client and the host machine is reduced.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, in the process of performing binary translation on a binary file of a source platform, if a current instruction is a memory access instruction, based on corresponding target address information after performing binary translation on the current instruction, the memory access instruction is accessed to the source platform; determining a target access address corresponding to the target platform; based on the target memory access address, generating a binary translated target check instruction corresponding to the current instruction; executing the target checking instruction to perform address checking on the target memory access address, and executing a target memory access operation corresponding to the current instruction under the condition that the target memory access address does not belong to a preset address constraint range; the preset address constraint range comprises a memory area which does not allow the target check instruction to access in the target platform. On the premise of ensuring the binary translation performance, the security of the binary translation process and the security and isolation of the resource data in the target platform are improved.

The invention discloses a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the steps that a translation result of each basic block is obtained from a cache of a translator and executed; when it is detected that a preset position in the translation result contains a target instruction, execution of the translation result is stopped; the target instruction is used for triggering writing in the preset position when it is detected that updating operation is carried out on the basic block; and when the translation result change is not detected in the cache, translating the basic block after the updating operation is executed, so as to obtain a corresponding correction result after the basic block is updated, and continuing to execute the correction result. The problem that in the prior art, cached basic block codes are not matched with actual codes after updating operation, code execution errors occur when the cached basic block codes are executed, and then translation accuracy is affected can be solved.

The invention discloses a dynamic binary translation acceleration method and system, a medium and a product, and the method comprises the steps: analyzing an ELF file of a target program before executing the target program, and extracting an external dependency library and function symbol information thereof; combining function information in a function library to generate an ELF function symbol information file containing function names of all function symbols and meta information of the function names, and mapping the ELF function symbol information file into a memory; when external function search calling is carried out in the process of binary translation execution of a target program in the target architecture, hash retrieval is carried out on ELF function symbol information in the memory; and according to the retrieved function type, realizing pointer mapping from the function type to a corresponding wrapper function, and according to the retrieved packaging type, obtaining an address of a local function to be executed actually so as to realize actual calling and parameter returning of the external function. The invention aims to reduce the symbol analysis and package matching overhead in the dynamic translation initialization process and improve the starting efficiency and the overall operation performance.

The invention discloses an operating system containerized kernel compatibility method based on mixed binary translation, which comprises the following steps of: constructing a container kernel data structure feature library containing field access frequency through static source code analysis and dynamic runtime tracking, generating a unique identifier consisting of a structure name and a high-frequency field offset sequence for a target structure, and generating a container kernel data structure feature library containing field access frequency; establishing an association graph between the system call and the target field; in a host machine, a static translation service is adopted to decompile a binary code of a container application, instrumentation is performed on a high-frequency site and a low-frequency site respectively, and an intermediate operation code sequence containing an operation code, a field name and double-end offset is pre-generated for the high-frequency site and stored in a cache; during operation, a pre-translation result is preferentially loaded from the cache for a high-frequency site, the pre-translation result is processed by the dynamic translation engine if the pre-translation result is not hit, and the pre-translation result is processed by the dynamic translation engine as required for a low-frequency site, so that efficient conversion combining field-level static preprocessing and on-demand dynamic conversion is realized.

The embodiment of the invention provides a binary translation method, a translator, electronic equipment and a readable storage medium, and the method comprises the steps: when a direct jump instruction in a first code block is translated, if it is determined that a jump target has a cross-page condition, recording jump target cross-page information, the jump target cross-page information being used for indicating a cross-page type; executing a target link strategy on the first translation code block and the second translation code block according to the jump target cross-page information; the target link strategy is used for judging whether the direct jump instruction meets an optimization condition or not according to a cross-page type indicated by the jump target cross-page information; and if the optimization condition is met, establishing a direct jump link for the first translation code block and the second translation code block. According to the embodiment of the invention, on the basis of ensuring the correct execution, the optimizable condition when the target page is skipped is identified, the link optimization operation is further executed, the code block search operation in the program running process is reduced, and the program running efficiency is improved.

The embodiment of the invention provides a binary translation method, electronic equipment, a readable storage medium and a program product, the method is applied to a translator, and after a client instruction stream is translated into a host instruction stream, a first class of instructions contained in the host instruction stream are obtained; the first type of instruction is a stack pointer calculation instruction, and a source operand of the first type of instruction comprises a stack pointer register and an immediate operand; under the condition that the number of the first-class instructions is M, combining the M first-class instructions into N first-class instructions based on the source operands of the first-class instructions; m is a positive integer larger than 1, and N is a positive integer smaller than M. Therefore, according to the embodiment of the invention, the host machine instructions after translation and before execution can be processed, the M first-class instructions are merged and processed into N instructions, the number of the first-class instructions after translation is reduced, the instruction expansion rate after translation is reduced, and the execution efficiency of a translator is improved.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The invention discloses a method and device for optimizing basic block jumping in a binary translation super block and computing equipment. The method for optimizing the basic block jump in the binary translation super block comprises the following steps: constructing a basic block in the super block; obtaining the current basic block and starting translation; if a direct jump instruction is encountered, jumping to a target basic block, combining the current basic block and the target basic block into a new basic block, and continuing to translate; if an indirect jump instruction is encountered, the current basic block which is translated at present points to the scheduling basic block, and translation is ended; if a privilege or abnormal instruction is encountered, the basic block which is translated currently points to the scheduling basic block, and translation is ended; and if the counter in the corresponding basic block exceeds a set threshold value, the translation is ended, otherwise, the translation is continued. According to the method, the times of quitting the super block when the super block is translated can be reduced, so that the overall execution performance of the super block is improved.

The embodiment of the invention provides a binary translation optimization method, a binary translator and electronic equipment, and the method comprises the steps: updating a state mark of a first register in a preset state table according to the write bit width of a narrow write operation to the first register when a narrow write operation instruction is translated; the state mark is used for indicating whether the high bit of the corresponding register needs to be reset or not and recording the effective bit width of the corresponding register; when a read operation instruction is translated, obtaining a state mark of a second register corresponding to read operation from the preset state table; if it is judged that the reading bit width of the reading operation is larger than the effective bit width indicated by the state mark of the second register, a first zero clearing instruction is inserted before the translation result of the reading operation instruction; the first zero clearing instruction is used for performing zero clearing on a specified high bit of the second register. According to the method, the target machine code sequence generated by translation can be simplified, redundant operations are greatly reduced, and the execution efficiency of a translation system is improved.

Embodiments of the present application provide an exception recovery method, device and electronic equipment, which are applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host, and the method comprises the following steps: in the case of an exception, determining a source instruction corresponding to a target instruction triggering the exception and a basic block in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to a target register according to the target position and a register delay calculation algorithm; the target register comprises registers corresponding to each instruction between a start position of the basic block and the target position and within a correction range of the register delay calculation algorithm; and correcting a value of the target register according to the offset value. Embodiments of the present application can solve problems such as incorrect register values caused by register delay optimization in the binary translation process in the case of exceptions, self-modifying code and other special cases, and improve the exception recovery efficiency.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining a dependency relationship between instructions in a target loop body if the target loop body is recognized to exist in a to-be-translated basic block; the obtained dependencies comprise dependencies among the instructions in the same-level iteration and dependencies among the instructions in different-level iterations; if it is recognized that a target instruction group matched with the preset mode exists in the target circulation body, marking is carried out; the instructions in the target instruction group have dependency relationships on the same register, and do not have dependency relationships of other instructions on the register; performing optimization translation on the marked target instruction group; the optimization translation means that the target instruction group is translated into a matched target instruction corresponding to the preset mode, and the instruction number of the target instruction corresponding to the preset mode is smaller than the instruction number in the target instruction group. According to the method, the number of translated instructions can be reduced, and the running efficiency of translated programs is improved.

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the following steps: translating a to-be-processed block to obtain a first sequence, and then adding a first instruction sequence into the first sequence; the first instruction sequence is used for writing a client virtual address of a jump block corresponding to the function call instruction into a preset address record stack; translating the jump block to obtain a host machine virtual address of the jump block, and adding a second instruction sequence in the first instruction sequence of the to-be-processed block corresponding to the jump block; if the client instruction to be translated is a return instruction, translating the return instruction to obtain a second sequence, and adding a third instruction sequence in the second sequence; the third instruction sequence is used for acquiring a record address corresponding to a return address of the return instruction from the address record stack as a target address, and skipping to the target address. And the efficiency of the binary translator is improved.

This invention discloses a method, apparatus, device, and medium for dynamic library mapping execution in binary translation, comprising: translating and executing the instructions of an x86 executable program; determining whether it is a dynamic library function call instruction; if it is a dynamic library function call instruction, parsing the call instruction to obtain the called function; using the called function as a lookup index key to query a pre-established dynamic library mapping allocator to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining the starting address of the RISC-V dynamic library in memory, and using the first value as an offset value to calculate the absolute address of the function in memory; determining the parameter address of the function based on the second value; performing calculations on the function using the parameter address and the absolute address, and returning the calculation result. This reduces the system overhead during the translation process.

The embodiment of the invention provides an exception recovery method and device and electronic equipment, and is applied to a binary translation system, the binary translation system is used for translating a source program in a client into a target program in a host machine, and the method comprises the following steps: under the condition that an exception occurs, translating the target program into a target program in the host machine; determining a source instruction and a basic block corresponding to the target instruction which is triggered abnormally in the source program, and marking a target position corresponding to the source instruction in the source program; determining an offset value corresponding to the target register according to the target position and a register delay calculation algorithm; the target register comprises a register corresponding to each instruction within a register delay calculation algorithm correction range between the initial position and the target position of the basic block; and correcting the value of the target register according to the offset value. According to the embodiment of the invention, the problems of register value errors and the like caused by delay optimization of the register in the binary translation process can be solved under the special conditions of exceptions, self-modification codes and the like, and the exception recovery efficiency is improved.

The embodiment of the present invention provides a branch prediction method, a processor and an electronic device, which are applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host machine, and the method comprises: when it is determined that the source program to be translated meets a preset condition, obtaining an auxiliary jump instruction and a jump instruction; wherein the jump instruction and the auxiliary jump instruction are corresponding instructions of the host machine; the auxiliary jump instruction comprises an operand, and the operand is determined according to the predicted jump address of the client in the source program to be translated; executing the auxiliary jump instruction to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction. The embodiment of the present invention can effectively reduce the bubbles generated by continuous jumps in the target program, which is beneficial to improving the prediction rate of the branch predictor and the operating efficiency of the binary translation system.

The invention discloses a dynamic library mapping execution method and device in binary translation, equipment and a medium. The method comprises the steps that translation execution is conducted on an instruction of an X86 executable program, whether the instruction is a dynamic library function calling instruction or not is judged, and when the instruction is the dynamic library function calling instruction, the calling instruction is analyzed, and a called function is obtained; querying in a pre-established dynamic library mapping distributor by taking the called function as a query index key to obtain a first value and a second value corresponding to the function in the RISC-V dynamic library; determining a first address of the RISC-V dynamic library in the memory, and calculating to obtain an absolute address of the function in the memory by taking the first value as an offset value; determining a parameter address of the function according to the second value; and calculating the function by using the parameter address and the absolute address, and returning a calculation result. And the system overhead in the translation process is reduced.

The invention discloses an application program running method and device, electronic equipment and a storage medium, and the method comprises the steps: translating a code of an application program into a first instruction and / or a second instruction; the first instruction is based on a first instruction set architecture and a data model is the same as a data model of a code of the application program; the second instruction is obtained based on the first instruction set architecture and through binary translation; compiling the code of the first shared library into a third instruction; the first shared library is a shared library of an operating system of the electronic equipment, the third instruction is based on a first instruction set architecture, and a data model is the same as a data model of a code of the application program; and executing the first instruction and / or the second instruction, and executing the third instruction to run the application program. According to the method, the binary translation range of the application program is reduced, the resource occupation of instruction expansion and instruction translation is reduced, and the compatibility of the translated instruction is improved.