A source computer
system with one
instruction set architecture (ISA) is configured to run on a target hardware
system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target
system, the invention provides
binary translation system. During execution from
binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring
processing action wholly within the target computer system) or non-transparent (requiring
processing that alters a visible state of the
source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied. The invention includes subsystems, and related methods of operation, for detecting the occurrence of all of these types of exceptions, to
handle them, and to do so with precise reentry into the interrupted
instruction stream; by “precise” is meant that the atomic execution of the source instructions is guaranteed, and that the application of actions, including those that originate from asynchronous exceptions, occurs at the latest at the completion of the
current source instruction at the time of the request for the action. The
binary translation and exception-handling subsystems are preferably included as components of a
virtual machine monitor which is installed between the target hardware system and the
source system, which is preferably a
virtual machine.