69 results about "Instruction pipeline" patented technology

The invention discloses a GPU computing power resource scheduling method and device based on load awareness and a medium, and relates to the technical field of computing power scheduling. The method comprises the steps that according to the video memory capacity and the number of calculation cores of the GPU, the video memory capacity is divided into a plurality of continuous fragments, the calculation cores are divided into a plurality of logic calculation groups, and sub-resource units are obtained; recording occupation states and load indexes of the sub-resource units in real time to obtain a resource pool; analyzing a job submitted by a user, and collecting an execution period of a kernel function, a video memory access mode and an instruction pipeline blocking rate when the job runs; and on the basis of a reinforcement learning algorithm, predicting a resource demand inflection point of the job according to the load fingerprint model, performing hierarchical scheduling on the sub-resource units based on virtualization isolation and multi-dimensional resource quantitative evaluation, and generating a preemptive allocation strategy of the sub-resource units. According to the method, efficient utilization and secure sharing of GPU resources are realized through collaborative design of dynamic granularity segmentation, load aware scheduling and hardware-level security isolation.

The invention provides an optimization method for sharing one group of physical registers by multiple groups of logic registers, which comprises the following steps: S1, defining a shared physical register file, the step comprises a physical register structure link and a quantity constraint link, the physical register structure link comprises N vector physical registers with VLEN bit width, and the quantity constraint link comprises N vector physical registers with VLEN bit width; each vector physical register can be divided into VLEN / FLEN floating point physical registers; in order to solve the problem of hardware redundancy caused by independence of a floating point register and a vector register in an RISC-V architecture, instruction pipeline sharing of floating point and vector expansion is realized through a scheme that multiple groups of logic registers share a physical register, and the hardware redundancy is avoided. And hardware overhead is reduced.

The invention provides a CPU assembly line operation monitoring system and method and electronic equipment, the system comprises an assembly line monitoring circuit and an event printing device, the assembly line monitoring circuit is in communication connection with the event printing device, the assembly line monitoring circuit is used for monitoring the operation state of a CPU kernel circuit, and the event printing device is in communication connection with the event printing device. The method comprises the following steps: capturing instruction information generated by a CPU kernel circuit in different stages of an instruction pipeline, wherein the instruction pipeline comprises an acquisition stage, a decoding stage, a transmitting stage, an execution stage and a retirement stage; the event printing device is used for triggering an event printing module corresponding to an instruction event category to print and output the instruction information according to the instruction event category generating the instruction information when the assembly line monitoring circuit captures the instruction information, and the instruction event category comprises an acquisition event, a distribution event, an execution event and a retirement event. The system is a monitoring mechanism independent of a CPU kernel circuit, records instruction information of each stage of a CPU assembly line, and improves monitoring granularity.

The invention provides an instruction pipeline processing method of a processor and the processor. A processor includes: a control module; the control module is set to execute the branch instruction speculatively according to the branch prediction direction when detecting that the first instruction subjected to initial decoding is the branch instruction, and execute the branch instruction if detecting that the second instruction subjected to initial decoding is the function call instruction or the function return instruction before the speculation execution result of the first instruction is generated. If yes, pausing all operations after the instruction processing assembly line performs initial decoding on the second instruction, and blocking the instruction fetching operation of the instruction processing assembly line on the next instruction until a speculation execution result of the first instruction is obtained; wherein the operation after the initial decoding comprises the step of carrying out a push-in or push-out operation of a return address stack (RAS) according to the second instruction. According to the technical scheme, the pollution risk caused by speculative execution of the branch instruction to the return address stack can be shielded, so that the hardware implementation logic of the return address stack is simplified, and the circuit area and power consumption are saved.

The invention discloses a processor, a chip, equipment and an instruction execution method. The processor comprises a shared memory for storing first quantity information, second quantity information, third quantity information and fourth quantity information; the first number information is the total number of threads in the working group, the second number information is the number of threads waiting to be synchronized on the N instruction branches, the third number information is the number of threads not needing to be synchronized, and the fourth number information is the number of finished threads. And the synchronization instruction assembly line is used for calculating the sum of the thread numbers of the second, third and fourth number information, and when the sum of the thread numbers is equal to the total number of the threads, unfinished threads in the working group are triggered to execute an instruction behind the rendezvous point. According to the scheme, under the condition that the sum of the thread numbers is equal to the total thread number, the synchronization instruction assembly line can trigger the threads which are not finished in the working group to continue to execute subsequent instructions, and the problem of task deadlock caused by the fact that part of the threads cannot reach the synchronization point is avoided.

The invention provides a system and method for processing different instructions on the same assembly line. The system comprises a control unit and an arithmetic unit, wherein the control unit is electrically connected with the arithmetic unit; the control unit comprises an instruction acquisition subunit, an instruction judgment subunit, an instruction register, an instruction decoder and a pipeline management subunit; the instruction registers include a first instruction register and a second instruction register. According to the method, instruction pipeline fusion is adopted for the two different types of instructions, and the two different instructions can run on the same pipeline through pipeline fusion, so that it is guaranteed that single-core hardware can process the two instructions on the same pipeline in a mixed mode, hardware resources are saved, and the hardware cost needed by the system is reduced; and meanwhile, the system has the advantages of high processing speed for the instruction of the first instruction type and high processing efficiency for the instruction of the second instruction type.

The invention discloses an ALU operation fusion processing module and method suitable for a neural network, and the module comprises a control unit which is used for receiving and decoding a machine instruction, managing the execution processes of internal and external circulation and microinstruction circulation, and generating a control signal of each stage of a microinstruction assembly line; the microinstruction buffer area is used for storing a microinstruction sequence pre-generated by the neural network compiler; the register file is used for storing source operands and results of ALU operation; each entry of the register file is composed of a valid bit, a tag bit and a data bit; the ALU computing core adopts an SIMD (Single Instruction Multiple Data) architecture and comprises a plurality of paths of parallel arithmetic logic function units; the Load / Store unit is used for processing data exchange between a register file and a local buffer area; and the data selection interface is used for selecting a data source or a target buffer area according to the storage tag field of the microinstruction. According to the method, the high efficiency and the flexibility of the ALU in the neural network hardware accelerator can be effectively considered.

The invention provides an operation method of an attention mechanism in a chip, the chip, electronic equipment, a storage medium and a program product. In a forward stage of attention model training, forward calculation is performed on a query matrix, a key matrix and a value matrix in each thread of a calculation engine based on a first instruction pipeline to obtain a forward output matrix, in algorithm implementation, matrix multiplication is executed by calling a matrix multiplication unit through a first thread and a third thread, and a forward output matrix is obtained. The vector calculation is processed by a second thread calling vector calculation unit; in a reverse phase, performing reverse calculation on the query matrix, the key matrix, the value matrix and the output gradient matrix in each thread based on a second instruction pipeline to obtain a target gradient matrix; the matrix multiplication unit is called in the first thread and the third thread to execute matrix multiplication, the vector calculation unit is called in the second thread to execute vector calculation, and the data carrying unit is called in the idle first thread or the third thread to obtain all matrixes. According to the invention, the operation performance of the chip can be improved.

A present invention embodiment improves responsiveness when looping on speculative atomic memory updates. A conditionally atomic updating instruction is determined to have encountered a fail condition. A fail loop of the conditionally atomic updating instruction is determined to have occurred. In response to determining that the conditionally atomic updating instruction has encountered the fail condition and that the fail loop has occurred, a count that each cross-interrogation request (XI) instruction rejection contributes toward an XI rejection count that is compared to a threshold is increased. In response to the XI rejection count satisfying the threshold, performing a selfish store mitigation operation, wherein the selfish store mitigation operation blocks a thread or core responsible for the fail loop from inserting a new instruction into an instruction pipeline and flushes non-completed instructions of the thread or core from the instruction pipeline.

Extraction across a predicted employed branch instruction in an extraction beam of a processor-based device is disclosed. In an exemplary aspect, a processor-based apparatus includes instruction processing circuitry configured to process a stream of instructions in an instruction pipeline. The instruction processing circuitry includes instruction fetch circuitry configured to generate a fetch bundle including a plurality of fetched instructions from the instruction stream, where a last fetched instruction of the plurality of fetched instructions is a branch instruction predicted to be taken. The instruction processing circuitry is further configured to identify the plurality of extracted instructions as loop iterations. The instruction processing circuitry is further configured to determine that at least one loop iteration copy is adapted to be placed within the fetch beam. The instruction processing circuitry is additionally configured to store the at least one loop iteration copy within the fetch beam in response to determining that the at least one loop iteration copy is adapted to be placed within the fetch beam.

In a general aspect, a processor includes a plurality of control registers, an instruction processing pipeline operatively coupled to the plurality of control registers, and a pipeline flush control unit operatively coupled to the instruction processing pipeline. The pipeline flush control unit is configured to record an indication of a first instruction in response to completion of execution of the first instruction by the instruction processing pipeline. The first instruction is configured to write to a first control register of the control registers. The pipeline flush control unit is also configured to identify a second instruction in the instruction processing pipeline before completion of execution of the second instruction and determine whether the second instruction conflicts with the first instruction based on a predetermined set of criteria. If the second instruction is determined to conflict with the first instruction, the pipeline flush control unit initiates a flush of the instruction processing pipeline.

The application discloses a kind of based on coprocessor's taint propagation method and system.The steps of the method include:1) pre-analysis instruction semantics, construct the taint propagation mask table of instruction;2) by coprocessor, intervene CPU instruction pipeline decoding, write-back process;3) in decoding stage, the opcode and operand of current instruction are acquired in real time quickly, and the taint propagation mask corresponding to instruction is found in taint propagation mask table by coprocessor;4) in write-back stage, the mask table corresponding to current instruction is searched in real time quickly, and taint propagation calculation is implemented.The application can analyze the semantics of instruction, calculate taint propagation process by using the characteristics of hardware fast and accurate when CPU instruction is executed by configuring the input function return value of monitoring.

The invention discloses a quantum measurement and control instruction assembly line parallel processing system, which adopts a double-thread framework, connects a producer thread and a consumer thread through a limited-capacity buffer queue, and can ensure the execution sequence of quantum measurement and control instructions and improve the execution efficiency of the quantum measurement and control instructions at the same time. The problems that in an existing measurement and control equipment system, serial processing efficiency is low, and the resource utilization rate is insufficient are solved, namely the technical defects that when an upper computer generates an instruction, external equipment is idle, and when the external equipment executes the instruction, the upper computer is idle are overcome, and a parallel assembly line strategy of upper computer instruction generation and external equipment instruction execution is achieved. The processing efficiency and the resource utilization rate are remarkably improved, and the method has high universality, expandability and a perfect exception processing mechanism.

Systems and methods related to a branch status table and control instruction buffer for processor instruction pipeline are disclosed herein. A processor may include a branch status table and a control instruction buffer. The branch status table may be formed by a set of registers and may store a set of pointers that correspond with a set of branches. The control instruction buffer may store a set of instruction pipeline control data entries in a set of addresses. The pointers may identify addresses which store the most recent instruction pipeline control data entries which proceed the branches that correspond with the pointers. Beneficially, when a branch misprediction occurs, the data structure can effectively be rewound to a point just before the misprediction with minimal overhead.

Reusing fetched, flushed instructions after instruction pipeline flushing in response to hazards in the processor is disclosed to reduce instruction refetching. The instruction processing circuitry is configured to detect fetched performance degradation instructions (PDIs) during the pre-execution phase of the instruction pipeline, which may result in a precise interrupt that causes instruction pipeline flushing. In response to detecting a PDI in the instruction pipeline, the instruction processing circuitry is configured to capture, in the pipeline refill circuitry, the fetched PDI and / or its subsequent, newer fetched instructions processed after the PDI in the instruction pipeline. If the subsequent execution of the PDI in the instruction pipeline causes instruction pipeline flushing, the instruction processing circuitry can inject the previously captured fetched PDI and / or its newer instructions from the pipeline refill circuitry into the instruction pipeline to be processed, without requiring such instructions to be refetched.

The invention provides a method for quickly releasing physical resources, a processor core and a processor, the method is applied to the processor core, and the processor core adopts an instruction pipeline mode to process an instruction; the method comprises the steps that under the condition that a register renaming unit completes register renaming operation on a first instruction, a submitting unit judges whether the first instruction is abnormal or not; and under the condition that the first instruction is determined not to be abnormal, the submitting unit releases a reordering buffer resource occupied by the first instruction, and the submitting unit sends a resource release message to the register renaming unit, the resource release message is used for notifying the register renaming unit to release the physical register resource occupied by the first instruction. According to the method, the physical resources occupied by the instruction can be more quickly released in the process that the processor core processes the instruction according to the instruction pipeline, so that the utilization rate of the physical resources and the performance of the processor can be improved.

The invention relates to a network processor and a chip, and the method comprises the steps: an instruction assembly line receives and analyzes a customer-defined instruction, reads a source data list and a command list from a storage module according to instruction analysis information, and transmits the source data list and the command list to a finite-state machine; in the finite-state machine, a data buffer stores source data and a command execution result, a command buffer stores a command list, a state controller reads a target command from the command list in sequence, obtains target source data from the data buffer according to the target command, then generates a task request and sends the task request to an execution unit, and the execution unit executes the task request. A command result returned by the execution unit is received and written into the data buffer, and finally, after the command list is executed, a write-back data write-back storage module is generated according to data in the data buffer. According to the method and the device, a customer can customize the custom instruction according to own requirements in the chip use process, and the utilization rate of the execution unit in the instruction assembly line is improved.

This application provides an IP address network partitioning method, apparatus, device, and storage medium, belonging to the field of asset management technology. The method includes: converting a target IP address into an integrated IP address block, wherein the target IP address belongs to either IPv4 or IPv6; determining the host bit width based on a variable-length subnet mask, and logically right-shifting the tail address block within the IP address block according to the host bit width to obtain a bit value; comparing the bit value of the tail address block with a reference bit value of the tail address block in a preset network partitioning rule to determine whether the target IP address matches the network partitioning rule. This method eliminates code redundancy and branch prediction failures. It significantly improves cache locality and instruction pipeline efficiency, thereby enhancing the adaptability of the solution.

A processor includes a plurality of execution pipelines and a distributed scheduler coupled to the plurality of execution pipelines. The distributed scheduler includes a first queue to buffer instruction operations from a front end of an instruction pipeline of the processor and a plurality of second queues, where each second queue is to buffer, for a corresponding separate subset of execution pipelines of the plurality of execution pipelines, instruction operations allocated from the first queue. The distributed scheduler further includes a queue controller to select an allocation mode from a plurality of allocation modes based on at least one indicator of whether an imbalance at the distributed scheduler is detected and further to control the distributed scheduler to allocate instruction operations from the first queue among the plurality of second queues in accordance with the selected allocation mode.

The present disclosure discloses a method for compiling a computational graph and related products. The method includes: obtaining a computational graph to be compiled, expressed by a second intermediate representation, performing forward deduction of the shape, and obtaining complete shape information based on the forward deduction and tensor data splitting information; using the complete shape information, determining whether the tensor data splitting information needs to be adjusted; determining tensor data splitting information that meets the requirements based on the judgment result; deducing memory access modes for operators in the computational graph based on the tensor data splitting information that meets the requirements; determining address domain-related parameters of instructions involved in a loop in the code logic of the computational graph based on the deduced memory access mode; pipeline-arranging the instructions in the loop; and compiling the computational graph based on the address domain-related parameters of the instructions involved in the loop and the result of the instruction pipeline arrangement to obtain a binary file recognizable by an intelligent processor.

A content provider in a content distribution system may be configured to reduce latency in a content distribution system by storing multiple frames from a sequence of frames in different buffers and encrypting, in parallel, the frames stored in the different buffers. For example, the content provider may encrypt each buffer via a different instruction pipeline of a processor.

The invention provides a Simulink code generation method and device based on instruction pipeline perception, and relates to the technical field of embedded code generation, and the method comprises the steps: carrying out instruction dependency analysis and delay modeling on a target Simulink model, and generating a dependency graph for describing a dependency relationship between modules and an instruction delay model combined with target processor system structure parameters; based on the dependency graph and the instruction delay model, determining an optimal execution sequence of each module through assembly line perception scheduling, and performing assembly line scheduling based on the optimal execution sequence to obtain a scheduling result; and based on the scheduling result, utilizing a local pipeline optimization strategy to generate a target code. According to the method provided by the invention, the data dependence path between the modules is determined by utilizing topology analysis, and the execution sequence is adaptively selected through the minimum penalty priority algorithm to avoid unnecessary waiting and resource conflicts, so that the number of pauses of the instruction assembly line is effectively reduced on the premise of ensuring the semantic consistency of the model.

The present disclosure relates to a thread scheduling system and method, an electronic device and a storage medium, the system comprising: an instruction cache module, an instruction register module, an execution module; the instruction cache module is configured to pre-read instruction data of a plurality of threads; the instruction register module is configured to store the pre-read instruction data of the plurality of threads, and in one clock cycle, determine a target thread and a target instruction of the target thread according to the instruction data of the plurality of threads; and the instruction register module is configured to send the target instruction of the target thread to the execution module. The embodiment of the present disclosure effectively reduces the thread scheduling time in the instruction pipeline scenario, and improves the utilization rate of the execution module.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

Systems and methods related to a branch status table and control instruction buffer for processor instruction pipeline are disclosed herein. A processor may include a branch status table and a control instruction buffer. The branch status table may be formed by a set of registers and may store a set of pointers that correspond with a set of branches. The control instruction buffer may store a set of instruction pipeline control data entries in a set of addresses. The pointers may identify addresses which store the most recent instruction pipeline control data entries which proceed the branches that correspond with the pointers. Beneficially, when a branch misprediction occurs, the data structure can effectively be rewound to a point just before the misprediction with minimal overhead.

This application relates to a network processor and chip, comprising: an instruction pipeline that receives and parses customer-defined instructions; reads a source data list and a command list from a storage module based on the instruction parsing information; and sends them to a finite state machine. In the finite state machine, a data buffer stores the source data and command execution results, a command buffer stores the command list, a state controller sequentially reads the target command from the command list, obtains the target source data from the data buffer based on the target command, generates a task request and sends it to the execution unit, receives the command result returned by the execution unit and writes it to the data buffer, and finally, after the command list is executed, generates a write-back data write-back storage module based on the data in the data buffer. This application enables customers to customize instructions according to their own needs during chip use and improves the utilization rate of the execution units in the instruction pipeline.

Systems and methods related to a processor with opportunistic bypass of dispatch buffer and reservation station are disclosed herein. The microarchitecture of the processor can determine when conditions exist for the dispatch buffers, reservation station, or other components of an instruction pipeline, to be bypassed by an instruction. One or more components may be bypassed after at least a portion of the instruction pipeline is flushed or ignored. Instructions may bypass one or more components if the source operands of the instruction are ready, there is sufficient space at the destination bypass path, and if the bypassed component is empty. Systems and methods as disclosed herein may improve the efficiency of processing instructions and reduce penalties for branch interpretations and other errors.

A processor, an instruction processing apparatus, an electronic device and an instruction processing method. The processor comprises: an instruction fetching unit, an instruction parsing unit, a DQ instruction execution unit and a CA instruction execution unit, wherein the instruction fetching unit, the instruction parsing unit and a first target unit form a first instruction pipeline; the instruction fetching unit, the instruction parsing unit and a second target unit form a second instruction pipeline; when a target condition is met, the first instruction pipeline and the second instruction pipeline are executed in parallel; and the first target unit comprises the DQ instruction execution unit, and the second target unit comprises the CA instruction execution unit.

This invention discloses a method, apparatus, and system for GPU performance prediction. In this embodiment, the following steps are taken: First, the hardware parameters of the function to be executed and the GPU to be tested are obtained. Then, the function to be executed is decomposed into multiple tasks according to a set decomposition method. These tasks are then allocated to multiple streaming multiprocessors (SMs) of the GPU according to a set scheduling method, and at least one task is assigned to each SM. Finally, the at least one task assigned to each SM is assigned to multiple instruction pipelines within that SM. A multi-level feature set is determined based on the multiple instruction pipelines. The multi-level feature set is then input into a multilayer perceptron (MLP), and the predicted latency is output. Through this method, the complex workflow of the function to be executed can be mapped to a fine-grained instruction pipeline. A multi-level feature set is constructed based on the instruction pipelines, and the MLP is used to capture nonlinear competition between different instruction pipelines, accurately predicting the latency of the GPU under test and determining its performance.

Data hazards are avoided by stalling from execution a received secondary instruction determined to be dependent on a primary instruction by an associated instruction pipeline if a counter of a plurality of counters associated with the primary instruction indicates that there is a hazard related to the primary instruction. In response to detecting that a hazard related to a primary instruction has been resolved by an instruction pipeline of a plurality of instruction pipelines, an adjustment signal is transmitted to a counter block that causes the value of the counter of the plurality of counters of the counter block associated with the primary instruction to be adjusted to indicate that the hazard related to the primary instruction has been resolved.