66 results about "Conditional branch" patented technology

The invention discloses a hand-eye cooperative robot control system and method based on dynamic operator arrangement, an upper computer planning layer operates a master control computer to periodically trigger task scheduling, a joint controller of a lower computer execution layer receives an instruction through a redundant bus to perform servo control, hand-eye camera data triggers a visual assembly line through an interrupt event, and a visual assembly line is controlled through a control interface. According to the method, pressure is calculated through visual processing, motion planning and joint control in a load sharing mode, a double-buffering mechanism is adopted to enable current frame visual processing and previous frame motion control to be executed in an overlapping mode, real-time scheduling and parallel computing of tasks are completed, hot data are cached in a memory database, cold data are archived to an HDFS and migrated through an LRU strategy, and the real-time scheduling and parallel computing of the tasks are completed. Data type conversion is automatically derived and performed based on a feature type registry, and conditional branch execution is triggered according to real-time sensor data. According to the control system, cross-hardware plug and play, algorithm flow configurability and data flow real-time sharing are achieved, and the requirement for improving the efficiency of complex operation tasks is met.

Circuitry and methods for implementing conditional fence instructions are described. In certain examples, a hardware processor (e.g., core) includes a branch predictor to predict one of a taken path and a not taken path for a conditional branch instruction; decoder circuitry to decode an instruction into a decoded instruction, the instruction comprising a field that indicates a condition to be set by execution of another instruction, and an opcode that indicates execution circuitry is to, in response to the condition being satisfied, implement an execution fence to delay execution of the instruction until prior instructions in program order execute and delay execution of instructions after the instruction in program order until the instruction executes; and the execution circuitry to execute the decoded instruction according to the opcode.

The invention discloses a production scheduling method and system based on multiple process branches. The method comprises the following steps of: analyzing a process route containing parallel or conditional branches, enumerating all complete process routes, respectively performing pre-scheduling simulation, allocating resources for a process and calculating time; evaluating and scoring each scheme by using a multi-target evaluation model; and finally, selecting and outputting an optimal scheduling scheme according to the score. According to the invention, by enumerating all complete process paths and simulation, the plan robustness is improved, conflict coordination of shared resources is realized, and idle equipment is reduced; the resource utilization rate, the order delivery time and the load balance are optimized through multi-target evaluation, so that the production cycle is shortened, the cost is reduced, and the scheduling automation level is enhanced.

A method, computer program (3), computer-readable data-carrier (4), computing device (2), and apparatus (1), such as a vehicle, in particular an aircraft, for deterministic execution of an instruction set (I) containing instructions (M) to be carried out by a processing unit (11) of the computing device (2), are provided, the method comprising the steps of executing a predefined number of pre-branch instructions (A) up to a conditional branch (C) of the instruction set (I) containing at least one branch condition determining a subsequent instruction which is to be executed after the conditional branch (C); predicting at least one of the pre-branch instructions (A) and / or a target instruction (T) to be executed as the subsequent instruction if the at least one condition is met; and inserting the at least one predicted pre-branch instruction (A) and / or the target instruction (T) into the instruction set (I) after the conditional branch (C).

The invention relates to a network module verification process generation method and system and a storage medium, and relates to the technical field of embedded communication, and the method comprises the steps: S1, obtaining a to-be-analyzed AT instruction document, and carrying out the preprocessing of the AT instruction document, and obtaining a plurality of plain text segments; s2, inputting the plain text segment into a preset semantic analysis engine for semantic extraction to obtain a semantic triple; s3, constructing an AT instruction knowledge graph according to the semantic triple; and S4, generating a network module verification process corresponding to the AT instruction document according to the AT instruction knowledge graph. Compared with the prior art, the method has the advantages that zero manual reading can be realized, multi-language and multi-format documents are supported, the time sequence, dependency and conditional branches among instructions are understood, an executable graphical verification process is automatically generated, and incremental updating is supported.

A computer-implemented workflow generation method in which a computer executes processing of calculating, in a case where a conditional branch item included in a workflow is acquired, an indicator value in a case where any one of a plurality of candidate items is used by using a machine learning model, by referring to a storage that stores the plurality of candidate items satisfying a condition of a branch destination corresponding to the conditional branch item and the machine learning model that calculates the indicator value of each of the plurality of candidate items, selecting an item of which the calculated indicator value satisfies a predetermined condition from among the plurality of candidate items, and generating a workflow in which the selected item is arranged at the branch destination of the conditional branch item.

The embodiment of the invention provides a code processing method and device, electronic equipment and a readable medium, and relates to the technical field of compilation, in the method, in the conversion process of source codes, any conditional branch statement contained in the source codes is detected. If it is detected that the code logic of the conditional branch statement conforms to the specified code logic, determining the conditional branch statement as a statement to be optimized; the code logic is used for representing the operation indicated by the conditional branch statement. And based on the related parameters defined by the to-be-optimized statement, converting the to-be-optimized statement into a non-branch instruction group for realizing code logic of the to-be-optimized statement. Compared with a mode of converting the conditional branch statements into the conditional branch instructions, the method and the device have the advantage that the statements to be optimized are converted into the non-branch instruction groups for realizing the code logic of the statements to be optimized. Therefore, the number of the generated branch instructions can be reduced under the condition of ensuring normal implementation of code logic, so that the subsequent execution performance can be improved.

A method of detecting malicious behavior in a malicious behavior detection apparatus that detects malicious behavior by analyzing the code of a program, comprises generating a first control flow graph (CFG) by performing dynamic analysis on the program, generating a second CFG by extracting a code block that is likely to be executed by a conditional branch instruction included in the program, and comparing the first CFG and the second CFG to detect hidden code included in the program, and detecting a malicious behavior of the program by determining whether the detected hidden code is a malicious code. According to the constitutions, the time it takes to discover and respond to new types of malicious code can be shorten by extracting hidden code related to the malicious behavior and detecting malicious behavior.

A method for deterministic execution of an instruction set (I) containing instructions (M) to be carried out by a processing unit of the computing device includes the steps of executing a predefined number of pre-branch instructions (A) up to a conditional branch (C) of the instruction set (I) containing at least one branch condition determining a subsequent instruction which is to be executed after the conditional branch (C); predicting at least one of the pre-branch instructions (A) and / or a target instruction (T) to be executed as the subsequent instruction if the at least one condition is met; and inserting the at least one predicted pre-branch instruction (A) and / or the target instruction (T) into the instruction set (I) after the conditional branch (C). A computer program, computer-readable data-carrier, computing device, and apparatus, such as a vehicle, in particular an aircraft may be configured to perform the method.

The embodiment of the invention discloses a branch prediction method, device and system, a computer device, a medium and a product. The branch prediction method comprises the following steps: at least dividing a jump threshold value of a first direction predictor into a first jump threshold value and a second jump threshold value which respectively correspond to an unconditional branch and a conditional branch of a zero-delay branch target buffer; according to the hit result, determining a jump threshold corresponding to the first direction predictor and jump thresholds of other direction predictors; if the determined jump threshold value corresponding to the first direction predictor is a first jump threshold value, determining a jump prediction result according to a symbol of the first jump threshold value; and if the determined jump threshold value corresponding to the first direction predictor is a second jump threshold value, performing addition operation on the second jump threshold value and jump threshold values of other direction predictors, and determining a jump prediction result according to a symbol of an addition operation result. According to the method, the logic depth of the ZBTB can be reduced, the capacity of the ZBTB can be improved, and the BP prediction speed can be improved.

The invention relates to a multi-layer nested service visual scheduling engine and method based on a graph structure, and belongs to the technical field of visual programming. The engine comprises a visual design module, a graph analysis module and a logic judgment module which are in communication connection with one another; the visual design module is used for constructing a business flow chart by dragging nodes, drawing edges and setting nested nodes, and the chart analysis module is used for converting the business flow chart into a task execution plan. And the logic judgment module is used for determining a concurrent and serial execution sequence of a plurality of tasks and an execution path of a conditional branch according to the task execution plan, and generating a logic judgment result.

Embodiments of this disclosure provide an instruction processing method and apparatus, a processor, an electronic device, and a storage medium. The instruction processing method includes, in response to identifying a first conditional branch instruction with a back jump from an instruction stream, recording instruction information of the first conditional branch instruction; in response to identifying the first conditional branch instruction with a back jump at least once more, determining that the first conditional branch instruction is an end branch instruction in a loop body instruction and performing a backfilling operation on the loop body instruction, the loop body instruction including at least one second branch instruction other than the first conditional branch instruction; performing the backfilling operation on the loop body instruction includes: backfilling the instruction information of the second branch instruction into an instruction information cache; invoking a branch predictor to obtain first prediction information of the second branch instruction, and backfilling the first prediction information into a branch instruction information cache. This instruction processing method expands the scope of loop body instruction recognition and reduces cache access power consumption.

The application discloses an evasive malicious software detection method and system based on dynamic plug-in. The method is as follows: deploying anti-anti-plug-in strategy, constructing trapping environment; inserting monitoring code in multiple levels of the trapping environment, establishing multi-level and fine-grained program behavior monitoring; for each target program in the trapping environment, after the probe instruction or function in the monitoring code is executed, the memory buffer area or register used for storing the probe result is dynamically identified and marked; the probe result is continuously monitored, when the probe result is tracked to be used for comparison instruction and affects the jump of subsequent conditional branch instruction, it is determined that the target program has a "probe-decision" logic chain; when the target program has one or more "probe-decision" logic chains, it is determined that the target program is evasive malicious software. The application can realize accurate, robust and automatic identification of evasive behavior.

The invention relates to the technical field of low codes, in particular to a low-code service configuration engine and a configuration method thereof. The device comprises a relation unit execution module used for defining and executing an input-operation-output relation unit; the JSON configuration analysis module is used for analyzing a configuration file in a JSON format, the configuration file comprises version information, variable initialization configuration and task configuration, and system behaviors are defined in a declarative configuration mode; the hardware abstract interface module is used for providing an operation interface irrelevant to hardware and realizing complete abstraction of hardware operation through a callback mechanism; the backup storage module is used for storing and backing up the configuration file by adopting two storage slots, and each storage slot is provided with a configurable storage space; and the real-time multi-task execution module is used for task scheduling and execution based on RTOS and supports multi-task parallel execution, conditional branching and loop control. According to the invention, the development complexity of the industrial control system is reduced, and non-technical personnel can quickly configure complex control logic.

Example solutions for optimizing an initial query execution plan for a federated database includes identifying a group of operations in the initial query execution plan that conform to a recognized pattern including fetching data from a data store. Based on detection of the pattern and of the presence of a condition, an optimized query execution plan is created from the initial query execution plan by replacing the group of operations with a first execution branch and a second execution branch, wherein the optimized query execution plan executes at least one of the first and second execution branches. The first execution branch includes first operations for fetching the data from a first data store and the second execution branch comprise second operations for fetching at least a subset of the data from a second data store.

Circuits and methods for conditional fence instructions are described. In some examples, a hardware processor (e.g., a core) includes a branch predictor to predict one of an taken path and an untaken path of a conditional branch instruction; decoder circuitry to decode an instruction to a decoded instruction, the instruction including a field indicating a condition set by executing another instruction and an opcode indicating that the execution circuitry will implement an execution fence in response to the condition being satisfied to delay execution of the instruction prior to execution of a previous instruction in a program order, the opcode indicating that the execution circuitry will implement the execution fence in response to the condition being satisfied. And before the instruction is executed, delaying execution of an instruction following the instruction according to the program order; and the execution circuit is used for executing the decoded instruction according to the operation code.

Various embodiments described herein control circuitry of a computing device to invalidate certain data elements associated with a forward conditional branch instruction (FCBI) to prevent computational inefficiencies, such pipeline flush. The data elements that are invalidated may correspond to conditional code associated with an FCBI. To make FCBIs more efficient, certain embodiments continue with a not-taken path that is invalidated if a branch resolves to be taken. This results in efficiencies because either the prediction was correct; or when the wrong path is taken, the wrong path is invalidated, thereby avoiding any resource utilization in redirection. In this manner, the FCBI may be executed more quickly or efficiently because certain data elements, such as the conditional code, are invalidated. Accordingly, certain embodiments improve computational inefficiencies, enhance performance of complex computational workloads with certain branches, and reduce or altogether eliminate pipeline stall and flushing for certain workloads.

An interrupt simulation device (10) includes an accumulation addition unit (14) and a branch addition unit (15). The accumulation addition unit (14) adds an accumulation addition process to add a value corresponding to an estimated execution time of a target basic block to a counter variable corresponding to a cumulative execution time of a target program (20) when the target basic block is executed in the target program (20) in a case in which each basic block of multiple basic blocks are regarded as the target basic block when the target program (20) being a computer program is divided into the multiple basic blocks. The branch addition unit (15) adds a conditional branching process that is executed when a value of the counter variable satisfies an ignition reference condition, to the target program (20).

This invention relates to computer programming and software engineering technology, specifically to a program control flow visualization method and system, and an electronic device. The program control flow visualization method includes: receiving an abstract syntax tree generated by a parser after parsing the program control flow source code through a receiving module; converting the control flow statements contained in the abstract syntax tree into a standardized flow graph containing only if / else conditional branches and unconditional edges through a conversion module according to a preset reduction rule; and adjusting the positions of unconditional edges and corresponding nodes and edges of each statement in the standardized flow graph through an image processing module according to an orthogonal layout method and / or a conflict elimination method, so as to optimize the standardized flow graph into a non-intersecting visual layout graphic.

This disclosure proposes an instruction processing method, apparatus, electronic device, chip, and storage medium. The method includes: responding to the current instruction being a conditional branch instruction, using a first branch predictor to predict the branch direction of the current instruction to obtain a first prediction result; wherein the first prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the current instruction being a loop branch instruction, using a second branch predictor to predict the branch direction of the current instruction to obtain a second prediction result; wherein the second prediction result is used to indicate whether a jump occurs after the current instruction is executed; responding to the second prediction result differing from the first prediction result, using the second prediction result to correct the first prediction result, thereby improving the accuracy of the first prediction result. Based on the accurate first prediction result, performance loss caused by prediction errors can be reduced.

Technology to program graphics processing unit (GPU) command buffers can include a processor and memory storing instructions which, when executed, cause the processor to compile a source file to generate a command list, where the command list includes hardware-specific executable commands for a GPU, and dispatch the command list to a command buffer for execution by the GPU. The command list can be dispatched via an application programming interface (API) call to a graphics driver, where the API call bypasses generating GPU commands for the command list and the graphics driver bypasses encoding the hardware-specific executable commands in the command list. Source files can include function calls specific to GPU hardware blocks, where the command list includes executable commands directed to the GPU hardware blocks based on the function calls. The command list can include an executable loop command, an executable conditional branch command, and / or an executable jump command.

A generation method includes acquiring a first measure and a second measure configured from graph data including a plurality of conditional branches coupled by a directed edge and nodes coupled to destinations to which each of the plurality of conditional branches is branched, first generating information regarding a first difference between the acquired first and second measures, the first difference being at least one of a difference in structure of graph data and a difference in branch probability of an object assigned to a node of the conditional branch, and second generating correspondence information in which the generated information regarding the first difference is associated with information regarding a second difference between the acquired first and second measures, the second difference being at least one of a difference in effect value and a difference in certainty factor, by a processor.

Technology to program graphics processing unit (GPU) command buffers can include a processor and memory storing instructions which, when executed, cause the processor to compile a source file to generate a command list, where the command list includes hardware-specific executable commands for a GPU, and dispatch the command list to a command buffer for execution by the GPU. The command list can be dispatched via an application programming interface (API) call to a graphics driver, where the API call bypasses generating GPU commands for the command list and the graphics driver bypasses encoding the hardware-specific executable commands in the command list. Source files can include function calls specific to GPU hardware blocks, where the command list includes executable commands directed to the GPU hardware blocks based on the function calls. The command list can include an executable loop command, an executable conditional branch command, and / or an executable jump command.

An extraction method includes acquiring a measure including a plurality of conditional branches coupled by a directed edge and each node coupled to a branch destination of each of the plurality of conditional branches, and extracting a conditional branch that is a branch source of each of the nodes from the plurality of conditional branches included in the measure, by a processor.

The invention discloses a high-concurrency processor architecture based on an instruction level event structure and a scheduling method of the high-concurrency processor architecture, which are characterized in that on the basis of an RISC-V instruction, stagnation, successful termination, sequential execution, conditional branching and merging operations of a program are defined through a process algebra PA-ISA oriented to an instruction set architecture; on the basis of PA-ISA, a dependency relationship among instructions in program execution is described through an instruction level event structure IES. According to the method, an instruction-level event structure model is adopted to describe a dependency relationship among instructions in a program, so that the concurrency of the instructions is improved, and good expansibility is achieved; a high-concurrency processor architecture based on IES is combined with an asynchronous circuit, event triggering is used as a basic execution propulsion mode, and the frequency or energy efficiency is improved; by simplifying a bypass control mechanism in out-of-order execution, the system reliability is improved; through combination of an instruction-level event structure and a double-path fetch mechanism, instruction waste and performance loss are reduced, and the fault-tolerant capability under a large-scale fetch strategy is optimized.

A policy evaluation method includes, when acquiring a first policy that is a policy including a conditional branch and a node connected by a directed edge, referring to a storage that stores a plurality of second policies and an evaluation value of each of the plurality of second policies, the evaluation value indicating a number of targets to which a plurality of targets is assigned to a node by the policy, calculating a similarity measure between the first policy and each of the plurality of second policies, and outputting an evaluation value of a similar policy that is a policy including the conditional branch and the node having the similarity measure equal to or greater than a threshold among the plurality of second policies, by a processor.

The present invention provides a design method of an experimental protocol capable of coping with a higher-level process. A system of one aspect includes at least one experimental device (121-126), a control device, and a terminal device. The control device controls the at least one experimental device (121-126) to execute an experimental protocol (p1) that defines a process order of the at least one experimental device (121-126). The terminal device designs the experimental protocol (p1) in the form of a directed graph (DG1) through GUI operation of a user on a specific application (500). A plurality of nodes selectable as vertices of the directed graph (DG1) in the terminal device include a process node (M1) corresponding to each process of the at least one experimental device (121-126), and a conditional branch node (T2) corresponding to a conditional branch process.

Example solutions for optimizing an initial query execution plan for a federated database includes identifying a group of operations in the initial query execution plan that conform to a recognized pattern including fetching data from a data store. Based on detection of the pattern and of the presence of a condition, an optimized query execution plan is created from the initial query execution plan by replacing the group of operations with a first execution branch and a second execution branch, wherein the optimized query execution plan executes at least one of the first and second execution branches. The first execution branch includes first operations for fetching the data from a first data store and the second execution branch comprise second operations for fetching at least a subset of the data from a second data store.

The application relates to the technical field of APP development, in particular to an industrial application software code testing method based on a large model, which comprises the following steps: receiving an industrial application software source file, parsing function definition statements and interface calling instructions in the file, extracting logical connection relationships between various business modules, constructing a function calling topological graph reflecting code unit directivity, and mapping code character sequences of each node in the function calling topological graph to a high-dimensional numerical coordinate system through a large model. In the application, conditional branching and parameter type reverse deduction are performed on a key path, constraint conditions are solved, and regression test case data capable of triggering a specific business scenario are automatically generated. In this way, the selection of a test focus, the discovery of a key path and the generation process of test data are automated and intelligentized, so that test resources can be accurately invested in function links with the highest value and the highest risk in software, and the test efficiency is improved.