12 results about "Conditional branch" patented technology

Embodiments of this disclosure provide an instruction processing method and apparatus, a processor, an electronic device, and a storage medium. The instruction processing method includes, in response to identifying a first conditional branch instruction with a back jump from an instruction stream, recording instruction information of the first conditional branch instruction; in response to identifying the first conditional branch instruction with a back jump at least once more, determining that the first conditional branch instruction is an end branch instruction in a loop body instruction and performing a backfilling operation on the loop body instruction, the loop body instruction including at least one second branch instruction other than the first conditional branch instruction; performing the backfilling operation on the loop body instruction includes: backfilling the instruction information of the second branch instruction into an instruction information cache; invoking a branch predictor to obtain first prediction information of the second branch instruction, and backfilling the first prediction information into a branch instruction information cache. This instruction processing method expands the scope of loop body instruction recognition and reduces cache access power consumption.

The application discloses an evasive malicious software detection method and system based on dynamic plug-in. The method is as follows: deploying anti-anti-plug-in strategy, constructing trapping environment; inserting monitoring code in multiple levels of the trapping environment, establishing multi-level and fine-grained program behavior monitoring; for each target program in the trapping environment, after the probe instruction or function in the monitoring code is executed, the memory buffer area or register used for storing the probe result is dynamically identified and marked; the probe result is continuously monitored, when the probe result is tracked to be used for comparison instruction and affects the jump of subsequent conditional branch instruction, it is determined that the target program has a "probe-decision" logic chain; when the target program has one or more "probe-decision" logic chains, it is determined that the target program is evasive malicious software. The application can realize accurate, robust and automatic identification of evasive behavior.

This invention relates to computer programming and software engineering technology, specifically to a program control flow visualization method and system, and an electronic device. The program control flow visualization method includes: receiving an abstract syntax tree generated by a parser after parsing the program control flow source code through a receiving module; converting the control flow statements contained in the abstract syntax tree into a standardized flow graph containing only if / else conditional branches and unconditional edges through a conversion module according to a preset reduction rule; and adjusting the positions of unconditional edges and corresponding nodes and edges of each statement in the standardized flow graph through an image processing module according to an orthogonal layout method and / or a conflict elimination method, so as to optimize the standardized flow graph into a non-intersecting visual layout graphic.

Technology to program graphics processing unit (GPU) command buffers can include a processor and memory storing instructions which, when executed, cause the processor to compile a source file to generate a command list, where the command list includes hardware-specific executable commands for a GPU, and dispatch the command list to a command buffer for execution by the GPU. The command list can be dispatched via an application programming interface (API) call to a graphics driver, where the API call bypasses generating GPU commands for the command list and the graphics driver bypasses encoding the hardware-specific executable commands in the command list. Source files can include function calls specific to GPU hardware blocks, where the command list includes executable commands directed to the GPU hardware blocks based on the function calls. The command list can include an executable loop command, an executable conditional branch command, and / or an executable jump command.

The application relates to the technical field of APP development, in particular to an industrial application software code testing method based on a large model, which comprises the following steps: receiving an industrial application software source file, parsing function definition statements and interface calling instructions in the file, extracting logical connection relationships between various business modules, constructing a function calling topological graph reflecting code unit directivity, and mapping code character sequences of each node in the function calling topological graph to a high-dimensional numerical coordinate system through a large model. In the application, conditional branching and parameter type reverse deduction are performed on a key path, constraint conditions are solved, and regression test case data capable of triggering a specific business scenario are automatically generated. In this way, the selection of a test focus, the discovery of a key path and the generation process of test data are automated and intelligentized, so that test resources can be accurately invested in function links with the highest value and the highest risk in software, and the test efficiency is improved.

This invention relates to the field of computer software technology, and in particular to a low-code workflow design system and application based on a workflow engine, comprising a multi-flow collaboration engine layer, an AI-enhanced rule orchestration layer, a distributed architecture layer, a data storage layer, a user interaction layer, and an extension interface layer. This invention achieves deep linkage between logic flow, data flow, and event flow through an event bus, constructing a closed loop of event triggering, logical judgment, and data flow, overcoming the limitations of traditional platforms that only support single process types and lack multi-flow collaboration capabilities. The logic flow engine supports multi-level conditional branches, nested sub-processes, and parallel task splitting; the data flow engine achieves seamless cross-system data mapping; and the event flow engine ensures real-time triggering and asynchronous notification. The three work together to meet the diverse needs of complex enterprise-level processes, such as the linkage between approval flows and data processing flows, and cross-system event-driven process execution.

The application provides a parallel thread virtualization and SIMT semantic degradation execution method and system, and belongs to the technical field of parallel computing. The application comprises the following steps: receiving a parallel source program and identifying kernel data; extracting parallel semantics from the kernel data and constructing an intermediate representation; constructing an activity mask based on the intermediate representation to indicate an effective logical thread set in a strip by using a vector length independent striping mapping; splitting host and device program instructions according to the kernel data; performing vector predication on a conditional branch to realize independent execution of each logical thread; intercepting a kernel start call through a pad layer on the host side, serializing kernel parameters into a command descriptor, writing the command descriptor into a lock-free ring queue of shared memory, and notifying the device to execute through a doorbell mechanism; and the device end firmware analyzes the command descriptor, configures execution resources, and jumps to the generated kernel code for execution. The application realizes efficient and transparent degradation of a parallel thread model.

The invention relates generally to cryptography in secure microchips using a password authentication scheme. More specifically, the invention is directed to a uniquely configured electronic hardware component and method of usage for providing secure password initialization and branch-free password authentication. The electronic hardware component together with a method of usage results in a system that, upon correctly entering a possibly low-entropy secret, such as a password, outputs a high-entropy cryptographic key while allowing only a limited number of attempts to enter the correct password. The invention effectively enforces the limit on the number of password attempts without employing a numeric counter, thus eliminating the use of conditional branching operations and making it suitable for use in secure tamper-resistant integrated circuits.

A method for making a program compatible across multiple-versions of Operation Systems (OS) is disclosed. The method includes receiving the program to be attached to function. Next, the method includes compiling the received program using macro to make it agnostic to OS version. The macro includes a conditional branching feature for determining type of syscall based on flag information from a shared map for attaching the program in different OS versions. Thereafter, the method includes attaching the program to the OS based on the determined type of syscall. In one scenario, the program is attached to a first function if the determined type of syscall is of a first type. In another scenario, the program is attached to a second function if the determined type of syscall is of a second type.

The invention relates generally to cryptography in secure microchips using a password authentication scheme. More specifically, the invention is directed to a uniquely configured electronic hardware component and method of usage for providing secure password initialization and branch-free password authentication. The electronic hardware component together with a method of usage results in a system that, upon correctly entering a possibly low-entropy secret, such as a password, outputs a high-entropy cryptographic key while allowing only a limited number of attempts to enter the correct password. The invention effectively enforces the limit on the number of password attempts without employing a numeric counter, thus eliminating the use of conditional branching operations and making it suitable for use in secure tamper-resistant integrated circuits.

This invention provides a microprocessor and a branch prediction control method. In one embodiment, a microprocessor includes: a table including a plurality of edges, wherein at least a first edge includes a first conditional branch predictor having a first set of prediction tables, wherein at least a second edge includes a second conditional branch predictor having a second set of prediction tables, wherein the second conditional branch predictor is configured to provide a first prediction based on a prediction table hit for a branch instruction including information in the second edge, and wherein the first conditional branch predictor has higher complexity than the second conditional branch predictor; and control logic, wherein, based on receiving an indication of an incorrect prediction corresponding to the first prediction for the branch instruction, the control logic is configured to write information for the branch instruction into one of the first set of prediction tables of the first edge.

The application is suitable for the field of computer programming and provides a Java language LINQ expression implementation method based on chain calling, which comprises the following steps: providing a LinqQuery interface, the LinqQuery interface defines a chain operator where operator and select, and type safety is provided through a generic T; a user generates an operator tree through calling the chain operator of the LinqQuery interface, the operator tree is used for recording query logic; the operator tree is parsed, query is executed in layers, and a result set is returned; the application has the beneficial effects that compared with traditional loop and conditional branch implementation, the number of code lines is reduced by about 40%, the readability is significantly improved, through an open operator interface, a developer can easily extend query functions, through generic constraints, type checking of query logic is completed at the compilation stage, runtime errors are reduced, and unified query of various scenes such as memory collection, database query and file reading is supported.