98 results about "Micro-operation" patented technology

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

An automatic end effector tip position initialization mechanism for a micromanipulation system is provided. The method includes: S1, positioning a macro end effector tip, calculating a camera pose by using ArUco Tag, and realizing a three-dimensional positioning of the end effector tip by using a triangulation method, and moving the end effector to a area near a center of a focal plane based on a visual servo; S2, positioning a micro end effector tip; S3, acquiring calibration data based on a visual servo, calibrating the end effector tip and the petri dish, and obtaining a left calibration matrix and a right calibration matrix reflecting the transformation relationship between left and right micromanipulator coordinates and image coordinates; generating an intuitive human-computer interaction interface based on a mouse and a keyboard according to acquired position information. The method has obvious advantages in terms of operation accuracy, operation efficiency and repeatability.

The embodiment of the invention provides a multi-account concurrent processing management system and a multi-account concurrent processing management method, which are applied to the technical field of multi-account high-concurrency business processing, and are used for analyzing a plurality of received account operation requests into a micro-operation set, packaging micro-operations into an operation object identifier, an operation type and a dependency relationship, and storing the operation object identifier, the operation type and the dependency relationship. Comprising resource dependence, granularity dependence and business logic dependence; determining a lock execution path based on the operation object identifier, the operation type and the dependency relationship; constructing a dependency tensor model, performing conflict density mapping to form conflict density distribution, and performing tensor conflict operation on the microoperation in combination with a lock execution path to obtain a conflict intensity value; a high-conflict area is identified based on conflict density distribution, a potential deadlock graph is constructed, a micro-operation directed acyclic graph is generated, nodes with zero in-degree and out-degree are identified to form a first execution sequence, a second execution sequence is constructed according to residual micro-operations, a micro-operation execution sequence is formed through splicing, and efficient parallel scheduling and throughput capacity improvement are achieved.

The invention provides an instruction processing method and device, a chip product, computer equipment and a storage medium. The method comprises the following steps: in response to a received to-be-processed vector instruction, splitting the vector instruction into a plurality of microoperations respectively corresponding to a plurality of destination registers; the micro-operation is used for acquiring data access information required by the destination register corresponding to the micro-operation; executing each item of microoperation in parallel; triggering an execution unit to execute a calculation operation under the condition of determining that all the micro-operations are executed; wherein the execution unit, in response to the calculation operation, performs a vector operation on the plurality of destination registers based on the data access information acquired by all the micro-operations. The number of micro-operations can be greatly reduced, and the problem of pipeline blockage caused by the fact that a transmitting queue is filled is avoided.

The invention relates to the technical field of robot micro-operation, and discloses a micro-operation tail end system integrating multi-dimensional micro-force sensing and visual servo, which comprises a data acquisition module used for synchronously acquiring binocular visual images and six-dimensional force data; the calibration registration module is used for establishing a multi-sensor unified coordinate system; the visual pose estimation module is used for realizing three-dimensional reconstruction and feature point extraction based on a deep neural network and structured light; the state fusion estimation module fuses vision and force information through an extended Kalman filter and judges a contact state; the cooperative control module is used for generating a motion instruction in combination with task priority and impedance control; the parameter self-adaptive module is used for identifying materials on line and self-adaptively adjusting force control parameters; and the motion control module adopts active damping control to suppress vibration. According to the invention, high-precision and multi-degree-of-freedom micro-operation can be realized in a narrow and limited space.

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

This invention presents an enhanced micro-operation target segmentation method utilizing improved Otsu and edge operators, addressing the limitations of conventional techniques in microscopic visual environments. The proposed approach effectively mitigates accuracy constraints caused by image noise and shadow effects from uneven illumination. The methodology comprises three key phases: Applying an optimized bilateral filtering algorithm to perform noise reduction on grayscale images, producing denoised images; Segmenting micro-operation targets using the refined Otsu algorithm on these denoised images to obtain initial segmentation results; Directly applying the final segmentation result when meeting predefined criteria, or conducting iterative segmentation through the enhanced edge operator and Otsu algorithm if necessary. This innovative method demonstrates exceptional performance in micro-operation target detection applications

The invention provides a fusion instruction processor, which belongs to the technical field of processors and comprises a decoding module, a plurality of conflict detection modules, a first operation module and an instruction execution module, the decoding module carries out decoding operation on a fusion instruction to be sent to obtain each expected occupation moment, and the plurality of conflict detection modules obtain a conflict judgment result about whether a target hardware unit has a resource conflict according to the received expected occupation moments and an occupied moment sequence stored locally and send a control signal; and the first operation module determines whether to send the decoded fusion instruction to be sent according to the received control signal sent by each conflict detection module. According to the fusion instruction processor provided by the invention, the problem of resource conflict during operation of the processor is effectively avoided from the fine-grained level of each micro-operation of the fusion instruction and each hardware unit of the execution module, the operation efficiency is fully improved, the operation power consumption is reduced, the hardware performance is exerted, and the number of instructions executed per clock is greatly increased.

A method for parallel decoding which is applied to a processor including a first decoder cluster and a second decoder cluster, the second decoder cluster being provided with at least one shared decoder shared by the first decoder cluster. In the method, if a quantity of a plurality of instructions is greater than a quantity of decoders in the first decoder cluster, the processor assigns, from the plurality of instructions, first instructions with a quantity corresponding to the quantity decoders of the first decoder cluster to a decoder in the first decoder cluster for decoding, and the processor assigns, from the plurality of instructions, at least one second instruction other than the first instructions to the at least one shared decoder for decoding. The processor then writes micro-ops obtained by decoding the first instructions and micro-ops obtained by decoding the at least one second instruction into a first micro-op queue.

The invention provides a microcode generation method and system based on reinforcement learning, and relates to the technical field of data processing.The microcode generation method comprises the steps that a pre-trained reinforcement learning strategy model is adopted, a state feature vector represented in the middle of microcodes is extracted, action probability distribution is output, and a target action is selected based on the action probability distribution; according to the method and the system, the current micro-code intermediate representation is subjected to iterative updating, the model comprehensively balances the subsequent income in combination with the current state in the iterative updating process, and a better scheduling sequence can be gradually approached under the condition that the micro-operation dependency relationship and hardware resource competition coexist. Meanwhile, a better scheduling change operation is selected through iterative updating, so that unnecessary pauses and resource conflicts can be reduced, and the utilization efficiency of key execution resources is improved.

The present invention aims to provide a machine tool in which operability at the start of operation of a hydraulic actuator is improved during micro-operation of a lever. To this end, a machine body controller controls a pump discharge flow rate to a minimum discharge flow rate before a first timing is detected, to a predetermined discharge flow rate greater than the minimum discharge flow rate after the first timing is detected and before a second timing is detected, and to a discharge flow rate corresponding to an amount of operation of a lever after the second timing is detected, based on a signal from a first timing detection device and a signal from a second timing detection device.

A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.

An apparatus and method for efficient matrix processing in a clustered processor core. For example, one embodiment of a processor comprises: a front end to fetch and decode a plurality of instruction strands to generate a corresponding plurality of microoperations, including matrix processing microoperations; a reservation station to schedule the microoperations for execution in accordance with a first scheduling mode; out-of-order execution circuitry to execute the microoperations; and a detector to determine a density of the matrix processing microoperations within an interval and to signal to the reservation station to implement a second scheduling mode when the density of matrix processing microoperations reaches or exceeds a first threshold.

The application belongs to the field of information processing and is a unified memory allocation management method for AI training of a heterogeneous architecture, comprising the following steps: S1: collecting hardware counter indexes and software layer operator graph topology information, calculating the instantaneous performance power consumption ratio of each heterogeneous node, and generating a global resource atlas with a weight label; S2: identifying a high communication operator cluster based on the global resource atlas, mapping the required memory to a physically adjacent area, constructing a cross-chip virtual continuous address space, and dynamically migrating the load under the delay constraint according to the performance power consumption curve; S3: predicting the future survival period of a memory block by using a timing model, triggering lazy fragment compression only for the region predicted to be released, and inserting the arrangement micro-operation into the idle period of the computing core for execution; S4: collecting throughput, delay, energy consumption and fragment arrangement hit rate data, calculating a reward function, and updating the weight parameters of the timing model in real time, and dynamically switching the special sub-model strategy according to the characteristics of the current training stage.

The invention provides an intelligent monitoring method and system for switching operation of a transformer substation, and relates to the technical field of power grids. Multi-source sensing data such as SCADA signals, video data, temperature data, vibration data and environment data are collected in real time, a global rule engine and a process state engine are adopted for parallel study and judgment, switching operation is subjected to real-time multi-dimensional cross validation and deep analysis from the two dimensions of a macroscopic safety rule and a microcosmic operation process, and the real-time multi-dimensional cross validation and deep analysis are achieved. And the comprehensiveness and accuracy of risk identification are improved. And then strategy fusion is carried out based on a security priority principle, and an intelligent monitoring instruction including graded early warning and equipment locking is generated, so that differentiated and precise countermeasures are implemented for risks of different grades. By constructing an intelligent monitoring process integrating real-time sensing, intelligent analysis, strategy decision and accurate execution, the problem of safety risk existing in manual switching operation is solved, and the safety and intelligent level of switching operation of the transformer substation are improved.

The invention discloses an intelligent control method and system for an ophthalmic surgical robot, a prediction model and a cooperative control method, and belongs to the technical field of medical robots. The system comprises a 3D display system, an OCT information system, a micro-touch system, an information comprehensive processing system, a control system, a mechanical arm and special inner boundary membrane tweezers. The core of the method is that an augmented reality surgical navigation model is constructed through preoperative and intraoperative OCT data fusion; the micro-operation force is monitored in real time through the novel inner boundary membrane tweezers integrated with the FBG sensor; the visual sense information and the force sense information are fused through an information comprehensive processing system, and a personalized control strategy is generated based on a pre-trained deep learning decision model; and finally, the control system adopts a self-adaptive impedance control algorithm to drive the mechanical arm to execute accurate and smooth force-position closed-loop operation. The problems that in the ophthalmologic operation, the visual depth is lost, the tactile feedback is deficient, and the operation precision depends on the experience of doctors are solved, and the safety, the precision and the standardization level of the retina inbound membrane stripping operation can be remarkably improved.

Disclosed techniques enable vector instruction processing. A processor core is accessed. The processor core is coupled to a memory hierarchy, and is configured to execute vector operations, scalar operations, and micro-operations. A decode unit decodes a vector memory operation. The vector memory operation is associated with a unit stride addressing mode. The decoding includes dividing the vector memory operation into one or more vector memory micro-operations. A dispatch unit sends at least one vector micro-operation within the one or more vector micro-operations to a scalar request queue within a plurality of request queues. The at least one vector micro-operation is issued to a load-store unit within the processor core. The issuing includes selecting, from the plurality of request queues, the at least one vector memory micro-operation.

In one embodiment, an apparatus includes: a plurality of execution circuits to execute and instruct micro-operations (μops), where a subset of the plurality of execution circuits are capable of execution of a fused μop; a fusion circuit coupled to at least the subset of the plurality of execution circuits, wherein the fusion circuit is to fuse at least some pairs of producer-consumer μops into fused μops; and a fusion throttle circuit coupled to the fusion circuit, wherein the fusion throttle circuit is to prevent a first μop from being fused with another μop based at least in part on historical information associated with the first μop. Other embodiments are described and claimed.

This invention proposes a micro-operation decomposition module, processor, and electronic device. A numbering update unit provides the current micro-operation number to an element quantity counting unit and an execution module. The element quantity counting unit determines the current micro-operation element quantity based on the current micro-operation number and the reference information corresponding to the target vector instruction. The execution module executes the corresponding micro-operation based on the current micro-operation number, the current micro-operation element quantity, and decoding information. Performing micro-operations before instruction execution avoids excessive pipeline delays caused by micro-operations, enabling rapid response to instruction changes, accurate completion of micro-operations, and improved instruction processing efficiency, thus meeting the demands of high-performance computing.

This invention belongs to the field of space station scientific payload control, specifically a control system for a space station scientific glove box, comprising: a first main controller, a second main controller, a robotic arm control system, a microscopic operating system, a payload system, a power supply module, an environmental control sub-controller A, an environmental control sub-controller B, and a host resource panel operating system. The first and second main controllers receive instructions from the host controller, parse them into internal instructions, and control the corresponding subsystems to perform corresponding actions based on the destination address parameters in the internal instructions and the current operating mode of the first or second main controller. The second main controller also receives control instructions from the host resource panel operating system to control the corresponding subsystems to perform corresponding actions. Each subsystem in this invention is configured with an independent controller for easy individual debugging. After subsystem debugging, the entire system is integrated, optimizing the system integration process and shortening the system integration time.

The invention provides a configurable multi-protocol bus conversion method and device, and the method comprises the steps: obtaining a first protocol rule set corresponding to a source data protocol and a second protocol rule set corresponding to a target data protocol from a protocol description rule library based on a configuration instruction, and analyzing the source data communication command based on the first protocol rule set to obtain the intermediate micro-operation, converting the intermediate micro-operation based on the second protocol rule set to obtain the target data communication command, and transmitting the target data corresponding to the source data based on the target data communication command, thereby greatly improving the flexibility and IP reusability of the SoC design. Moreover, when a system bus architecture is changed or a protocol is upgraded, a hardware circuit does not need to be redesigned, and new protocol conversion can be realized only by configuring instruction switching or updating a rule set in a rule base, so that the design cost and verification period of a chip are remarkably reduced, and meanwhile, efficient compatibility of various heterogeneous bus protocols is realized.

The invention relates to a task scheduling method and device, computer equipment, a readable storage medium and a program product. The method comprises the following steps: receiving a tensor instruction distributed by a processor unit; querying the dependency check table, obtaining dependency check information of the tensor instruction, and performing dependency check according to the dependency check information; under the condition that the dependency check is passed, the tensor instruction is converted into a micro-operation control signal, and the micro-operation control signal is sent to the finite-state machine module, so that the finite-state machine module dispatches the processing unit module to execute tensor operation; and an execution completion signal fed back by the neural network acceleration unit after the tensor operation is completed is received, the dependency check table is updated, and an operation notification message is sent to the processor unit. By adopting the method, the processor unit can process other logic transactions in parallel or enter a low-power-consumption state while the neural network acceleration unit performs tensor operation, so that the overall throughput rate and the energy efficiency ratio of the heterogeneous system are remarkably improved.

The invention provides a special execution control device and control method for in-memory calculation. The control device comprises an instruction caching assembly used for receiving and caching batch bit operation instructions, a microprogram storage assembly used for caching microprograms, a microoperation code storage assembly used for storing a currently executed microoperation code sequence, an addressing assembly used for generating a DRAM row physical address, and a data processing assembly used for processing the DRAM row physical address. The register file component is used for storing a general register and control information, the counting component is used for recording the processing number of data blocks, the control component is used for decoding a microoperation code and controlling an execution process, and the counting control component is used for pointing to the currently executed microoperation code. According to the control device provided by the invention, through cooperative work of all the components, the execution process of in-memory calculation is optimized, the throughput and energy efficiency of the system are remarkably improved, and meanwhile, the control device has good flexibility and integration.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

Disclosed are techniques for macro-operation fusion. In an aspect, a method for macro-operation fusion comprises detecting that a plurality of macro-operations involving a first register is a fusible set of macro-operations comprising a first macro-operation to perform an arithmetic operation using a second register and a second macro-operation to perform the arithmetic operation using an immediate value, wherein the arithmetic operation is addition or subtraction. The method also comprises decoding the fusible set to one micro-operation that performs functions of the fusible set, and executing the one micro-operation that performs the functions of the fusible set. In some aspects, the detection, decoding, and executing steps may be performed by an instruction fetch unit, a decoder unit, and an execution unit, respectively, of a processor. In some aspects, the instruction fetch unit routes the fusible set of macro-operations to the same decoder unit from a plurality of available decoder units.

The invention discloses a vset class instruction splitting performance optimization method in RISC-V vector extension, and relates to the technical field of processors, comprising: splitting a vset class instruction into a first micro-operation and a second micro-operation in a decoding stage; the first microoperation enters a sequential transmitting queue and is used for setting vl and vtype CSR registers; the second microoperation enters an out-of-order transmitting queue and is used for writing the vl value back to the target register; the two microoperations are mutually independent, and the instruction is recovered only when the delivery state and the write-back state are both updated. According to the method, the vset instruction is divided into two micro-operations, CSR setting and a write-back result are decoupled, the second micro-operation is executed through the out-of-order transmitting queue, and the result is forwarded through the bypass network, so that data dependence of the vset instruction and a subsequent instruction is eliminated, pipeline pause is reduced, and the instruction level parallelism and the overall throughput rate of a processor are improved.

The invention relates to the technical field of electronic component assembly, in particular to a symmetric micro-operation device and a use method. The symmetrical micro-operation device comprises two groups of manipulators, and the two groups of manipulators are oppositely arranged and are positioned on the two sides of the welding station; the manipulator comprises a flexible clamping jaw, a supporting arm and a position and posture adjusting assembly. The flexible clamping jaw is provided with a driving assembly so that the flexible clamping jaw can conduct clamping or opening. The flexible clamping jaw is arranged at the front end of the supporting arm; the tail end of the supporting arm is connected to the position and posture adjusting assembly so that the relative position and angle of the flexible clamping jaw and the welding station can be adjusted through the position and posture adjusting assembly. Welding spots of the camera are divided into two columns, and each group of manipulators correspond to welding of one column, so that the situation that a column welded later is inconvenient to operate due to shielding of a column welded first is avoided.

Apparatus and methods for dependency tracking, chaining, and / or fusing for vector instructions. A system, processor, or integrated circuit includes a renamer to generate a valid bit mask for each micro-operation decoded from a first vector instruction, where the valid bit mask indicates what portion of a mask register to write and generate a dependency bit mask for each micro-operation decoded from a second vector instruction, where the dependency bit mask is based on a relationship between the first vector instruction and the second vector instruction, and an issue queue configured to issue for execution each micro-operation from the second vector instruction when an associated dependency bit mask is cleared based on execution of appropriate micro-operations from the first vector instruction.