199 results about "Micro-operation" patented technology

The embodiment of the invention provides an instruction processing method and device, a storage medium and an electronic device.The method comprises the steps that a first type of to-be-processed instructions are determined from multiple to-be-processed instructions according to preset instruction codes, and a first vector parameter is updated into a second vector parameter in an updating mode corresponding to the first type of to-be-processed instructions; and splitting a long vector instruction in other to-be-processed instructions into a plurality of micro-operations based on the second vector parameter, and renaming the other to-be-processed instructions according to the plurality of micro-operations, the other to-be-processed instructions being instructions except the first type of to-be-processed instructions in the plurality of to-be-processed instructions. According to the method and the device, the problem that an execution part circuit in a processor is too complex and too large in area and power consumption due to the appearance of a long vector in a vector instruction in the related technology is solved, and the effects of reducing the design complexity of the execution part circuit and realizing better processing frequency in a limited area are achieved.

The invention provides a memory access instruction processing method and a processor, and relates to the technical field of data processing, and the method comprises the following steps: splitting a target vector memory access instruction into a plurality of target vector memory access micro-operations based on a memory access width, combining the target scalar memory access instruction with at least one unexecuted scalar memory access instruction into a target scalar memory access micro-operation; executing each target vector memory access micro-operation, and / or executing a target scalar memory access micro-operation; the memory access width is determined based on a number of data cache banks in a data cache in the processor and a bit width of the data cache banks. According to the memory access instruction processing method and the processor provided by the invention, resources can be more reasonably allocated for vector memory access and scalar memory access during data memory access through splitting of the vector memory access instruction and merging of the scalar memory access instruction, and maximum resource sharing of the vector memory access and the scalar memory access is realized.

Apparatus and method for a quantum control processor. For example, one embodiment of a QCP comprises: instruction fetch logic to fetch instructions from a memory, the instructions including quantum instructions; decode logic to decode the quantum instructions into a first plurality of quantum microoperations; translation logic translate the first plurality of quantum microoperations into a second plurality of quantum microoperations based on characteristics of a plurality of quantum controller cores coupled to the quantum control processor; and issue logic to synchronously issue the second plurality of quantum microoperations in parallel to the plurality of quantum controller cores.

Embodiments are provided for converting a bit mask from a compressed format to an extended format. The bit mask is stored in a storage register in a compressed format. The compressed format does not include placeholder bits. The compressed format includes a single bit defining each element of a vector. The sizes of the elements can vary according to data types, for example, each element has 4, 8 and 16 bytes. In a single microoperation, the bitmask of the compressed format is converted to an extended format. The extended bit mask may be written to a predicate register. The extended bit mask includes a plurality of placeholder bits (the placeholder bits are not used in computation). The size of the extended bit mask corresponds to the size of the definition vector, including a plurality of elements of the data type. The extended bit mask may be used to execute an instruction. For example, a vector processor multiplies a sparse matrix with the vector using the extended bit mask.

A pipelined decoding microarchitecture design method for RISC-V vector instructions includes the following steps: S1, extracting an instruction packet according to a PC, performing preprocessing, and writing a preprocessing result, each instruction field and preprocessed instruction information into a cache; S2, reading the cache, obtaining pre-decoding result data and recognizing each configuration instruction; S3, transmitting the pre-decoding result data to an instruction buffer, and acquiring field information, a split quantity and predicted vtype information; and splitting each instruction into multiple microoperations, and constructing a queue to store each microoperation; and S4, transmitting first, by means of the queue, each configuration instruction, performing decoding and execution, acquiring vtype information generated after execution, and when the vtype information generated after execution is identical with the predicted vtype information, controlling the number of microoperations input to multiple decoders, and transmitting a decoding result to an instruction slot.

The invention discloses a nanoscale high-precision positioning method based on a multi-degree-of-freedom motion workbench, and relates to the field of large-stroke and high-precision positioning, and the method comprises the steps: S1, initializing the motion workbench, and guaranteeing that a system is in a zero position state; s2, sending a target position instruction by the upper computer, and driving the macro moving platform to quickly move to a position near a target; s3, acquiring the current position, calculating the deviation from the target position according to the target displacement and the current actual feedback displacement value, and generating micropositioner control parameters; s4, a control instruction is generated, and nanoscale displacement compensation is executed; and S5, iteratively correcting the displacement of the micropositioner until the deviation fed back by the laser interferometer meets the requirement. According to the invention, the positioning precision of large-stroke (hundred millimeters) movement is improved to a nanometer level, the device is suitable for the fields of photoetching machines, ultra-precision machining, biological micromanipulation and the like, and the equipment performance and the process level are improved. In addition, the system adopts a modular design, can adapt to different driving and sensing units according to requirements, and has strong expansibility.

Provided in the embodiments of the present disclosure are an instruction processing method and device, and a storage medium and an electronic device. The method comprises: on the basis of a preset instruction code, determining from among a plurality of instructions to be processed a first-type instruction to be processed; using an update mode corresponding to said first-type instruction to update a first vector parameter to a second vector parameter; and on the basis of the second vector parameter, splitting into a plurality of micro-operations a long vector instruction in the other instructions to be processed, and performing renaming processing on said other instructions on the basis of the plurality of micro-operations, wherein said other instructions are instructions among the plurality of instructions to be processed other than said first-type instruction. By means of the present disclosure, the problems in the related art of an execution part circuit in a processor being excessively complex and having an excessively large area and an enormous power consumption overhead due to the occurrence of a long vector in vector instructions are solved.

Enabling high-performance Scalable Matrix Extension (SME) instruction issue in processor devices is disclosed herein. In some aspects, a processor device comprises a reservation station circuit configured to perform, during a first phase, a reduced-precision vector accumulator (ZA) tracking operation on micro-ops for which corresponding vector (Z) registers and corresponding predicate (P) registers are ready. Based on the reduced-precision ZA tracking operation, the reservation station circuit selects a first micro-op and a second micro-op having no Read-After-Write (RAW) hazard with respect to the ZA registers. During a subsequent second phase, the reservation station circuit performs a full-precision ZA tracking operation on the first micro-op and the second micro-op, and selects one as a micro-op for issue for which the full-precision ZA tracking operation indicates no RAW hazard exists with respect to the ZA registers. The reservation station circuit then issues the selected micro-op for execution.

A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector instructions, scalar instructions, and micro-operations. A dispatch unit within the processor core receives a vector memory operation. The dispatch unit sends the vector memory operation to a first vector input queue of multiple vector input queues. The sending is based on the memory addressing mode. A micro-operation sequencer splits the vector memory operation into one or more memory micro-operations, which includes forwarding each micro-operation within the one or more micro-operations to a first memory queue within multiple memory queues. A memory operation is then issued to a load-store unit within the processor core. The issuing includes selecting, from the multiple memory queues, the memory operation. The vector memory operation comprises either a vector load operation or a vector store operation.

The invention provides a parallel structure micro-operation robot parameter calibration method based on microscopic vision, and belongs to the technical field of robot parameter calibration, the method mainly uses a microscopic camera to amplify the motion of an end effector of a micro-operation robot, obtains the position of the end effector through image processing, and determines the position of the end effector according to a kinematics analysis result. Kinematics parameters are obtained through calculation, and then the motion precision of the micro-operation robot is measured. The method mainly comprises the following steps of parallel structure robot modeling and kinematics analysis, camera correction, proportional scale determination, robot orthogonality correction, parameter calibration, repeated positioning precision measurement, translation precision measurement and rotation precision measurement. According to the method, the problem of kinematics parameter calibration of the parallel structure micro-operation robot is solved, calibration of the kinematics parameters under the high-precision requirement is achieved, and the kinematics precision of the micro-operation robot is improved.

The invention discloses an instruction splitting method and device, electronic equipment, a storage medium and a computer program product. The method comprises the steps that a target instruction set and first information are obtained, the target instruction set comprises one or more to-be-split instructions and second information of each to-be-split instruction, and the first information comprises related information of a hardware structure of a target processor; the second information is at least used for indicating first input data and first output data of the to-be-split instruction; aiming at each to-be-split instruction contained in the target instruction set, based on the second information, splitting the to-be-split instruction into a plurality of micro-operations, and enabling second input data and second output data of each micro-operation to meet a first condition which is associated with a hardware structure of the target processor.

An automatic end effector tip position initialization mechanism for a micromanipulation system is provided. The method includes: S1, positioning a macro end effector tip, calculating a camera pose by using ArUco Tag, and realizing a three-dimensional positioning of the end effector tip by using a triangulation method, and moving the end effector to a area near a center of a focal plane based on a visual servo; S2, positioning a micro end effector tip; S3, acquiring calibration data based on a visual servo, calibrating the end effector tip and the petri dish, and obtaining a left calibration matrix and a right calibration matrix reflecting the transformation relationship between left and right micromanipulator coordinates and image coordinates; generating an intuitive human-computer interaction interface based on a mouse and a keyboard according to acquired position information. The method has obvious advantages in terms of operation accuracy, operation efficiency and repeatability.

Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method includes: generating an instruction fetch request carrying at least one switching flag, in which the switch tag at least indicates an instruction position for performing decoder group switch; acquiring an instruction stream fetched by the instruction fetching request in response to a micro-op being obtained as decoded by decoder group, and determining the instruction position for performing decoder group switch in the instruction stream according to the switch tag carried by the instruction fetching request; allocating the instruction steam to a plurality of decoder groups for parallel decoding according to the instruction position; and attaching the switch tag to a target micro-op obtained by decoding a targe instruction, in which the target instruction is an instruction corresponding to the instruction position.

The embodiment of the invention provides a multi-account concurrent processing management system and a multi-account concurrent processing management method, which are applied to the technical field of multi-account high-concurrency business processing, and are used for analyzing a plurality of received account operation requests into a micro-operation set, packaging micro-operations into an operation object identifier, an operation type and a dependency relationship, and storing the operation object identifier, the operation type and the dependency relationship. Comprising resource dependence, granularity dependence and business logic dependence; determining a lock execution path based on the operation object identifier, the operation type and the dependency relationship; constructing a dependency tensor model, performing conflict density mapping to form conflict density distribution, and performing tensor conflict operation on the microoperation in combination with a lock execution path to obtain a conflict intensity value; a high-conflict area is identified based on conflict density distribution, a potential deadlock graph is constructed, a micro-operation directed acyclic graph is generated, nodes with zero in-degree and out-degree are identified to form a first execution sequence, a second execution sequence is constructed according to residual micro-operations, a micro-operation execution sequence is formed through splicing, and efficient parallel scheduling and throughput capacity improvement are achieved.

The invention provides an instruction processing method and device, a chip product, computer equipment and a storage medium. The method comprises the following steps: in response to a received to-be-processed vector instruction, splitting the vector instruction into a plurality of microoperations respectively corresponding to a plurality of destination registers; the micro-operation is used for acquiring data access information required by the destination register corresponding to the micro-operation; executing each item of microoperation in parallel; triggering an execution unit to execute a calculation operation under the condition of determining that all the micro-operations are executed; wherein the execution unit, in response to the calculation operation, performs a vector operation on the plurality of destination registers based on the data access information acquired by all the micro-operations. The number of micro-operations can be greatly reduced, and the problem of pipeline blockage caused by the fact that a transmitting queue is filled is avoided.

The invention relates to the technical field of robot micro-operation, and discloses a micro-operation tail end system integrating multi-dimensional micro-force sensing and visual servo, which comprises a data acquisition module used for synchronously acquiring binocular visual images and six-dimensional force data; the calibration registration module is used for establishing a multi-sensor unified coordinate system; the visual pose estimation module is used for realizing three-dimensional reconstruction and feature point extraction based on a deep neural network and structured light; the state fusion estimation module fuses vision and force information through an extended Kalman filter and judges a contact state; the cooperative control module is used for generating a motion instruction in combination with task priority and impedance control; the parameter self-adaptive module is used for identifying materials on line and self-adaptively adjusting force control parameters; and the motion control module adopts active damping control to suppress vibration. According to the invention, high-precision and multi-degree-of-freedom micro-operation can be realized in a narrow and limited space.

Apparatus and methods for tracking sub-micro-operations and groups thereof are described. An integrated circuit includes a load store unit configured to receive store micro-operations cracked from a vector store instruction. The load store unit is configured to unroll multiple store sub-micro-operations from each of the store micro-operations. The load store unit includes an issue status vector to track issuance of each sub-micro-operation, an unroll status vector to track unrolling of each sub-micro-operation associated with a group of sub-micro-operations, and a replay status vector to track a replayability of sub-micro-operations associated with the group of sub-micro-operations.

A string operation method, string operation device, and storage medium are disclosed. The method comprises: obtaining a unit operation width corresponding to the type of string operation; obtaining a processing data width for the target data to be operated; obtaining a number of repeated operations of the string operation on the target data; determining mask information based on the unit operation width, the processing data width, and the number of repeated operations; and writing the operation portion to a target address based on the mask information. This method effectively improves the execution speed of string operation instructions, reduces the number of micro-operations during the execution of string operation instructions, and increases the utilization of processor hardware resources.

The invention discloses a global nerve drawing method and system based on a programmable rasterization engine, and belongs to the technical field of computer graphics, and the method comprises the steps: at the programmable rasterization engine, analyzing a rasterization descriptor according to a rasterization instruction, and extracting vector microoperation and control parameters; maintaining a task state machine according to the parameters and distributing a control signal, selecting an execution entry from a vector kernel table according to the control signal, and instantiating an operation into a parallel vector thread; in a vector thread execution process, tracking data dependence of a vector register and a synchronization state of a direct memory access unit, executing vector loading / storage operation so as to carry data between the register and an on-chip shared memory according to the data dependence and the synchronization state, and dynamically scheduling vector micro-operation to an execution component so as to complete rasterization calculation; and outputting a result to the neural rendering network to complete global neural rendering. According to the method, the multi-representation neural rendering load can be uniformly and efficiently supported on the AI accelerator, the memory access overhead is remarkably reduced, and the calculation efficiency is improved.

Apparatus and methods for processing of a vector load or store micro-operation with mask information as a no-operation (no-op) when a mask vector for the vector load or store micro-operation has all inactive mask elements or processing vector load or store sub-micro-operation(s) with active mask element(s) are described. An integrated circuit includes a load store unit configured to receive load or store micro-operations cracked from a vector load or store operation, determine that a mask vector for the vector load or store micro-operation is fully inactive, and process the vector load or store micro-operation as a no-operation. If the mask vector is not fully inactive, the vector load or store micro-operation is unrolled into vector load or store sub-micro-operation(s) which have active mask element(s). Vector load or store sub-micro-operation(s) which have inactive mask element(s) are ignored.

This invention presents an enhanced micro-operation target segmentation method utilizing improved Otsu and edge operators, addressing the limitations of conventional techniques in microscopic visual environments. The proposed approach effectively mitigates accuracy constraints caused by image noise and shadow effects from uneven illumination. The methodology comprises three key phases: Applying an optimized bilateral filtering algorithm to perform noise reduction on grayscale images, producing denoised images; Segmenting micro-operation targets using the refined Otsu algorithm on these denoised images to obtain initial segmentation results; Directly applying the final segmentation result when meeting predefined criteria, or conducting iterative segmentation through the enhanced edge operator and Otsu algorithm if necessary. This innovative method demonstrates exceptional performance in micro-operation target detection applications

The invention provides an electronic device and a method for managing microoperation. In an embodiment, the method comprises: when a processing unit executes a translation instruction, determining, by the processing unit, whether a microoperation corresponding to the translation instruction is stored in a translation buffer and a microoperation cache; when the microoperation corresponding to the translation instruction is not stored in the translation buffer area and the microoperation cache, outputting a specific microoperation by the processing unit to enter a system management mode; translating, by the processing unit, the translation instruction into a micro-operation corresponding to the translation instruction in a management mode; and storing, by the processing unit, a microoperation corresponding to the translation instruction in a microoperation cache.

The invention provides a fusion instruction processor, which belongs to the technical field of processors and comprises a decoding module, a plurality of conflict detection modules, a first operation module and an instruction execution module, the decoding module carries out decoding operation on a fusion instruction to be sent to obtain each expected occupation moment, and the plurality of conflict detection modules obtain a conflict judgment result about whether a target hardware unit has a resource conflict according to the received expected occupation moments and an occupied moment sequence stored locally and send a control signal; and the first operation module determines whether to send the decoded fusion instruction to be sent according to the received control signal sent by each conflict detection module. According to the fusion instruction processor provided by the invention, the problem of resource conflict during operation of the processor is effectively avoided from the fine-grained level of each micro-operation of the fusion instruction and each hardware unit of the execution module, the operation efficiency is fully improved, the operation power consumption is reduced, the hardware performance is exerted, and the number of instructions executed per clock is greatly increased.

A method for parallel decoding which is applied to a processor including a first decoder cluster and a second decoder cluster, the second decoder cluster being provided with at least one shared decoder shared by the first decoder cluster. In the method, if a quantity of a plurality of instructions is greater than a quantity of decoders in the first decoder cluster, the processor assigns, from the plurality of instructions, first instructions with a quantity corresponding to the quantity decoders of the first decoder cluster to a decoder in the first decoder cluster for decoding, and the processor assigns, from the plurality of instructions, at least one second instruction other than the first instructions to the at least one shared decoder for decoding. The processor then writes micro-ops obtained by decoding the first instructions and micro-ops obtained by decoding the at least one second instruction into a first micro-op queue.

A method for identifying and locating a micro-operation object under deflection and occlusion belongs to the technical field of micro-operation object identification and positioning under microscopic vision. The present invention solves the problem of low positioning accuracy of micro-operation objects by existing methods when the micro-operation object is deflected and occluded. The present invention specifically comprises the following steps: graying and denoising the original image where the micro-operation object is located to obtain a denoised image; performing wavelet decomposition on the denoised image to obtain a downsampled image; extracting feature points from the downsampled image and the micro-operation object template image respectively, and describing the feature points; matching the feature points in the downsampled image and the micro-operation object template image to obtain a coarse matching feature point pair, and then screening the feature point pairs obtained by the coarse matching to obtain a fine matching feature point pair; and obtaining the operation point coordinates of the micro-operation object in the original image based on the fine matching result. The method of the present invention can be applied to the identification and positioning of micro-operation objects.

The invention relates to a circuit and a method for enhancing performance monitoring. An apparatus includes a first set of execution circuits of a first type; a second set of execution circuits of a second type different from the first type; a distribution circuit to distribute a first set of one or more ports for a first set of execution circuits of the first type and to distribute a second set of one or more ports for a second set of execution circuits of the second type; and a performance monitor circuit to generate a first value and a second value, the first value indicating a first number of ports of the first set of one or more ports that delay the push-out of ready-to-execute microoperations of the first type to a first set of execution circuits of the first type due to busy execution of another microoperation of the first type, and the second value indicating a second number of ports of the first set of one or more ports of the first set of execution circuits of the first type, and the second value indicates a second number of ports of the second set of one or more ports that delay the push-out of ready-to-execute microoperations of the second type to a second set of execution circuitry of the second type due to busy execution of another microoperation of the second type.

The invention provides a microcode generation method and system based on reinforcement learning, and relates to the technical field of data processing.The microcode generation method comprises the steps that a pre-trained reinforcement learning strategy model is adopted, a state feature vector represented in the middle of microcodes is extracted, action probability distribution is output, and a target action is selected based on the action probability distribution; according to the method and the system, the current micro-code intermediate representation is subjected to iterative updating, the model comprehensively balances the subsequent income in combination with the current state in the iterative updating process, and a better scheduling sequence can be gradually approached under the condition that the micro-operation dependency relationship and hardware resource competition coexist. Meanwhile, a better scheduling change operation is selected through iterative updating, so that unnecessary pauses and resource conflicts can be reduced, and the utilization efficiency of key execution resources is improved.

The present invention aims to provide a machine tool in which operability at the start of operation of a hydraulic actuator is improved during micro-operation of a lever. To this end, a machine body controller controls a pump discharge flow rate to a minimum discharge flow rate before a first timing is detected, to a predetermined discharge flow rate greater than the minimum discharge flow rate after the first timing is detected and before a second timing is detected, and to a discharge flow rate corresponding to an amount of operation of a lever after the second timing is detected, based on a signal from a first timing detection device and a signal from a second timing detection device.

A vector processing unit contains an operation cache and a separate micro-op cache. The operation cache tracks state and logic of instructions, and is responsible for splitting instructions into micro-ops. The micro-op cache tracks state and logic of micro-ops. Having a separate micro-op cache provides power and area benefits, as well as allowing instructions to be split out of order.