A Circuit for reducing the number of
serial ATA external
PHY signals includes: a
serializer / deserializer, connected to a storage medium controller through a set of parallel
signal transmitting lines and a set of parallel
signal receiving lines, so as to convert signals between parallel and serial specifications; a
phase locked loop, connected to the
serializer / deserializer so as to generate a
clock signal required for
data signal transmission; at least one pair of
transmitter and
receiver, each connected to the
serializer / deserializer, each
transmitter able to transmit the serial
data signal from the serializer through a set of serial signal transmitting lines to a
serial ATA device, and each
receiver able to receive the serial data from the
serial ATA device through a set of serial signal receiving lines to the deserializer; and at least one OOB
signal detector, each connected to the corresponding receiving lines, so as to detect the out of band signals from the serial ATA device. The Circuit also employs in certain applications a
signal encoding approach for reducing the number of serial ATA external
PHY signals, wherein an
encoder and a decoder are employed to
encode control signals and status signals into special data codes transmitted between a serial ATA external
PHY and a storage medium controller, so as to minimize the number of interface signals.