414 results about "PHY" patented technology

Various aspects of the present disclosure generally relate to wireless communication. Some aspects more specifically relate to configuration of downlink and / or uplink quality of service (QoS) based radio link monitoring and prediction and related signaling and procedures. In some aspects, a network node may configure a user equipment (UE) with set(s) of physical (PHY) and / or medium access control (MAC) parameters for QoS radio link monitoring and reporting. Once configured with the parameter sets, the UE may receive a signal from the network node to use a particular set, or may autonomously select a set using traffic requirements. The network node may schedule the UE to send a QoS report in accordance with one or more downlink or uplink measurement and / or prediction results. For example, when the monitored results exceed one or more configured threshold(s), the UE may transmit a report to the network node.

A method, an apparatus, a terminal, and a medium for processing a sidelink consistent listen before talk failure, are provided. The method for processing a sidelink consistent listen before talk (LBT) failure includes: determining, by a terminal, that the sidelink consistent LBT failure is triggered on a first resource; and performing, by the terminal, a first operation, where the first operation includes at least one of the following: resource selection or resource reselection or resource switching; determining that the first resource is recovered from the sidelink consistent LBT failure, or canceling the sidelink consistent LBT failure triggered on the first resource; and a Media Access Control (MAC) layer of the terminal informs a PHYsical (PHY) layer: the first resource is recovered from the sidelink consistent LBT failure, or canceling the sidelink consistent LBT failure triggered on the first resource.

A communication method includes: sending a first poll frame, where the first poll frame is for triggering ranging measurement in a first range-measurement cycle, the first poll frame further indicates a first parameter set that takes effect in the first range-measurement cycle, and the first parameter set includes one or more of the following parameters: a first narrowband physical layer (PHY) parameter, a first narrowband channel allow list, a first ranging block structure parameter, or a first ultra-wideband (UWB) multi-millisecond (MMS) ranging configuration parameter; and receiving a response frame of the first poll frame. According to the present disclosure, an initiator uses a poll frame to indicate a parameter set that takes effect in a current range-measurement cycle.

Methods, apparatus and systems for wireless sensing are described. In one example, a described system in a wireless data communication network comprises: a transmitter configured to transmit a time series of at least one wireless sounding signal (WSS) based on a standard wireless network protocol associated with the wireless data communication network, and a receiver. The wireless data communication network comprises a physical (PHY) layer, a medium access control (MAC) layer, and at least one higher layer. The receiver is configured to: receive the time series of at least one WSS (TSWSS) based on the standard wireless network protocol through a wireless channel of a venue, and perform a plurality of wireless sensing measurements based on the received TSWSS to obtain sensing measurement results based on the standard wireless network protocol. The PHY layer or the MAC layer of the receiver provides the sensing measurement results locally to the at least one higher layer of the receiver based on the standard wireless network protocol. The sensing measurement results are available to the at least one higher layer of the receiver for performing a sensing-based task based on the sensing measurement results.

Procedures, methods, architectures, apparatuses, systems, devices, and computer program products directed physical layer signaling in a wireless local area network system are provided. Among the methods is a method that may include any of generating an extremely high throughput (EHT) physical (PHY) layer protocol data unit (PDU) (PPDU) based on a PPDU format defining a preamble comprising (i) a fixed duration universal signaling (U-SIG) field, (ii) an EHT signaling (EHT-SIG) field, and (iii) an EHT short training field (EHT-STF), wherein the U-SIG and EHT-SIG fields respectively comprise an extra signaling indicator and extra signaling to support a third feature; and transmitting the U-SIG and EHT-SIG fields on a first bandwidth segment, followed by the EHT-STF on any of the first bandwidth segment and a second bandwidth segment, followed by (iii) an EHT data field on any of the first and second bandwidth segments.

Disclosed are techniques for wireless communication. In an aspect, a method performed by a receiving entity includes: receiving, from a transmitting entity, a first physical layer identity matrix (PHY ID) for the transmitting entity; receiving, from the transmitting entity, an encrypted ranging message; calculating a second PHY ID for the transmitting entity based on the encrypted ranging message; and authenticating the encrypted ranging message based on a comparison of the first PHY ID and the second PHY ID. Upon determining that the encrypted ranging message is authentic, the encrypted ranging message is decrypted to produce a decrypted ranging message and processing the decrypted ranging message. In some aspects, upon determining that the encrypted ranging message is not authentic, the encrypted ranging message is not processed (e.g., ignored or discarded). In some aspects, the receiving entity rejects further signal transmission and ranging procedures with the device thereby preventing successful attack.

The invention relates to a clock management structure, a system on chip and electronic equipment, and the clock management structure comprises a phase-locked loop and an arbitration frequency division module connected with the phase-locked loop. The phase-locked loop is deployed in the PHY; the phase-locked loop is used for generating a phase-locked loop clock of X channels according to an externally input clock signal; the arbitration frequency division module is used for processing the phase-locked loop clocks of the X channels to generate an MAC interface clock, and synchronizing the MAC interface clock to an MAC interface and a port corresponding to each channel; wherein X represents the total number of channels corresponding to a plurality of ports between the PHY and the MAC. According to the clock management structure, the cross-clock domain design in the SoC design is greatly reduced, and the clock structure in the SoC is simplified, so that the area of the SoC chip is reduced.

Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

The invention discloses a printed circuit board, a layout method thereof and a vehicle, and relates to the technical field of printed circuit board layout. The method comprises the following steps: connecting a capacitor in series on a differential signal line of a physical layer chip; carrying out hollowing processing on the adjacent layer corresponding to the pin bonding pad based on a preset hollowing strategy; carrying out region division on the inner layer of the printed circuit board so as to divide the inner layer into a plurality of different regions; a plurality of backflow via holes are formed beside layer changing via holes of a circuit of the printed circuit board based on a preset setting strategy, and the backflow via holes are used for providing layer changing channels for backflow currents of the circuit on a reference plane when layers of the circuit are changed. By implementing the PCB design measures of capacitor series filtering, pad adjacent layer hollowing, inner layer segmentation and isolation and backflow via hole optimization, the problem that electromagnetic compatibility radiation and conducted emission exceed the standard due to PHY circuit filtering loss, impedance mismatch, power ground noise coupling and unreasonable high-speed signal backflow path in the traditional TBOX design is effectively solved.

The application provides a multi-bin temperature monitoring system and method in the technical field of chemical component storage, which comprises a communication acquisition board and a plurality of temperature acquisition boards; the communication acquisition board comprises a first MCU, an Ethernet interface, a PHY chip, a memory, a plurality of fire-fighting IO ports and a plurality of first communication interfaces; the temperature acquisition board comprises a second MCU, a second communication interface, a plurality of ADC chips and a plurality of temperature sensors; the first MCU is connected with the PHY chip, the memory, the fire-fighting IO ports and the first communication interfaces respectively; the Ethernet interface is connected with the PHY chip; each first communication interface is connected with a plurality of second communication interfaces respectively; one end of each ADC chip is connected with the second MCU, and the other end is connected with a plurality of temperature sensors. The application has the advantages of greatly reducing the temperature monitoring cost and greatly improving the production line expandability.

A communication device communicates a physical (PHY) frame including a preamble and a data field. The preamble includes a Legacy Short Training Field (L-STF), a Legacy Long Training Field (L-LTF), a Legacy Signal Field (L-SIG), an EHT (Extremely High Throughput) Signal Field (EHT-SIG-A), an EHT Short Training Field (EHT-STF), and an EHT Long Training Field (EHT-LTF), and the EHT-SIG-A includes at least one subfield indicating that the communication device performs communication in a frequency band more than 160 MHz.

The application discloses a reset circuit and a vehicle-mounted Ethernet PHY chip reset system. The reset circuit comprises an Ethernet SWITCH unit, an MCU unit, a PHY chip unit and a reset chip unit. The Ethernet SWITCH unit is connected with a plurality of the PHY chip units. The plurality of the PHY chip units are connected with the reset chip unit. The Ethernet SWITCH unit is connected with the MCU unit. The MCU unit is connected with the reset chip unit. The reset circuit provided by the application can be reset in multiple ways. The reset circuit provided by the application has improved reliability, functionality and flexibility in a vehicle-mounted environment.

The present disclosure provides techniques to enhance privacy and security for wireless communications involving vendor-specific physical layer (PHY) extensions. A client device generates an obfuscated vendor identifier (ID) by applying one or more transformation functions to a real vendor ID. The client device generates an encrypted message, where the encrypted message comprises obfuscation data, which, when used, converts the obfuscated vendor ID into the real vendor ID. The client device transmits the encrypted message to an access point (AP). The client device transmits a data packet containing the obfuscated vendor ID to the AP.

User equipment includes a transceiver configured to transmit and receive signals over an air interface, a memory configured to store executable instructions, a processor configured to execute instructions stored in the memory. The processor executes the instructions to measure characteristics of uplink channels of the air interface at a first physical (PHY) layer and a second PHY layer. The processor also executes instructions to selectively route data from a packet data convergence protocol (PDCP) layer to one or more of a first radio link control (RLC) layer associated with the first PHY layer and a second RLC layer associated with the second PHY layer based upon the characteristics of the uplink channels.

The invention discloses a method for improving decoding robustness of an MIPI A-PHY (Mobile Industry Processor Interface A-Physical Layer) cable, and belongs to the field of high-speed serial buses. The method comprises the following steps: in a process of establishing a signal link between a local end and an opposite end, periodically sending a 01 sequence with a fixed length and a fixed format by a sending end, and recording the 01 sequence as a first sequence; and in the stage of establishing the double-end signal link, the receiving end continuously detects the received code stream, and when the receiving end continuously detects that the number of times of the first sequence reaches a preset threshold value thresholdA, the double-end signal link work is completed. Compared with a cable link algorithm which does not limit adjacent detection intervals, the algorithm provided by the invention has the advantages that the cable link judgment standard is improved, the occurrence of misrecognition caused by poor signal quality is effectively avoided, a foundation is laid for subsequent decoding operation, the credibility of real data after decoding is improved, the realizability on a hardware circuit is high, and the method is suitable for popularization and application. The method has high configurability, and improves the degree of adaptation to different link detection environments.

The invention discloses a universal control module, which belongs to the technical field of industrial field control and comprises a Loongson 2K0300 processor, a DDR4 (Double Data Rate 4) memory bus, a CAN (Controller Area Network) bus interface, a network PHY (Physical Layer) chip, an Ethernet interface, an Ethercat slave station interface, an Ethercat controller, a network transformer, an RS232 transceiver, a transceiver LTM2881 and an LCD (Liquid Crystal Display) interface. The Loongson 2K0300 processor comprises a memory controller, a CAN controller, an Ethernet controller and a UART controller. And the network PHY chip is connected with the Ethernet interface. And the Loongson 2K0300 processor, the Ethercat controller, the network transformer and the Ethercat slave station interface are sequentially communicated with one another. And the UART controller is communicated with the RS232 transceiver. And the UART controller is connected with the transceiver LTM2881 through a pin 1 and a pin 2 of the UART. The universal control module provided by the invention not only can be used as a subsystem single machine to realize corresponding functions in a relatively complex comprehensive control system, but also can independently realize the goal of comprehensive control of the system in small and medium-sized control systems, and realizes the balance of cost and power consumption and the high-efficiency cost ratio of simplicity and easiness in use.

Embodiments of the present disclosure provide a data packet sending method, and a data packet receiving method, an electronic device, and a computer program product. A first MAC sends a first instruction notification to a first PHY, the first instruction notification being used for instructing the first PHY to send a PPDU by means of a non-primary channel access mode.

The invention discloses a PCIe link state monitoring system and a monitoring method thereof. The PCIe link state monitoring system comprises a PCIe monitoring subsystem, a PCIe controller subsystem and a PHY (Physical Layer) module, wherein the PCIe controller subsystem and the PHY module are connected through a PIPE interface, and the PCIe monitoring subsystem is used for monitoring state information of a PCIe link; four levels of leaky bucket modules are integrated on the same layer of the PCIe monitoring subsystem, and the four levels of leaky bucket modules are used for dropping correctable error information in the state information of the PCIe link into leaky buckets, carrying out overflow counting to obtain leaky bucket overflow times, carrying out error pattern recognition according to the leaky bucket overflow times and preset different execution thresholds, and outputting the error pattern recognition result. Link recovery is carried out by adopting a progressive link recovery strategy; therefore, extra special equipment does not need to be introduced into the PCIe link, the observability of the PCIe link can be improved, and correctable errors caused by the signal integrity problem on the link can be analyzed and diagnosed in real time, so that a corresponding link recovery strategy is adopted.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

The invention discloses a long-distance port expansion device based on a multi-port PHY chip, and the device comprises a near-end device which is integrated with a multi-channel serial interface supporting a multi-port protocol; the remote equipment comprises at least one PHY (Physical Layer) chip, and the PHY chip is provided with an uplink multi-channel protocol interface supporting a multi-port protocol and is provided with a plurality of downlink network ports; and the multi-channel serial interface of the near-end equipment is connected with the uplink multi-channel protocol interface of the PHY chip through a long-distance transmission medium. According to the invention, the port access and data forwarding functions of a traditional switch (including a switch realized by a switch chip or a processor) are directly replaced by the far-end multi-port PHY, and the method is suitable for various network communication scenes sensitive to network cost, time delay and architecture complexity.

Embodiments include an automatic set top box placement (STB) process and system that balances video playback needs against the performance characteristics of individual devices and the communications system. For video playback, this involves maintaining required sustained data rates needed to support video of various levels of quality and resolution and matching these against the capacity of the Wi-Fi system in terms of channel capacity and gateway / Access Point to STB connection quality. An intelligent network controller calculates the STB total airtime. Each STB is associated with a Service Set Identifier (SSID) that the controller uses to identify the STB clients. The controller calculates the End-to-End PHY rates for each client. The total STB airtime can then be calculated and compared to the default allocation for the STBs. Recommendations regarding moving STBs, gateways, and or satellite / booster devices can then be provided to the user.

The application provides a vehicle-mounted Ethernet communication plug-in. The plug-in comprises an MCU unit, a switching chip, a PHY chip, a high-speed signal connector and a power connector. The MCU unit is configured to configure and manage the switching chip. The switching chip is connected with the PHY chip, the high-speed signal connector and the power connector, and is configured to provide at least two gigabit Ethernet interfaces and at least nine first hundred megabit Ethernet interfaces. One of the two gigabit Ethernet interfaces provides DC48V standard POE power supply externally through the power connector, and the other one of the two gigabit Ethernet interfaces is connected with a vehicle-mounted main control unit through the high-speed signal connector. The at least nine first hundred megabit Ethernet interfaces are respectively connected with one service unit through the high-speed signal connector.

A memory device includes a physical layer (PHY) interface, and a memory cell array. The PHY interface includes a phase adjusting circuit configured to generate a plurality of phase-shifted clock signals and a phase-shifted training clock signal based on a clock signal and configured to delay the clock signal based on a plurality of comparison signals output from a comparator, the comparator configured to compare training data with each of a first reference voltage and a second reference voltage based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal to output the plurality of comparison signals, the plurality of comparison signals including first comparison signals based on the plurality of phase-shifted clock signals, and second comparison signals based on the plurality of phase-shifted clock signals and the phase-shifted training clock signal, and a decoder configured to perform a duo-binary decoding on the first comparison signals.

A wireless network device configured to monitor multiple channels for clear channel assessment (CCA) is disclosed. The receiver circuit of the network device includes at least one CCA block for indicating whether a particular channel is clear. In some embodiments, the network device sequentially checks each channel and transmits at least one data packet if both channels are clear. The at least one data packet can include a mode switch data packet and a second data packet transmitted using a new PHY mode. The network device can also have multiple CCA blocks. In this case, the channels can be checked simultaneously and the network device transmits at least one data packet if both channels are clear. Alternatively, the network device simultaneously monitors multiple channels and selects one of the channels to transmit a preferred PHY mode on that channel, thereby avoiding the need for a mode switch data packet.

This invention discloses an FPGA-based visible light Ethernet rate-adjustable communication method and system, relating to the field of visible light communication equipment technology. It includes: an off-chip PHY chip, a MAC core, and an FPGA rate conversion and flow control module connected sequentially. The FPGA rate conversion and flow control module is connected to both an FPGA transmit control module and an FPGA receive control module. The FPGA transmit control module and the FPGA receive control module are connected to transceiver circuits, which are then connected to an LED and a photodiode, respectively. This invention addresses the need for visible light-Ethernet communication interface conversion, deeply integrating visible light communication with Ethernet access technology, while simultaneously solving the problem of the traditional single rate of visible light Ethernet, thus broadening the application scenarios of visible light communication.

The utility model discloses a high definition interactive fusion type set top box, it includes PON module, DVB module, optical communication module, first interface module, network state indicating lamp, first memory, second interface module, power indicating lamp and second memory, PON module and DVB module pass through internal PHY communication circuit communication, integration in a equipment, optical communication module, first interface module, network state indicating lamp and first memory all are connected to PON module, and second interface module, power indicating lamp and second memory all are connected to DVB module, PON module adopts the chip of RTL9603C type and realizes, DVB module adopts the chip of MC2416 type and realizes, the high definition interactive fusion type set top box of the utility model, through with PON module and DVB module integration in a equipment, and together through internal PHY layer connection, has improved operating speed, has improved user experience and reduced user cost.

The invention relates to the technical field of satellite communication, in particular to an end-to-end network system and a serving cell switching method and device. According to the serving cell switching method, the system comprises a gNB-control plane CP, at least one gNB-user plane DP, a first satellite and a second satellite, the first gNB-control plane CP is arranged on the first satellite, the at least one gNB-user plane DP is arranged on the second satellite, and the gNB-user plane DP is arranged on the second satellite. The gNB-control plane CP is connected with the at least one gNB-user plane DP through an interstellar link wireless resource interface, the satellite height of the first satellite is greater than the satellite height of the second satellite, and a base station RRC layer protocol stack function is deployed on the gNB-control plane CP. And any gNB-user plane DP in the at least one gNB-user plane DP is deployed with a base station PHY (Physical Layer) and L2 protocol stack function. According to the invention, the switching efficiency and the continuity of network services can be improved, and the application range of the system and the transmission rate of user plane data can be improved.