616 results about "PHY" patented technology

A wireless communication method and system enabling dynamic multi-path data transmission and reception across heterogeneous radio access networks. The method includes selecting between sequential, concurrent, or redundant multipath transmission strategies based on real-time measurements of link quality parameters, including signal-to-interference-plus-noise ratio (SINR), reference signal received power (RSRP), delay, and spectrum availability. The system further enables adaptive transmission power control, modulation scheme selection, and carrier configuration based on physical layer feedback, minimizing interference and optimizing spectral efficiency. Peer-to-peer communication between terminals is supported without base station mediation, reducing RAN load. Multi-base station connectivity is enabled, allowing terminals to simultaneously transmit through multiple nodes and aggregate at the core network. The architecture supports real-time topology control, dynamic link adaptation, and transmission parameter adjustment based on physical-layer constraints.

An embodiment of aspect 1 provides an user device, UE, for a wireless communication system, wherein the UE or a its transceiver is configured toreceive from a network node, e.g., gNB, at leasta channel state information, CSI, report configuration via a higher layer, e.g., radio resource control, RRC, layer,a configuration or indication via a PHY-layer, e.g., physical downlink control channel, PDCCH, signalling, and / or a higher layer signalling,perform measurement(s) on said at least one CSI-RS resource,compute one or more parameters related to a channel state information, CSI, and / or DL transmission rate and / or reliability associated with at least one of the P subsets of a CSI-RS resource, andtransmit a report to the network node via the PHY-layer or a higher layer.

This disclosure provides systems, methods, and apparatuses for wireless communication. An example apparatus selects a resource unit (RU) for a physical (PHY) layer convergence protocol (PLCP) protocol data unit (PPDU). The selected RU includes a set of contiguous tones spanning a bandwidth. The apparatus maps the set of contiguous tones to a set of non-contiguous tones distributed across the frequency spectrum, and transmits the PPDU over the set of non-contiguous tones. Another example apparatus selects an RU of a group of RUs that collectively span a frequency spectrum, and formats a PPDU based on a first frequency bandwidth wider than the selected RU's bandwidth. The apparatus parses the contiguous tones of the selected RU to a set of non-contiguous tones spanning a unique segment of a second frequency bandwidth wider than the first frequency bandwidth, and schedules a transmission of the PPDU over the set of non-contiguous tones.

The invention provides a dynamic high-precision PTP (Precision Time Protocol) time synchronization system realized based on an FPGA (Field Programmable Gate Array), which comprises a master device and a slave device, and the master device and the slave device are connected through a PHY (Physical Layer) to carry out PTP time synchronization; the master device and the slave device have the same structure and comprise an FPGA and a voltage-controlled crystal oscillator; in the master device, the FPGA obtains the frequency difference and the phase difference between the master device and an externally input reference source, further adjusts the frequency of a voltage-controlled crystal oscillator, corrects a local time mark, and sends a PTP message to the slave device; and in the slave equipment, the FPGA obtains the frequency difference and the phase difference between the slave equipment and the master equipment based on the received PTP message, so that the frequency of the voltage-controlled crystal oscillator is adjusted, and the local time scale is corrected. According to the invention, low-cost and high-precision PTP time synchronization is realized.

The invention discloses a financial auditing system based on artificial intelligence, which belongs to the technical field of artificial intelligence and comprises a heterogeneous data dynamic adaptation device, a trusted data pipeline system and a central auditing processing unit. The heterogeneous data dynamic adaptation device comprises a multi-protocol PHY chip set, an FPGA programmable logic array, a protocol sensing antenna array and an AI coprocessor. The protocol sensing antenna array is annularly arranged on the inner wall of the device shell and comprises at least 12 miniature receiving and transmitting modules with adjustable directions; a protocol reverse learning model is arranged in the AI coprocessor, and a protocol analysis scheme is dynamically generated by analyzing electromagnetic radiation characteristics of an interface. According to the financial auditing system based on artificial intelligence, real-time dynamic data adaptation and credible traceability of a cross-heterogeneous financial system can be achieved, the problems of format conflict, semantic ambiguity and transmission delay of multi-source heterogeneous data in the auditing process are solved, and meanwhile verifiability and non-tampering performance of the data extraction process are ensured.

The invention provides a universal serial bus (USB) 2.0 host speed reduction bridge based on bidirectional protocol handshake and a prototype verification or hardware simulation acceleration platform, which are characterized in that a slow-speed side module runs at a slow clock frequency, is responsible for realizing a protocol layer of a USB protocol and a physical link layer function of the USB protocol, and communicates with a USB2.0 host controller in a chip design (DUT) to be tested; the original speed side module works under the original clock frequency, logic of a protocol layer of a USB protocol and a physical link layer of the USB protocol is achieved, communication with an external real USB2.0 slave end device is achieved through a USB2.0 PHY, data caching and synchronization are achieved through a data caching RAM, and the bridge control module overall plans the whole situation and accurately regulates and controls independent handshake of the USB2.0 protocol layers on the two sides under the original clock frequency. Through bidirectional protocol handshake on the two sides of the speed reduction bridge, data communication between a low-speed to-be-tested chip design (DUT) in a chip prototype verification platform and external standard-speed real USB slave equipment is achieved through the speed reduction bridge.

Various aspects of the present disclosure generally relate to wireless communication. Some aspects more specifically relate to configuration of downlink and / or uplink quality of service (QoS) based radio link monitoring and prediction and related signaling and procedures. In some aspects, a network node may configure a user equipment (UE) with set(s) of physical (PHY) and / or medium access control (MAC) parameters for QoS radio link monitoring and reporting. Once configured with the parameter sets, the UE may receive a signal from the network node to use a particular set, or may autonomously select a set using traffic requirements. The network node may schedule the UE to send a QoS report in accordance with one or more downlink or uplink measurement and / or prediction results. For example, when the monitored results exceed one or more configured threshold(s), the UE may transmit a report to the network node.

A method, an apparatus, a terminal, and a medium for processing a sidelink consistent listen before talk failure, are provided. The method for processing a sidelink consistent listen before talk (LBT) failure includes: determining, by a terminal, that the sidelink consistent LBT failure is triggered on a first resource; and performing, by the terminal, a first operation, where the first operation includes at least one of the following: resource selection or resource reselection or resource switching; determining that the first resource is recovered from the sidelink consistent LBT failure, or canceling the sidelink consistent LBT failure triggered on the first resource; and a Media Access Control (MAC) layer of the terminal informs a PHYsical (PHY) layer: the first resource is recovered from the sidelink consistent LBT failure, or canceling the sidelink consistent LBT failure triggered on the first resource.

A communication method includes: sending a first poll frame, where the first poll frame is for triggering ranging measurement in a first range-measurement cycle, the first poll frame further indicates a first parameter set that takes effect in the first range-measurement cycle, and the first parameter set includes one or more of the following parameters: a first narrowband physical layer (PHY) parameter, a first narrowband channel allow list, a first ranging block structure parameter, or a first ultra-wideband (UWB) multi-millisecond (MMS) ranging configuration parameter; and receiving a response frame of the first poll frame. According to the present disclosure, an initiator uses a poll frame to indicate a parameter set that takes effect in a current range-measurement cycle.

This disclosure provides methods, components, devices and systems for indications for non-primary channel access. Various aspects relate generally to communicating an indication relating to a wireless device or signaling (such as a physical layer (PHY) protocol data unit (PPDU)) from an OBSS. Sharing the indication between wireless devices may facilitate non-primary channel access (NPCA). Some aspects more specifically relate to a first wireless device that may receive a portion of a PPDU communicated by a third wireless device in an OBSS. The portion of the PPDU may indicate that the third wireless device is included in the OBSS. The first wireless device may transmit a frame including an indication to a second wireless device. The first wireless device and the second wireless device may be included in a BSS and may utilize the indication to perform NPCA on an opportunistic primary channel.

This disclosure provides methods, components, devices, and systems for signaling designs for enhanced long range (ELR) transmissions. Some aspects more specifically relate to preamble field designs of ELR physical layer (PHY) protocol data unit (PPDU) formats. In some implementations, a wireless communication device may transmit, via a universal signal (U-SIG) field, a first indication that a PPDU is associated with an ELR format and a second indication of a station (STA) identifier. Additionally, or alternatively, a wireless communication device may transmit, via a set of ELR symbols within a PPDU, an ELR sequence in accordance with a mapping between basic service sets (BSSs) and ELR sequences. Additionally, or alternatively, a wireless communication device may include one or more subfields within an ELR-signal (ELR-SIG) field in accordance with a location of the ELR-SIG field and employ one or more transmission schemes associated with the ELR-SIG field and an ELR-data field.

Methods, apparatus and systems for wireless sensing are described. In one example, a described system in a wireless data communication network comprises: a transmitter configured to transmit a time series of at least one wireless sounding signal (WSS) based on a standard wireless network protocol associated with the wireless data communication network, and a receiver. The wireless data communication network comprises a physical (PHY) layer, a medium access control (MAC) layer, and at least one higher layer. The receiver is configured to: receive the time series of at least one WSS (TSWSS) based on the standard wireless network protocol through a wireless channel of a venue, and perform a plurality of wireless sensing measurements based on the received TSWSS to obtain sensing measurement results based on the standard wireless network protocol. The PHY layer or the MAC layer of the receiver provides the sensing measurement results locally to the at least one higher layer of the receiver based on the standard wireless network protocol. The sensing measurement results are available to the at least one higher layer of the receiver for performing a sensing-based task based on the sensing measurement results.

In an embodiment, a method includes receiving a data packet and generating an optimized security tag based on a standard security tag by replacing an 8-byte optional secure channel identifier (SCI) of the standard security tag with 32 most significant bits of a 4 packet number, a 2-byte MAC Security Entities (SecY) engine identifier, and a 2-byte short SCI. The method further includes encrypting the data packet and transmitting the encrypted data packet comprising the optimized security tag to an electronic device.

Procedures, methods, architectures, apparatuses, systems, devices, and computer program products directed physical layer signaling in a wireless local area network system are provided. Among the methods is a method that may include any of generating an extremely high throughput (EHT) physical (PHY) layer protocol data unit (PDU) (PPDU) based on a PPDU format defining a preamble comprising (i) a fixed duration universal signaling (U-SIG) field, (ii) an EHT signaling (EHT-SIG) field, and (iii) an EHT short training field (EHT-STF), wherein the U-SIG and EHT-SIG fields respectively comprise an extra signaling indicator and extra signaling to support a third feature; and transmitting the U-SIG and EHT-SIG fields on a first bandwidth segment, followed by the EHT-STF on any of the first bandwidth segment and a second bandwidth segment, followed by (iii) an EHT data field on any of the first and second bandwidth segments.

The present disclosure provides techniques for physical layer (PHY) parameter recommendation for improved link quality. An access point (AP) receives a recommendation request frame from a station (STA), the recommendation request frame comprising at least one of: one or more physical layer (PHY) parameters of the STA, a link margin of the STA, or one or more acceptable link degradation limits of the STA. The AP determines, based on the recommendation request frame, a recommended range for at least one of the PHY parameters, the recommended range being determined to maintain link performance within the acceptable link degradation limits. The AP transmits a recommendation response frame to the STA, the recommendation response frame comprising the recommended range, where the STA adjusts at least one PHY parameter based on the recommended range.

Disclosed are techniques for wireless communication. In an aspect, a method performed by a receiving entity includes: receiving, from a transmitting entity, a first physical layer identity matrix (PHY ID) for the transmitting entity; receiving, from the transmitting entity, an encrypted ranging message; calculating a second PHY ID for the transmitting entity based on the encrypted ranging message; and authenticating the encrypted ranging message based on a comparison of the first PHY ID and the second PHY ID. Upon determining that the encrypted ranging message is authentic, the encrypted ranging message is decrypted to produce a decrypted ranging message and processing the decrypted ranging message. In some aspects, upon determining that the encrypted ranging message is not authentic, the encrypted ranging message is not processed (e.g., ignored or discarded). In some aspects, the receiving entity rejects further signal transmission and ranging procedures with the device thereby preventing successful attack.

Disclosed are an automotive Ethernet circuit board and communications system, and a vehicle. The automotive Ethernet circuit board includes: a component placement layer, configured to carry a PHY chip and a control chip of the PHY chip; a plurality of signal wiring layers, configured to carry signal wiring between components in the component placement layer; and a signal shielding layer, located between the plurality of signal wiring layers and configured to prevent interference of a clock signal in the signal wiring. In the embodiments of the present application, a plurality of signal wiring layers are used for signal wiring between components, and a plurality of complete signal shielding layers are used to prevent interference of a clock signal in the wiring. The embodiments help reduce signal crosstalk between PCBs, prevent interference of a clock signal in signal wiring, and improve stability and consistency of a data communications system.

The invention discloses a drainage pipe network overflow prediction method based on a Pry-STNN model, and the method comprises the steps: carrying out the calibration of a checked SWMM model, and generating multiple rainfall data based on a Chicago rain pattern; modeling the drainage pipe network into an undirected graph with node features and edge features, and constructing a data set in a PyG format; a GNN and LSTM series space-time neural network architecture is adopted, space features are extracted, and time correlation is captured; a differentiable physical layer is embedded into the output end of the neural network, and the physical consistency of prediction results is ensured through physical constraints such as a continuity equation and a mixed loss function; finally, the model is optimized through staged training and a dynamic regularization strategy, evaluation is carried out according to indexes such as R, MAPE and RMSE, high-precision and robust drainage pipe network overflow early warning can be achieved under the scenes such as conventional rainfall, extreme rainstorm and pipe network faults, and powerful technical support can be provided for intelligent drainage and waterlogging prevention scheduling.

The invention relates to a clock management structure, a system on chip and electronic equipment, and the clock management structure comprises a phase-locked loop and an arbitration frequency division module connected with the phase-locked loop. The phase-locked loop is deployed in the PHY; the phase-locked loop is used for generating a phase-locked loop clock of X channels according to an externally input clock signal; the arbitration frequency division module is used for processing the phase-locked loop clocks of the X channels to generate an MAC interface clock, and synchronizing the MAC interface clock to an MAC interface and a port corresponding to each channel; wherein X represents the total number of channels corresponding to a plurality of ports between the PHY and the MAC. According to the clock management structure, the cross-clock domain design in the SoC design is greatly reduced, and the clock structure in the SoC is simplified, so that the area of the SoC chip is reduced.

A vehicle-mounted relay device for relaying Ethernet frames includes a plurality of PHY units corresponding to a plurality of vehicle-mounted devices, a switch unit to which the plurality of PHY units are connected, and a control unit configured to monitor operating states of the plurality of PHY units. The plurality of PHY units include a predetermined PHY unit whose operating state switches between a sleep state and an active state in response to reception of a predetermined control signal that differs from the Ethernet frames. When an Ethernet frame to be transmitted from the predetermined PHY unit has been detected during a period where the predetermined PHY unit is in the sleep state, the control unit executes switching control to switch the predetermined PHY unit to the active state.

The embodiment of the invention provides a link training method, chip, device and system, in the method, a sending end device generates and sends a first link training request to a receiving end PHY chip, the first link training request is used for instructing the receiving end PHY chip to perform link training on a first parameter, the first parameter at least comprises a parameter of a receiving end module, and the first parameter is used for instructing the receiving end PHY chip to perform link training on the first parameter. The parameters of the receiving end module are optical module parameters; and the transmitting end device receives first state information, wherein the first state information indicates a state after link training is performed on the first parameter based on the first link training request. Thus, even if the receiving end module in the communication system does not comprise an oDSP chip, link training of parameters in the receiving end module connected with the receiving end PHY chip by the receiving end PHY chip can be realized through interaction of an end-to-end link training request and state information between the sending end equipment and the receiving end PHY chip, so that the working performance of the communication system is guaranteed.

Datacenter workloads demand flexible memory architectures spanning from rack-level to pod-scale deployments. Embodiments herein disclose systems enabling CXL memory semantics over physical layers based on IEEE 802.3 PMA, facilitating memory disaggregation across datacenter fabric infrastructures. The embodiments comprise processing cores with coherent interconnects, MMUs for address translation, and memory channels supporting substantial memory capacities. Resource Provisioning Units (RPUs) translate between CXL data, optionally encapsulated, transmitted via physical layers based on IEEE 802.3 PMA, and CXL requests, enabling external entities to access memory across different physical address spaces. This architecture provides memory pooling using datacenter network infrastructure, supporting intra-rack memory sharing, inter-pod memory access, distributed AI training across datacenter resources, and elastic memory provisioning for cloud-native applications, overcoming physical layer limitations of traditional CXL implementations while maintaining protocol coherency suitable for GenAL, LLM inference, and HPC workloads.

Embodiments herein relate to testing chiplets during the manufacturing process. In one aspect, an on-chiplet interface is provided which allows testing of inter-chiplet communications of a chiplet on a package substrate without requiring the use of another chiplet. The interface communicates with an external Field-Programmable Gate Array (FPGA) on the package substrate at a reduced frequency compared to a frequency of the inter-chiplet communications. The FPGA can in turn communicate with a workstation to receive instructions and provide test results. The FPGA sends test pattern signals to, and evaluates corresponding responses from, circuitry of the chiplet which implements an inter-chiplet communication standard such as the Universal Chiplet Interconnect Express (UCIe) standard. In another aspect, the physical layer (PHY) circuits of two chiplet are tested with respective FPGAs.

A three-dimensional (3D) stacked memory package is described. The 3D stacked memory package includes a first plurality of stacked memory dies. The 3D stacked memory package also includes a first base die stacked on the first plurality of stacked memory dies. The 3D stacked memory package further includes a package substrate supporting the first plurality of stacked memory dies. The 3D stacked memory package also includes a first plurality of through silicon vias (TSVs) extending between the first plurality of stacked memory dies and a first compute block on the first base die. The 3D stacked memory package further includes a first set of wire-bonds coupled between the package substrate and a first physical IO interface (PHY) on the first base die.

A pulse amplitude modulation 4-level (PAM-4) physical layer (PHY) serializer / deserializer (SerDes) receiver is provided. The receiver may include an analog-front-end (AFE) block to receive a transmit signal, an analog-to-digital converter (ADC) block to convert the transmit signal into a digital signal at sampling intervals defined by a sampling clock signal, a clock and data recovery (CDR) circuit to receive the digital signal from the ADC block and extract a recovered clock signal and a recovered data stream, the recovered data stream containing a sequence of symbols with amplitude values corresponding to four levels of PAM-4, a phase integrator (PI) to generate the sampling clock signal for the ADC block based on the recovered clock signal, and a feedforward phase correction (FFPC) block to receive the recovered data stream and generate a receive signal.

The invention discloses a printed circuit board, a layout method thereof and a vehicle, and relates to the technical field of printed circuit board layout. The method comprises the following steps: connecting a capacitor in series on a differential signal line of a physical layer chip; carrying out hollowing processing on the adjacent layer corresponding to the pin bonding pad based on a preset hollowing strategy; carrying out region division on the inner layer of the printed circuit board so as to divide the inner layer into a plurality of different regions; a plurality of backflow via holes are formed beside layer changing via holes of a circuit of the printed circuit board based on a preset setting strategy, and the backflow via holes are used for providing layer changing channels for backflow currents of the circuit on a reference plane when layers of the circuit are changed. By implementing the PCB design measures of capacitor series filtering, pad adjacent layer hollowing, inner layer segmentation and isolation and backflow via hole optimization, the problem that electromagnetic compatibility radiation and conducted emission exceed the standard due to PHY circuit filtering loss, impedance mismatch, power ground noise coupling and unreasonable high-speed signal backflow path in the traditional TBOX design is effectively solved.

The application provides a multi-bin temperature monitoring system and method in the technical field of chemical component storage, which comprises a communication acquisition board and a plurality of temperature acquisition boards; the communication acquisition board comprises a first MCU, an Ethernet interface, a PHY chip, a memory, a plurality of fire-fighting IO ports and a plurality of first communication interfaces; the temperature acquisition board comprises a second MCU, a second communication interface, a plurality of ADC chips and a plurality of temperature sensors; the first MCU is connected with the PHY chip, the memory, the fire-fighting IO ports and the first communication interfaces respectively; the Ethernet interface is connected with the PHY chip; each first communication interface is connected with a plurality of second communication interfaces respectively; one end of each ADC chip is connected with the second MCU, and the other end is connected with a plurality of temperature sensors. The application has the advantages of greatly reducing the temperature monitoring cost and greatly improving the production line expandability.

The utility model discloses a network encryption control module with a protection structure, comprising an encryption control module which is internally provided with a hardware sub-module and a software sub-module. The hardware sub-module is internally provided with a ZYNQ7020 processor, an external interface, a debugging interface, a socket XS1, a socket XS2, a socket XS3, a reset key, a power supply, a power supply state indicating lamp, a conversion chip, a gigabit PHY and a gigabit transformer. According to the network encryption control module with the protection structure, the XC7Z020-3CLG484I processor realizes the functions of four paths of Ethernet and the like; by arranging the main control IP address module, the audio and video IP address module, the telephone IP address module, the unvarnished transmission mode module, the ad hoc network encryption mode and the access network encryption mode, the problem that in a specific environment, the network is encrypted by a large-capacity memory and abundant external interfaces and convenient debugging interfaces is solved. The network encryption control module selectively carries out encryption or unvarnished transmission on voice, data and other information transmitted by the wireless ad hoc network.

A communication device communicates a physical (PHY) frame including a preamble and a data field. The preamble includes a Legacy Short Training Field (L-STF), a Legacy Long Training Field (L-LTF), a Legacy Signal Field (L-SIG), an EHT (Extremely High Throughput) Signal Field (EHT-SIG-A), an EHT Short Training Field (EHT-STF), and an EHT Long Training Field (EHT-LTF), and the EHT-SIG-A includes at least one subfield indicating that the communication device performs communication in a frequency band more than 160 MHz.

The application discloses a reset circuit and a vehicle-mounted Ethernet PHY chip reset system. The reset circuit comprises an Ethernet SWITCH unit, an MCU unit, a PHY chip unit and a reset chip unit. The Ethernet SWITCH unit is connected with a plurality of the PHY chip units. The plurality of the PHY chip units are connected with the reset chip unit. The Ethernet SWITCH unit is connected with the MCU unit. The MCU unit is connected with the reset chip unit. The reset circuit provided by the application can be reset in multiple ways. The reset circuit provided by the application has improved reliability, functionality and flexibility in a vehicle-mounted environment.