985 results about "PHY" patented technology

A system and method for auto-polling a status register within a physical layer (PHY) interface to a local area network (LAN). The system includes a host CPU which needs to detect and service interrupts generated by a PHY device on the LAN which is coupled between a first transmission medium (such as copper or fiber cable) and a management interface to the system. The system further includes an auto-polling unit which monitors activity on the management interface of the PHY device. When the auto-polling unit detects a lack of activity on the management interface of the PHY for a predetermined interval, the auto-polling unit reads a first value from the PHY status register. This first status value is then compared to a previously stored value which corresponds to the last PHY status value read by the host CPU. If a mismatch is detected between these two values, an interrupt is generated to the CPU. In response to receiving the interrupt, auto-polling is suspended (to avoid changing the status data that caused the interrupt) and the CPU requests a read of the status value in the first register. In this manner, the CPU is able to access the status value which caused the interrupt and determine the appropriate course of action. This status read by the CPU also has the effect of clearing the interrupt. This system frees the CPU from having to continually poll the PHY status register to determine if a change in status has occurred.

In view of the foregoing, the present invention provides a unified software framework or architecture for distributed coordination of wireless devices and radios, referred to as Layer 2.5 Software MAC (or ‘SoftMAC’), which resides between the standard 802.11 MAC layer (Layer 2) and IP layer (Layer 3) to regulate and control the amount of traffic (both real-time and “best effort”) delivered to 802.11 MAC DCF interfaces. The software based design can be ported to different OS platforms and systems and is capable of handling new hardware interfaces and MAC mechanisms (e.g., 802.11e) with only a software upgrade. The invention thus provides a natural way to make end systems support coordination of different radios of device(s), achieving better performance. Advantages of the 2.5 layer software MAC in accordance with the invention include: (a) there are no hardware constraints; (b) heterogeneous wireless/radio support is provided at the 2.5 layer; and (c) an evolutionary and extensible solution with the ability to support future wireless MAC/PHY chip combinations.

Methods and systems for communicating in a wireless network negotiate a level of service for a data stream between peers of the wireless network. The level of service may be modified based on one or more characteristics of a communication link or the wireless network such as channel load, channel free time, physical (PHY) link rate, data rate and/or overall channel capacity. Various specific embodiments and variations are also disclosed.

The invention discloses a method for realizing a precision time protocol (PTP) with nanosecond-level precision. The method comprises the following steps of: identifying a PTP message and recording a leaving or arrival timestamp of the PTP message in a physical layer (PHY) chip; realizing frequency synchronization by using a synchronization Ethernet (SyncE) technology in a physical layer; and managing the timestamp in a way of combining the PHY chip and a field programmable gate array (FPGA), and ensuring the consistency of time in the PHY chip and FPGA maintenance time at the arrival of the PTP message by adopting a software processing method. By the technical scheme provided by the invention, the requirements of a communication system on time synchronization precision can be met, and the synchronization precision of the PTP reaches a nanosecond level.

An arrangement in a network device for facilitating at least one of multiple connection speeds with a network, active response between a monitoring device and an end-device, and power over Ethernet (POE) over a network is provided. As a facilitator of multiple connection speeds, the arrangement includes a plurality of physical layer interface (PHY) and media access controller (MAC) that are configured to support multiple speeds. As a facilitator of active response, the arrangement includes a logic arrangement for multicasting a set of instructions that is sent from a monitoring port. As a facilitator of POE, the arrangement is configured to receive data traffic (e.g., data packets and/or power packets) through a first network port and to send the data traffic out a second network port.

The invention discloses a gigabit Ethernet field bus communication device based on an FPGA (Field Programmable Gate Array). The device comprises an ARM (Asynchronous Response Mode)/DSP (Digital Signal Processor) expansion interface, an FPGA module, a PHY (Physical Layer) chip and a field bus communication interface and is characterized in that an electrical signal or an optical signal on a field bus is converted into a differential signal through a field bus interface; data is downloaded into the FPGA module through the gigabit PHY chip; and the FPGA module is used for receiving and analyzing the downloaded data and then transmitting the analyzed data to an ARM or a DSP connected with the ARM/DSP expansion interface through the ARM/DSP expansion interface for processing; the data processed by the ARM/DSP is packaged into a data frame by the FPGA module and is then converted into the differential signal through the gigabit PHY chip; and the differential signal is converted into the electrical signal or the optical signal through the field bus communication interface to be transmitted onto a the field bus. The gigabit Ethernet field bus communication device has the beneficial effects that the data transmission rate of 1000 Mbps can be realized, the communication with external equipment with the PCI (Peripheral Component Interconnect) interface can be realized, and different controllers can be externally connected according to the actual needs, the flexibility is high, and the gigabit Ethernet field bus communication device can be flexibly applied to real-time monitoring and communication of an industrial control field.

Systems and methods are provided for providing communication between an ATM layer device and multiple multi-channel PHY layer devices, which increase the number of multi-channel PHY layer ports supported by the ATM layer device. In general, one such system comprises an ATM layer device that supports a plurality of ATM communication channels in which each of the plurality of ATM communications channels correspond to a first class of service or a second class of service, a plurality of physical layer devices each having a first channel port associated with the first class of service and a second channel port associated with the second class of service, and a local interface in communication with the ATM layer device and the plurality of physical layer devices for establishing a plurality of channel connections between each of the plurality of ATM communication channels and the first channel port and the second channel port in each of the plurality of physical layer devices, the local interface having a plurality of addresses. In the system, each of the plurality of channel connections associated with the plurality of second channel ports is via one of the plurality of addresses and at least two of the plurality of channel connections associated with the plurality of first channel ports is via no more than one of the plurality of addresses. In this manner, the system increases the number of physical layer devices communicating with the ATM layer.

A system and method of analyzing a powered device (PD) in a Power-over-Ethernet (PoE) system are presented. The system includes an Ethernet interface having a physical layer (PHY) chip capable of providing a signal pulse in addition to physical layer 1 functions. The system further includes a pulse transformer, coupled to the PHY chip, capable of relaying the signal pulse provided by the PHY chip to the PD via the transmit line and a second PHY chip. The first PHY chip receives one or more return pulse signals from the PD, analyzes characteristics such as voltage and/or frequency of the return pulse signal(s), and determines attributes of the PD based on those characteristics. The attributes can include powered device validity and power classification. A method of supplying power to a PD is also presented.

The invention provides a method for controlling a physical layer (PHY) chip and a control circuit. The control circuit comprises a timing clock module, a first register module, a first state locking and storing module, a state rotation module and a management data input/output (MDIO) controller, wherein the state rotation module is used for reading the first register module according to a clock signal provided by the timing clock module and change information provided by the first state locking and storing module and providing first address information and control data information for the MDIO controller according to a reading result; and the MDIO controller is used for writing the control data information into a register of a pin of the PHY chip corresponding to the first address information so that the pin state of the PHY chip can be controlled automatically. After the technical scheme disclosed by the invention is adopted, the same MDIO controller can be used for managing multiplePHY chips so that the load of a central processing unit (CPU) is reduced.

A device that recognizes the time synchronization packet and substitutes a real-time value from the master internal counter into the proper place in a data packet is placed between an Ethernet Media Access Controller (MAC) and a Physical Interface Transceiver (PHY). A second device monitors the packet passing from the MAC to the PHY and determines when it is a time synchronization packet from the time master. Upon recognition of the proper packet, the second device simultaneously captures the master's time value and captures the value of a local real-time clock. The result of these captures are presented to the local host computer which controls the time base clock that increments the local real-time clock to either speed up or slow down this local clock, thereby synchronizing the local clock to the time master clock. The offset and skew of the local clock to the master clock is reduced to only the network latency plus variability due to network congestion.

The invention relates to a gigabit Ethernet redundant network card and a link switching condition determination result control method thereof and belongs to the technical field of networks. The network card consists of a gigabit Ethernet controller, a working link Physical Layer (PHY) chip, and a backup link PHY chip, wherein the gigabit Ethernet controller comprises a working link control module and a backup link control module. The working link control module and the backup link control module are connected to a PHY chip of a corresponding link through a corresponding link MII bus and a link Management Data Input Output (MDIO) bus, corresponding working heartbeat frames and backup heartbeat frames are transmitted, the state of the working link and the backup link can be determined through receiving of corresponding working heartbeat frames and backup heartbeat frames, the Ethernet link is determined to be disconnected under the condition that the gigabit Ethernet PHY chip is not modified, the switch of the working link and the backup link is controlled, the response speed of the redundant switching of the card is improved and the use experiment of users is optimized.

Switching between Orthogonal Multiple Access (OMA) and Non-Orthogonal Multiple Access (NOMA) modes of a user equipment (UE) can be determined and indicated by a gNB to a UE at an RRC connected state using one or more of the following schemes: at an RRC (Radio Resource Control) layer with an RRC configuration message, at a MAC (Medium Access Control) layer with MAC CE (MAC control element) signaling, at a PHY (Physical) layer with DCI (Downlink Control Information) signaling, jointly with RRC configuration and DCI signaling, and/or jointly with RRC configuration and MAC CE signaling. The OMA or NOMA mode that the UE operates after the transition may be requested by the UE, indicated by the gNB, and/or may be based on one or more rules for OMA-NOMA switching.

The present invention relates to the field of Ethernet exchange equipment and router equipment, mainly, it is an optical/electric interface module space multiplexing method for Ethernet SFP interface and its device. Said method includes: 1). adopting PHY chip for supporting 10/100/1000 BASE-T and 1000 BASE-X function; 2). interface of 10/100/1000 BASE-T adopts special SFP electric interface module; 3). 1000 BASE-X adopts general SFP kilomega optical interface module; 4). at SFP interface side of PHY chip using multiplexer equipment provided by said invention for supporting SFP electric module and SFP optical module and making space multiplex in same SFP CAGE space; 5). according to the detected result large system can make correspondent configuration for said port so as to make said port be worked in electric interface or optical interface module.

An example method comprises receiving, by a first PHY of a first transceiver, a timing packet, timestamping, by the first transceiver, the timing packet and providing the timing packet to a first intermediate node, determining a first offset between the first intermediate node and the first transceiver, updating a first field within the timing packet with the first offset between the first intermediate node and the first transceiver, the offset being in the direction of the second transceiver, receiving the timing packet by a second transceiver, the timing packet including the first field, information within the first field being at least based on the first offset, determining a second offset between the second transceiver and an intermediate node that provided the timing packet to the second transceiver and correcting a time of the second transceiver based on the information within the first field and the second offset.

The invention discloses a method and a device for realizing time synchronization on an Ethernet switch. The device comprises a Switch module, a plurality of PHY (Physical layer) modules, a CPU module and a clock processing module, wherein the clock processing module comprises a clock synchronization sub-module and a clock production sub-module. The clock can be synchronized according to the clock provided by the PHY module through adopting the time delay measuring technology provided by the synchronic Ethernet (SyncE, SynchronousEthernet) protocol and the IEEE1588 protocol, then the reference input clock needed by the relative modules in the system can be produced, and the frequencies of the main device and the auxiliary device are synchronized. Because of adopting the PHY chip with SyncE function, the frequency synchronization precision is very high, which can reach nanosecond level.

The invention provides a router equipment, a main card thereof and a method for adapting the main card to an interface card. A data bus for the interactive data of the main card and the interface card is set into a serial differential data bus, and a processor can support any serial interface protocol of the interface card and transmit data on the serial differential data bus in a bandwidth meeting the requirement of the interface card, so that the bandwidth requirement of various interface cards can be met through the flexible configuration of the processor. Furthermore, for the Ethernet interface card, the function of an Ethernet MAC (Media Access Control) controller and the function of a physical layer can be integrated in the processor, so that the Ethernet interface card does not need to be provided with the Ethernet MAC controller, even an Ethernet PHY (Physical Layer) chip, and the cost of the Ethernet interface card can be accordingly reduced.

A cloud radio access network (CRAN) system includes a baseband unit (BBU) and a radio unit (RU) remote from the BBU. The fronthaul interface between the RU and the BBU includes a radio frequency interface (RF) functionality implemented in the RU, and implementation of asymmetrical physical layer (PHY) functionality split between the BBU and RU. The asymmetrical physical layer (PHY) functionality split includes: downlink (DL) antenna port mapping and DL precoding implemented in the RU; and the split of the PHY functionality for uplink (UL) at the antenna port mapping in the BBU. For the DL, precoding and resource element (RE) mapping to frequency resources is implemented in BBU, and RE mapping for antenna ports is implemented in the RU|[WA1]. The split also provides support for license-assisted access (LAA) in the CRAN system.

A signal transmitted to an STA 200a from a communication device AP is also received by an STA 200b. Upon reception, the STA 200b measures an RSSI. The STA 200b then creates a state notice frame which includes the measured RSSI, and transmits it to the AP 100. In accordance with the received state notice frame, the AP 100 determines and updates a PHY rate for transmission to the STA 200b. This allows to increase the determination and update frequency of PHY rates than before, resulting in an improved possibility of coping with rapid changes in channel environments.

The present invention relates to a method for implementing fast optical fibre protection replacement in the ring network and its equipment. The method mainly includes the folling steps: firstly, notifying the fibre-breaking warning message produced by standby equipment to main equipment by means of bottom layer hardware, then according to the received fibre-breaking warning message making opticalfibre protection replacement by main equipment. In the complex programmable logic device of main equipment and standby equipment the warning detection module, standby equipment serial-parallel conversion module and main equipment serial-parallel conversion module are set respectively.