Method for realizing precision time protocol (PTP) with nanosecond-level precision
An implementation method and nanosecond-level technology, applied in digital transmission systems, electrical components, transmission systems, etc., to achieve the effects of reducing fluctuations, improving precision and accuracy, and ensuring consistency
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[0031] figure 1 It is a system block diagram of this embodiment, which includes a CPU module 10 , a Switch module 12 , a PHY chip module 14 , an FPGA module 11 and a DPLL module 13 .
[0032] CPU module 10, running system software, manages the whole system;
[0033] Switch module 12 is the core switching module of the system, except that completing the forwarding function, it is also responsible for sending the PTP message to the CPU module for processing;
[0034] The PHY chip module 14, in addition to completing the data packet encoding and decoding and sending and receiving functions, is also responsible for: identifying the PTP event message, and latching its time stamp into a specific register, and generating an interrupt signal 4 to notify the CPU module to read; The clock is extracted from the Ethernet link, and the recovered clock 1 is output to the DPLL module for processing; the internal counter overflows to generate a pulse signal 2 to the FPGA;
[0035] FPGA modu...
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