252 results about "Precision Time Protocol" patented technology

The present disclosure relates to Ethernet synchronization systems and methods that combines Synchronous Ethernet (Sync-E) and Precision Time Protocol (PTP) IEEE 1588 algorithms. The present invention includes systems and methods for Ethernet networks and node configurations that include a set of rules on node placement, such as Boundary Clock (BC) nodes and Sync-E nodes, a clock selection algorithm, a holdover algorithm, and the like. Advantageously, the present invention provides an architecture that allows practical and real-world useful clock propagation through placement of BCs and Sync-E nodes for best performance. Practical experience and theoretical design are embodied in the present invention to define a very specific set of rules on how to build a network capable of providing accurate and reliable synchronization. The present invention includes clock selection that unifies Sync-E and 1588 algorithms.

Provided are a network slave node and a time synchronization method using precision time protocol-like (PTP-like) in a network. The network slave node includes a packet detection unit for detecting whether the slave node receives or sends a synchronization protocol packet and recording a synchronization protocol packet receiving time and a synchronization protocol packet sending time; a hardware clock; and a control unit controlling the packet detection unit and the hardware clock. The control unit reads out the packet receiving time and the packet sending time from the packet detection unit and informs a local master node. The local master node calculates a time offset between the local master node and the slave node, and informs the control unit. The control unit adjusts the hardware clock based on the time offset so that the local master node and the slave node are time synchronized.

Precision Time Protocol (PTP) emulation service for a data communication network of a type that is adapted to support circuit emulation services (CES). The PTP emulation service enables seamless PTP-style clock synchronization over such a network using any combination of legacy switches, PTP boundary switches and PTP switches. The PTP emulation service is delivered through the expedient of external PTP emulation devices that are associated with legacy switches and PTP boundary switches.

This invention relates to methods and devices for clock synchronization. The invention makes particular use of IEEE 1588 with offset and skew correction. In embodiments of the invention, the IEEE 1588 Precision Time Protocol is used to exchange time stamps between a time server and a client from which the client can estimate the clock offset and skew. In embodiments of the invention a free running clock at the client is provided with an estimation technique based on the time stamps from the IEEE 1588 PTP message exchange between the server and client clocks. The offset and skew from the estimation process can be combined with the local free running clock to give a synchronized local clock which is an accurate image of the master clock.

Apparatus for making legacy network elements transparent to IEEE 1588 Precision Time Protocol operation. Network elements are wrapped by device(s) capable of providing either transparent clock or boundary clock operation. In one embodiment, smart interface converters are used to provide transparent clock or boundary clock operation. The smart interface converters work cooperatively.

The invention relates to a method for realizing sub-microsecond synchronization accuracy based on a PTP (Precision Time Protocol), belonging to the technical field of communication; in order to obtain high-accuracy synchronization efficiency and save hardware investment cost, the method comprises the following steps: before a master time sends synchronization messages, synchronizing a clock and a clock source of an Ethernet transceiver; obtaining average path delay of links by a delay request information packet delay measuring mechanism or measuring a waiting delay information packet delay measuring mechanism; and performing asynchronous correction on the links so as to realize sub-microsecond synchronization accuracy. In the method, the DP83640 Ethernet transceiver is adopted, network message time stamp can be exactly obtained, the PTP protocol on an AT91RM9200 platform is realized, and sub-microsecond synchronization accuracy can be realized. Via test, the synchronization accuracy can be up to 100ns; and the whole system is low in cost, excellent in openness and expandability, and easy to implement.

The invention discloses a time synchronization method and a time synchronization system for synchronous messages of IEEE1588 master-slave clocks of an intelligent transformer substation. The method comprises the following steps of: establishing a master clock synchronous message, and sending the timestamp t1 of the sending moment of the message to the clock in a broadcasting manner; recording a receiving moment t2 of the master clock synchronous message; recording an absolute receiving moment TT2 when the master clock synchronous message is received by a slave clock; establishing a slave clock responding message, sending the slave clock responding message to the master clock in a peer-to-peer manner, and recording the timestamp t3 of the sending moment of the message; recording an absolute sending moment TT3 when the slave clock sends the clock responding message; recording an acquiring moment t4 when the master clock acquires the message; calculating a time deviation, and calculating asymmetry errors according to the timestamp t1, the absolute receiving moment TT2, the absolute sending moment TT3 and the acquiring moment t4; and carrying out time correction on the slave clock by the time deviation and the asymmetry errors. According to the time synchronization method and the time synchronization system for synchronous messages of IEEE1588 master-slave clocks of the intelligent transformer substation, the influences of the asymmetry errors can be eliminated, and the time synchronization precision of the master-slave clocks is improved.

This invention relates to methods and devices for time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. The primary challenge in clock distribution over packet networks is the variable transit delays experienced by timing packets, packet delay variations (PDVs). Embodiments of the invention provide a method for time offset alignment with PDV compensation where a synchronized frequency signal is available at a slave device via Synchronous Ethernet and is used to determine the compensation parameters for the PDV.

Network timing synchronization for virtual machine (VM) host systems and related methods are disclosed that provide synchronization of master/slave clocks within VM host hardware systems. Master timing messages are sent from the master clocks to slave clocks within VM guest platforms hosted by the VM host hardware system within a virtualization layer, and return slave timing messages are communicated from the VM guest platforms to the master clock. Virtual switches within the virtualization layer use virtual transparent clocks to determine intra-switch delay times for the timing packets traversing the virtual switch. These intra-switch delay times are then communicated to target destinations and used to account for variations in packet transit times through the virtual switch. The VM guest platforms synchronize their timing using the timing messages. The master/slave timing messages can be PTP (Precision Time Protocol) timing messages and/or timing messages based upon some other timing protocol.

A method is provided in one example embodiment and includes providing a time protocol assistant associated with a time-synchronized domain (TSD). The TSD includes a set of nodes that are synchronized to a same time source. The TSD has defined egress and ingress edge points where bidirectional measurements can be made and the egress and ingress edge points are coupled to the time protocol assistant. The method also includes synchronizing one or more packets flowing through a network that includes the TSD through the same time source. In more specific embodiments, the nodes are synchronized to the same time source via the network and the same time source is a grandmaster clock that synchronizes one or more transparent clocks. In yet other embodiments, the transparent clocks manipulate precision time protocol (PTP) packets sent by the grandmaster clock.

The invention discloses a clock synchronization device and a clock synchronization method. The device comprises a delay measurement module, a clock extraction module and a delay compensation module, wherein the delay measurement module is used for measuring a delay value of a message passing through a hardware delay node in real time, and transmitting the delay value to the delay compensation module; the clock extraction module is used for extracting a timestamp stamped before a precision time protocol message enters the hardware delay node when the message is determined to be the precision time protocol message, and transmitting the timestamp to the delay compensation module; and the delay compensation module is used for correspondingly performing delay compensation according to the received delay value and the received timestamp. Compared with the delay value, computed as a fixed value, of the precision time protocol (PTP) message passing through a certain hardware delay node, the delay value, measured in real time, of the PTP message passing through the certain hardware delay node is more precise. Therefore, corresponding timestamp regulation can be performed according to the precise delay value and the extracted timestamp, and the synchronization accuracy of the precision time protocol message is further improved.

The invention discloses a method for realizing a precision time protocol (PTP) with nanosecond-level precision. The method comprises the following steps of: identifying a PTP message and recording a leaving or arrival timestamp of the PTP message in a physical layer (PHY) chip; realizing frequency synchronization by using a synchronization Ethernet (SyncE) technology in a physical layer; and managing the timestamp in a way of combining the PHY chip and a field programmable gate array (FPGA), and ensuring the consistency of time in the PHY chip and FPGA maintenance time at the arrival of the PTP message by adopting a software processing method. By the technical scheme provided by the invention, the requirements of a communication system on time synchronization precision can be met, and the synchronization precision of the PTP reaches a nanosecond level.

A method and an apparatus for encrypting/decrypting packet data of a precise time synchronization protocol and a time synchronization system are illustrated. The method is suitable for the time synchronization system using a precise time protocol. The time synchronization system includes a master node and a slave node, wherein the slave node synchronizes its time with the master node. In the method for encrypting/decrypting packet data of the precise time synchronization protocol, an encryption/decryption hardware device is disposed on the hardware protocol layer of each of the master node and the slave node. The hardware protocol layer is under the data link layer, and includes the data link layer. A synchronization message is encrypted by using the encryption/decryption hardware devices of the master node to generate a frame data, and the frame data is decrypted by using the encryption/decryption hardware devices of the slave node to obtain the synchronization message.

The invention discloses a system time synchronization device and method in a packet transport network, relating to packet transport networks in optical communication. The device comprises a CPU (central processing unit), a time synchronization module, an FPGA (field-programmable gate array), a 1PPS+TOD (1pulse per second+time of day) time interface, an entry time stamp module, an exit time stamp module, a first PTP (precision time protocol) port and a second PTP port, wherein the FPGA is connected with the CPU through the time synchronization module; the first PTP port is connected with the CPU through the entry time stamp module; the second PTP port is connected with the CPU through the exit time stamp module; and the FPGA is also respectively connected with the CPU and the 1PPS+TOD time interface. The device and the method have the following advantages: through combination of software and hardware, nanosecond precision system time synchronization between master and slave stations in the packet transport network can be effectively and quickly implemented, and high precision timing of the whole network can be implemented.

This invention relates to methods and devices for synchronization using linear programming, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a two-dimensional linear programming technique for estimating clock offset and skew, particularly from two-way exchange of timing messages between a master and a slave device. Some embodiments include a skew and offset adjustable free-running counter for regenerating the master time and frequency at the slave device.

This invention relates to methods and devices for compensating for path asymmetry, particularly with reference to time and frequency synchronization. The invention has particular application where time and frequency synchronization over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP) is being carried out. Typically communication path delays between a time server (master) and a client (slave) are estimated using the assumption that the forward delay on the path is the same as the reverse delay. As a result, differences between these delays (delay asymmetries) can cause errors in the estimation of the offset of the slave clock from that of the master. Embodiments of the invention provide techniques and devices for compensating for path delay asymmetries that arise when timing protocol messages experience dissimilar queuing delays in the forward and reverse paths.

The invention provides an SOPC (System on a Programmable Chip) networking based sub-microsecond level clock synchronizing method. The clock synchronizing method comprises the steps of synchronizing UTC (Universal Time Coordinated) of a remote reference primary parent clock with UTC from an external GPS (Global Positioning System) clock or a Big Dipper system clock; synchronizing each node of a local first-level PTP (Precision Time Protocol) domain with the remote reference primary parent clock through a network switching device which supports a transparent clock function; receiving an optimal primary clock from a network at the same level by each Zynq platform based slave clock which supports IEEE158V2 protocol and gigabit Ethernet for time synchronization and frequency synchronization; when a PTP domain at the next level synchronizes with the primary parent clock through a border clock, performing clock synchronization by a primary clock at the upper level; and during the period that the PTP domain at the same level masters an independent clock synchronization control right, selecting the optimal primary clock as the primary clock of the network at the same level through an optimal primary clock algorithm. The invention also provides an SOPC networking based sub-microsecond level clock synchronizing system which adopts the clock synchronizing method.

This invention relates to methods and devices for time and frequency synchronization, especially over packet networks using, for example, the IEEE 1588 Precision Time Protocol (PTP). Timing protocol messages are exposed to artifacts in the network such as packet delay variations (PDV) or packet losses. Embodiments of the invention provide a recursive least squares mechanism for clock offset and skew estimation. A major potential advantage of such estimation is that it does not require knowledge of the statistics of the measurement noise and process noise. An implementation using a digital phase locked loop based on direct digital synthesis to provide both time and frequency signals for use at the slave (time client) is also provided.

A method and system is disclosed for clock synchronization in a wireless backhaul network, based on the IEEE1588 Precision Time Protocol (PTP). The network comprises a plurality of hubs, each hub serving one or more remote backhaul modules. Each hub comprises a slave clock, which communicates with a master clock through forward and reverse links. The method comprises, for each hub, estimating the frequency drift {circumflex over (α)} and offset {circumflex over (β)} from the forward and reverse links between the master and slave clock, estimating the accuracy of {circumflex over (α)} and {circumflex over (β)}, determining the least congested link, and adjusting the frequency of the slave clock based on {circumflex over (α)} and {circumflex over (β)} from the least congested link. A fixed or variable time window size is selected to achieve a desired accuracy of {circumflex over (α)} and {circumflex over (β)}. The method may comprise estimating a maximum holdover time for maintaining synchronization with a desired confidence level.

The invention is applicable in the technical field of network communication, and provides a realizing device of accurate time synchronization protocol, the device comprises a system initialization unit, initializing the realizing device of PTP (precision time protocol), preparing for running of PTP(precision time protocol); a human-computer interaction unit, providing one or more interactive interfaces, providing interact between users and the realizing device of the PTP(precision time protocol); a protocol engine unit, running PTP(precision time protocol); a hardware communication unit, stamping time for all PTP(precision time protocol) messages of engine unit organization of the protocol , transmitting the PTP(precision time protocol) messages with stamp between the master clock device and the vice clock device. The invention of realizing device of PTP(precision time protocol) runs the PTP(precision time protocol) in the network, realizing high-precision synchronization of the network clock, and solving all kinds of problems caused by error of clock synchronization or asynchronization in the current industrial control.

The invention discloses a method and device for achieving clock time synchronization, and relates to the Ethernet technology. The method comprises the steps of estimating the clock jitter and the clock frequency deviation with the difference of sending and receiving timestamp of a synchronous message packet and the difference of sending and receiving timestamp of a response message packet in a precision time protocol (PTP) message packet as observed values respectively to obtain the phase difference of a master clock and a slave clock, and carrying out the synchronization adjustment on the slave clock according to the estimated phase difference. The invention further discloses the device for achieving the clock time synchronization. According to the technical scheme, the state quantity is obtained by calculating measuring values respectively based on the kalman filtering algorithm and the combination (O+D and O-D) of the phase difference and the path delay, the estimated value for the clock synchronization phase difference is obviously far more superior to the estimated value, worked out through the single measuring value of the phase difference serving as the state value, for the clock synchronization phase difference , the phase difference can be reflected better and the synchronous precision between the master clock and the slave clock is greatly improved.

A system may include a plurality of subsystems, e.g. instrumentation units housed in separate chassis, each chassis including multiple instrumentation devices, e.g. data acquisition cards. Each subsystem may generate a local reference clock, which may be phase aligned and locked with respect to one or more similar reference clocks of other subsystems, via a high-level precision time protocol (PTP). Each instrumentation device within a given subsystem may generate its own sample clock based on the local reference clock, and may generate its own trigger clock based on its own sample clock. All trigger clocks may be synchronized with respect to each other through a future time event issued using the PTP, and each instrumentation device may then use its trigger clock to synchronize any received trigger pulses, which may also be issued through future time events using the PTP. This results in synchronizing the received triggers across all participating instrumentation devices across all participating subsystems, ensuring that data acquisition is properly synchronized across the multiple subsystems.

The invention provides a time synchronization method and a clock device, the limitation of a block port on a precision time protocol (PTP) synchronization message is cancelled, a local clock is amended according to the PTP synchronization message transmitted from an optimal path, as the hop count of routing of the PTP synchronization message is minimal, the cumulative error is also minimal and the time synchronization precision is further improved. Furthermore, when the PTP synchronization message is received through a slave port and the clock device has a master port, after clock information carried in the PTP message is amended, the master port is used for forwarding the PTP synchronization message so as to enable the follow-up clock device to conveniently perform precision time synchronization.