Method and device for achieving clock time synchronization

Abstract

The invention discloses a method and device for achieving clock time synchronization, and relates to the Ethernet technology. The method comprises the steps of estimating the clock jitter and the clock frequency deviation with the difference of sending and receiving timestamp of a synchronous message packet and the difference of sending and receiving timestamp of a response message packet in a precision time protocol (PTP) message packet as observed values respectively to obtain the phase difference of a master clock and a slave clock, and carrying out the synchronization adjustment on the slave clock according to the estimated phase difference. The invention further discloses the device for achieving the clock time synchronization. According to the technical scheme, the state quantity is obtained by calculating measuring values respectively based on the kalman filtering algorithm and the combination (O+D and O-D) of the phase difference and the path delay, the estimated value for the clock synchronization phase difference is obviously far more superior to the estimated value, worked out through the single measuring value of the phase difference serving as the state value, for the clock synchronization phase difference , the phase difference can be reflected better and the synchronous precision between the master clock and the slave clock is greatly improved.

Description

technical field [0001] The present invention relates to Ethernet technology, in particular to a method and device for realizing clock time synchronization. Background technique [0002] With the development of science and technology, people have higher and higher requirements for time accuracy, and the computer and network industries are all committed to solving the problem of insufficient timing synchronization capability of Ethernet. The Network Precision Clock Synchronization Committee has passed the IEEE1588 standard (referred to as PTP, Precision Time Protocol, precision clock synchronization protocol). IEEE1588 is based on Ethernet and distributed system applications, and its time synchronization accuracy can reach sub-microsecond level. The basic principles are as follows: figure 1 shown. figure 1 Among them, the Master Clock is the main clock, the Slave Clock is the slave clock, O is the phase difference Offset between the Slave Clock and the Master Clock, and D is ...

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Problems solved by technology

[0009] It can be seen from the above description that the above calculation of the path delay and phase difference is based on the delay from the Master Clock to the Slave Clock and the delay from the Slave Clock to the Master Clock. Changes in the environment will bring errors, which will cause inconsistencies in the two-way delay. Usually, the difference between the two may be tens of nanoseconds or may be greater in harsh environments, which also makes it possible to directly use the The accuracy of the clock synchronization algorithm needs to be further improved

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