46 results about "Clock time" patented technology

The invention discloses a time service synchronization method, a computer readable storage medium and electronic equipment, and the method comprises the steps: starting a high-frequency SPXO clock source in each preset period based on the timing of a low-frequency SPXO clock source, and enabling the high-frequency SPXO clock source to be aligned with a low-frequency clock moment after buffering; calculating the planned output time of the pulse time service signal by combining the high-frequency clock receiving window, the synchronous packet sending duration, the preset ToF correction window timing value and the latest ToF value; the synchronization packet sent by the host is received before the plan time, correction output time is determined according to the receiving moment, the ToF correction window timing value and the ToF value, and the host sends a pulse to the slave after sending the synchronization packet and passing through the ToF correction window; calculating correction and plan time deviation; performing clock taming on a low-frequency SPXO clock source and a high-frequency SPXO clock source through a multi-cycle deviation value to realize time service synchronization of the slave and the host; and then the high-frequency SPXO clock source is closed.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

This invention provides a method, system, device, and storage medium for in-baseband data synchronization. One method is applied to a master device, which is a baseband unit or its corresponding acceleration subsystem. The baseband unit and the acceleration subsystem form a master-slave relationship. The method includes: sending a 1pps+tod clock synchronization signal to the slave device via a reserved pin in a PCIe slot; acquiring clock time information from the master device based on the 1pps signal, and generating a first data synchronization pointer for the data to be transmitted based on the clock time information; and sending the data to be transmitted carrying the first data synchronization pointer to the slave device. This invention enables the transmission of clock synchronization signals between the master and slave devices using reserved pins in a PCIe slot. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing and reduces the capacity of the processor chip.

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

The application discloses a time updating method and system and a storage medium, relates to the technical field of vehicle-mounted distributed system consistency and time trust defense, and comprises the following steps: generating a time updating proposal entry; the time updating proposal entry comprises a proposed updating time; broadcasting the time updating proposal entry, so that a slave node calculates the difference between the proposed updating time and a local reference time and votes according to the difference and an acceptable interval radius; counting the number of votes in favor of the time updating proposal entry; when the number of votes in favor of the time updating proposal entry reaches a majority threshold, submitting the time updating proposal entry and broadcasting a time updating proposal entry submission notification, so that the slave node updates a wall clock time to the proposed updating time. The method can reduce the risk of false time diffusion.

The invention discloses a clock synchronization detection method, and relates to the technical field of clock synchronization, and the method comprises the steps: determining a reference clock in a clock system, and determining a conversion relation expression between the clock time of the reference clock and the clock time of other clocks; substituting the clock time of other clocks except the reference clock into the conversion relation expression to obtain clock time, and taking the clock time as first synchronous detection time corresponding to the reference clock; time obtained based on a preset synchronization algorithm is used as second synchronization detection time corresponding to the reference clock; comparing the first synchronous detection time with the second synchronous detection time to obtain a comparison detection result; and if the comparison detection result is abnormal, carrying out abnormal processing on the clock system. According to the invention, the synchronization algorithm of the clock system is detected based on the first synchronization detection time, and related processing is carried out when abnormality is detected.

The application provides an automatic navigation driving system with multiple clocks, which comprises: a first system on chip, which obtains a starting clock based on a first clock from a GNSS receiving module and / or a central gateway, generates a second clock according to a first local crystal oscillator based on the starting clock; a camera, which is triggered to expose according to the second clock; a laser radar; a millimeter wave radar; a micro control unit, which generates a third clock based on a second local crystal oscillator, and uses the third clock to time the millimeter wave radar, and stamps the second clock and the third clock time stamp in the millimeter wave radar sensing data according to the second clock and the third clock; a perception fusion module, which fuses the millimeter wave radar sensing data with the second clock time stamp and the third clock time stamp, the laser radar sensing data with the second clock time stamp, and the image data with the second clock time stamp.

The embodiment of the invention relates to the technical field of industrial networks, and discloses a real-time optimization method for an IgH EtherCAT master station, and the method comprises the steps: carrying out the real-time analysis of an EtherCAT frame header in a received data frame, so as to extract the frame feature information; monitoring a reference clock timestamp returned from one or more EtherCAT slave stations, and calculating an actual drift value sequence on a plurality of communication periods; predicting a predicted drift value of the next communication period by using the historical drift vector; the IgH master station kernel module adjusts the reference clock time sent to the slave station by superposing the predicted drift value to the reference clock time so as to provide feed-forward compensation; and if the change of the indication frame length of the extracted frame feature information exceeds a set threshold value, a reconfiguration module executed on the processing system dynamically reconfigures direct access to the storage descriptor ring. According to the scheme provided by the embodiment of the invention, lower and more stable communication delay and higher clock synchronization precision are realized.

The invention provides a time service method and a vehicle, the method is applied to the technical field of vehicle control, and the method comprises the steps that after a TBox system is started, the TBox system determines first system time, and the first system time comprises undetermined system time determined by the TBox system based on a verification result or target system time obtained by the TBox system from a host entertainment system; the TBox system adopts a first priority rule to determine second system time from first clock time and first system time obtained from a first external clock source; and adopting the second system time to carry out time service on the TBox system. According to the method, a plurality of virtual systems can be constructed in a system-on-chip, the plurality of virtual systems comprise a host entertainment system and a TBox system, and under the condition that the plurality of virtual systems share the same microcontroller unit, high-precision time service is still performed on the TBox system by adopting a first priority rule.

Disclosed example configurations include a playback device configured to, among other features, (i) receive reference clock timing; (ii) receive two or more data streams, where each data stream includes audio content and playback timing; (iii) for each data stream, generate sample-rate adjusted audio content for the data stream by adjusting a sample rate of at least a portion of the audio content of the data stream to compensate for a difference between a rendering clock at the playback device and the reference clock; (iv) generate a mix of the sample-rate adjusted audio content of the two or more data streams at the playback device; and (v) play the mix of the sample-rate adjusted audio content of each data stream based on a clock time of the rendering clock at the playback device and the playback timing information for each data stream.

The invention relates to a method for determining the control unit temperature in a motor vehicle by means of Ethernet, comprising the steps of: determining a transit time of a first signal on a first connection path between a first server ECU of the Ethernet vehicle electrical system and a second server ECU of the Ethernet vehicle electrical system; determining a maximum speed of the first connection path on the basis of the transit time; identifying at least a first server ECU of the Ethernet vehicle electrical system; synchronising at least a first server ECU of the Ethernet vehicle electrical system; determining the synchronisation interval; determining a timestamp of the first server ECU; reading a timestamp or querying the clock time of the first server ECU; comparing the timestamp with a reference clock of the Ethernet vehicle electrical system; carrying out a transit time measurement; determining the speed of the associated clock generator; determining the time difference of the synchronisation interval; determining the last synchronisation.

A method of determining latency in a network includes providing a plurality of nodes, the plurality of nodes including at least one origination node and at least one destination node; synchronizing clocks in the plurality of nodes; transmitting a packet from the origination node to the destination node; time stamping the packet with clock times from the synchronized clocks as the packet passes through nodes as the packet passes from the origination node to the destination node; and analyzing the stamped times to determine hop-to-hop times taken by the packet as the packet travelled from the origination node to the destination node. Other methods, devices, and systems are disclosed.

The present invention simplifies a process related to content reproduction. This control method includes causing a computation circuit to: transmit, to each of first and second reproduction devices, a request for requesting transmission of the time being counted; receive the time of day of a first internal clock from the first reproduction device that has responded to the request and derive a first difference that is the difference in the time of day between the first internal clock and a third internal clock; receive the time of day of a second internal clock from the second reproduction device that has responded to the request and derive a second difference that is the difference in the time of day between the second internal clock and the third internal clock; transmit, to the first reproduction device, a first control signal for reproducing first content at a first reproduction start time; and transmit, to the second reproduction device, a second control signal for reproducing second content at a second reproduction start time.

The application discloses a single monotone switching type successive approximation analog-digital converter using bottom plate sampling time sequence, comprising a sample-and-hold circuit, a comparator, a digital-analog converter, an asynchronous clock generation module, a multi-clock time-sharing control successive approximation control module and a digital error correction circuit. The successive approximation approximation control logic adopts multi-clock time-sharing control, and uses switch switching time sequence in the bottom plate sampling technology to replace the switch switching time sequence of the top plate sampling technology of the single monotone switching type successive approximation analog-digital converter. In the sampling stage, the input signal is connected to the top plate of the capacitor array of the digital-analog converter and the input end of the comparator through the sample-and-hold circuit, but the switch in the sample-and-hold circuit and the bottom plate control switch of the capacitor array are switched using the bottom plate sampling time sequence to complete the sampling of the signal. The digital-analog converter module adopts non-binary redundancy technology and a segmented architecture, reduces the number of unit capacitors, and improves the tolerance of the reference voltage establishment error in the conversion process.

The application discloses a distributed training resource scheduling method and device, equipment and storage medium, applied to the field of distributed training, and target jobs are screened from submitted jobs to construct an optimal job combination with the maximum value as the target; target nodes of the target jobs are screened from nodes based on network states between the nodes, target communication topologies of the target nodes are determined; the target jobs are determined in different communication frequencies under the network states, iteration rounds of different communication frequencies within a budget time are determined based on the clocking time, convergence analysis is performed based on the iteration rounds, and target communication frequencies are determined from the communication frequencies; and distributed tasks of the target jobs are trained in the target nodes based on the target communication frequencies and the target communication topologies. Global value maximization is realized through job screening, network topology optimization and dynamic adjustment of communication frequencies are performed based on network states and clocking time, and the training quality is guaranteed while the global value maximization is realized.

This invention discloses a communication delay calibration method and system for traversing a power safety zone. The method includes: Step 1, devices in Zone I and Zone III each set their local RTC clocks to the same time base, and device I simultaneously sends an electrical pulse to device III; Step 2, after receiving the electrical pulse, device III quickly records the millisecond-level difference Δt1 between its local RTC clock time and the time base; Step 3, after waiting for a certain period of time, device I sends a time-stamped data packet of its current RTC clock to device III through a network communication interface; Step 4, after receiving the time-stamped data packet, device III quickly unpacks it and records the difference Δt2 between its local RTC clock time and the time-stamped data packet; Step 5, device III's time synchronization program calculates |Δt2-Δt1| to obtain the difference and performs communication delay calibration. This invention can conveniently and quickly detect communication time errors between physically isolated safety zones in a power secondary system.

The application discloses a method for taming a rubidium atomic clock based on a sliding window dynamic compensation and related products, and belongs to the technical field of time-frequency synchronization. The method divides a sampling period into a first time length and a second time length, acquires long-wave-rubidium clock time difference data and constructs a time difference model, calculates the phase difference and the frequency deviation of the rubidium atomic clock by using a least square method, takes the phase difference and the frequency deviation as adjustment amounts when the cycle number is 1, otherwise, takes the change amount of the frequency deviation as an adjustment amount to adjust the rubidium atomic clock, retains the second time length data, acquires the first time length data after adjustment, compensates the data based on the frequency deviation change amount, updates the time difference data after splicing the compensated data and the retained second time length data, and repeatedly executes the taming of the rubidium atomic clock. The method can shorten the taming adjustment period of the rubidium atomic clock while maintaining the advantage that the long-wave timing signal has strong anti-interference capability, and improves the stability of the rubidium atomic clock.

A system for generating time encodings. The system comprises a timestamp generating circuit configured to periodically generate a timestamp; an internal clock system operationally connected to the timestamp generating circuit, whereby the timestamp generating circuit is further configured to periodically generate the timestamp based on the internal clock; at least one LED arranged in at least one array of the LED or LEDs, obtaining respectively for each array a LED clock. The timestamp generating circuit is further configured to convert the timestamp into a binary form, and control the LEDs in the at least one array to visually code in accordance with the binary form, whereby each one of the LEDs represents a bit in the binary form. The system further comprises at least one camera, each of the at least one camera having a corresponding field of view, whereby the at least one LED clocks are placed within a respective corresponding field of view of the at least one camera. The system further comprises a processing system configured to record image data from images output from the at least one camera, comprising for each image at least a representation of the LED clock visually coding the binary form physically, encoded with the image for retrieval of information.

The invention discloses a vernier-multiphase clock time-to-digital conversion method. The method comprises the following steps: generating two groups of multiphase clocks with different frequencies; when an initial signal edge arrives, starting a counter Cnt1 and latching the state of the first group of multi-phase clocks; when the stop signal edge arrives, starting a counter Cnt2 and latching the state of the second group of multi-phase clocks; monitoring the edges of the two counting clocks, and stopping counting when the two counting clocks are aligned for the first time; according to the latched phase state, fine counting correction values of the starting signal edge and the stopping signal edge in respective clock periods are calculated; and finally, the accurate time interval is calculated by integrating the rough counting value and the fine counting correction value. According to the invention, through combination of multi-phase clock interpolation and the vernier method, a nonlinear synchronization error in a traditional vernier method is converted into a deterministic system error, and the resolution, absolute precision and linearity of time measurement are significantly improved.

A kind of in-core bidirectional timer suitable for multi-core system includes ascending timer, countdown timer, adder and in-core timer interrupt module;The output of kernel clock is connected respectively with adder and in-core timer interrupt module;Ascending timer is used to realize absolute time point timing function, and the absolute time point configured is sent to in-core timer interrupt module;Countdown timer is used to realize relative time point timing function, and the countdown value configured is sent to adder;Adder converts the countdown value configured into ascending time value, and the converted ascending time value is sent to in-core timer interrupt module by ascending timer;In-core timer interrupt module, according to kernel clock time value in combination with the absolute time point configured, kernel clock ascending time arrives at the absolute time point, then generates interrupt signal, and informs interrupt controller timing end;According to kernel clock time value in combination with ascending time value, when countdown value reduces to 0, interrupt signal is generated, and informs interrupt controller timing end.

The invention discloses a high-speed source synchronous parallel interface sampling clock alignment method and device based on an FPGA (Field Programmable Gate Array), a medium and computer equipment in the technical field of clock time sequence optimization, and aims to solve the problems of sampling errors of a receiving end and the like caused by an incorrect clock data phase relation in the prior art. According to the invention, a dynamic PLL phase shift technology is adopted, phase adjustment is carried out on a clock signal, an adaptive optimal phase is accurately found, and data sampling time sequence optimization is realized, so that the data establishment time and retention time in the sampling process are both far greater than the minimum establishment time and retention time standard required by sampling; and the correctness and the stability of the data can still be kept under the requirement of high bandwidth.

The present invention relates to systems, methods and nodes for enabling synchronization between a plurality of nodes in a network, by comparing the times of the GPS clocks of the plurality of nodes to determine accurate clocks being within a tolerance of each other, adjusting priority, and, if the priority of a local clock of a node is low, selecting a remote GPS clock to be used as a timing reference of the GPS clock of the node.

To provide a new and innovative way of displaying time in analog clocks. [Solution] The hour hand 16 is configured to move back and forth within a 30° angle range clockwise from the starting point of a one-hour unit. This makes it easy to determine what hour it is. To know the exact time, one simply needs to check the position indicated by the minute hand 18, so it is possible to know the current time just like with a conventional analog clock. The back-and-forth movement of the hour hand 16 also serves as an indicator of the passage of seconds, making the functioning of the clock 10 visible through its movement.

The invention relates to the technical field of information security and time service, in particular to a satellite common-view and portable moving clock time synchronization time service system and method, which thoroughly avoids a network transmission path and realizes end-to-end physical isolation by introducing a physical carrying mechanism and a hardware-level one-way isolation module of a portable time service clock. And digital signature and verification are carried out on the time data in combination with a national secret SM2 / SM3 algorithm, so that the integrity, tamper resistance and identity authentication of the data are ensured, the security is fundamentally improved, and security vulnerabilities caused by network dependence in the prior art are effectively eliminated. In terms of deployment flexibility, the portable design overcomes the dependence on a fixed monitoring station in the prior art, and supports rapid deployment in a dynamic environment and a remote area. The beneficial effects jointly solve the defects of insufficient precision, high security risk, complex deployment and the like in the prior art, and provide reliable support for secret-related networks with high security requirements.

Embodiments include methods for a controller of a plurality of user equipment (UEs) that are served by a radio access network (RAN) node. Such methods include receiving information about the following from each of the UEs: first measurements, UEDL,RX, of respective timing events of the radio link between the UE and the RAN node; and second measurements, UERxTxDiff, of respective time differences between the UE receiving a downlink reference signal, RS, and transmitting a corresponding uplink RS. Such methods also include, based on the received information, selecting one of the plurality of UEs to provide a time-sensitive network (TSN) end station with a TSN message timestamped by a system clock time that is associated with the RAN and that is based on at least one first measurement and at least one second measurement. Other embodiments include complementary methods for a UE, and controllers and UEs configured to perform such methods.

A power consumption measurement endpoint comprising a local clock and a clock compensation module, wherein the clock compensation module is configured to receive a plurality of reference clock time updates output by a reference clock, record the time of the local clock at which the plurality of reference clock time updates were received, and determine an approximation function of the error progression between the local clock and the reference clock, and further configured to acquire the time of the local clock, determine the error between the local clock and the reference clock using the time of the local clock and the approximation function, calculate a compensated time using (i) the time of the local clock and (ii) the error between the local clock and the reference clock, and send at least one clock configuration message to the local clock based on the compensated time, and the local clock outputs a time update based on the clock configuration message.

An information processing apparatus acquires identification information about a wireless device detected by a detection apparatus which detects wireless devices, detection clock time information about a clock time at which the detection apparatus has detected the wireless device, and movement amount information about a movement amount by which the detection apparatus has moved between an optional first clock time and an optional second clock time, determines, with use of the movement amount information and detection clock time information and identification information about each of a plurality of wireless devices, relative positions of the plurality of wireless devices, and causes a display unit to display information about the determined relative positions of the plurality of wireless devices.