90 results about "Clock time" patented technology

A method is provided for configuring an SIL simulation of a control unit running on a computer, software modules for the control unit, which have a plurality of tasks, being installed on the computer for the SIL simulation of the control unit, the tasks being processed in a predetermined clock cycle having a periodic period between the individual clock time points, and the computer including a plurality of processor cores, on which a plurality of virtual machines run, which each process predetermined tasks. A possibility is thus provided for minimizing the computing time of an SIL test.

In one embodiment, a system includes a peripheral device, which includes an interface to receive from a virtual machine (VM) running on a host device, over a communication data bus, a request for timing data derived from a time measurement dialogue, the host device maintaining a master clock time, a hardware clock to maintain a peripheral device clock time, and processing circuitry to transform the master clock time to a frame of reference of the VM, and provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM.

In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.

The invention discloses a time service synchronization method, a computer readable storage medium and electronic equipment, and the method comprises the steps: starting a high-frequency SPXO clock source in each preset period based on the timing of a low-frequency SPXO clock source, and enabling the high-frequency SPXO clock source to be aligned with a low-frequency clock moment after buffering; calculating the planned output time of the pulse time service signal by combining the high-frequency clock receiving window, the synchronous packet sending duration, the preset ToF correction window timing value and the latest ToF value; the synchronization packet sent by the host is received before the plan time, correction output time is determined according to the receiving moment, the ToF correction window timing value and the ToF value, and the host sends a pulse to the slave after sending the synchronization packet and passing through the ToF correction window; calculating correction and plan time deviation; performing clock taming on a low-frequency SPXO clock source and a high-frequency SPXO clock source through a multi-cycle deviation value to realize time service synchronization of the slave and the host; and then the high-frequency SPXO clock source is closed.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

The application provides a high-precision timing method and device for Windows system real-time simulation, a storage medium and electronic equipment, and relates to the technical field of computers. The method comprises the following steps: comparing a first time corresponding to a current time with a second time corresponding to the current time, and generating a first comparison result; the first time is a processor clock time calculated based on an initial value of a high-resolution performance counter; the second time is calculated based on a sum of a simulation time of the current time and a timing precision control quantity; in the case that the first time corresponding to the current time is less than the second time corresponding to the current time, a preset time calibration algorithm is executed in a loop until the first time is greater than or equal to the second time; and a target simulation function is executed. The high-precision timing method and device for Windows system real-time simulation, the storage medium and the electronic equipment provided by the application are used for improving the timing precision of an operating system.

A power consumption metering terminal includes: a local clock; a clock compensation module configured to: receive a plurality of reference clock time updates output by a reference clock; recording the time of the local clock which receives the time update of the plurality of reference clocks; and determining an approximation function of error development between the local clock and the reference clock; wherein the clock compensation module is further configured to: obtain a time of a local clock; determining an error between the local clock and the reference clock using the time of the local clock and the approximation function; calculating a compensation time using (i) the time of the local clock and (ii) an error between the local clock and the reference clock; and transmitting at least one clock configuration message based on the compensated time to a local clock, the local clock outputting a time update based on the clock configuration message.

Disclosed herein are playback devices, groups of playback devices, and methods of operating playback devices and groupings thereof, wherein individual playback devices are configured to detect and correct clock rate drift by synchronizing a clock rate and perhaps clock time of a local clock to a remote time source.

This invention provides a method, system, device, and storage medium for in-baseband data synchronization. One method is applied to a master device, which is a baseband unit or its corresponding acceleration subsystem. The baseband unit and the acceleration subsystem form a master-slave relationship. The method includes: sending a 1pps+tod clock synchronization signal to the slave device via a reserved pin in a PCIe slot; acquiring clock time information from the master device based on the 1pps signal, and generating a first data synchronization pointer for the data to be transmitted based on the clock time information; and sending the data to be transmitted carrying the first data synchronization pointer to the slave device. This invention enables the transmission of clock synchronization signals between the master and slave devices using reserved pins in a PCIe slot. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing and reduces the capacity of the processor chip.

A functional device (130) for controlling a variable physical quantity (QU1A) comprises a timer (342) and a processing unit (331), wherein the variable physical quantity (QU1A) is characterized by a physical quantity target state (JE1U). The timer (342) senses a clock time (TH1A) to generate a sensing signal (SY81), wherein the clock time (TH1A) is characterized by a clock time application interval (HR1EU) represented by a measurement value application range (RQ1U). The processing unit (331) is coupled to the timer (342), obtains a measurement value (NY81) in response to the sensing signal (SY81), and brings the variable physical quantity (QU1A) into the physical quantity target state (JE1U) on condition that the processing unit (331) determines the clock time application interval (HR1EU) in which the clock time (TH1A) is currently located by checking a mathematical relationship (KQ81) between the measurement value (NY81) and the measurement value application range (RQ1U).

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

The application discloses a time updating method and system and a storage medium, relates to the technical field of vehicle-mounted distributed system consistency and time trust defense, and comprises the following steps: generating a time updating proposal entry; the time updating proposal entry comprises a proposed updating time; broadcasting the time updating proposal entry, so that a slave node calculates the difference between the proposed updating time and a local reference time and votes according to the difference and an acceptable interval radius; counting the number of votes in favor of the time updating proposal entry; when the number of votes in favor of the time updating proposal entry reaches a majority threshold, submitting the time updating proposal entry and broadcasting a time updating proposal entry submission notification, so that the slave node updates a wall clock time to the proposed updating time. The method can reduce the risk of false time diffusion.

1. The name of the design product: intelligent AI time manager (A6). 2. The use of the design product: time manager for displaying clock time, timing and countdown, etc. 3. The design points of the design product: in shape. 4. The picture or photo that best indicates the design points: perspective view 1.

The invention discloses a clock synchronization detection method, and relates to the technical field of clock synchronization, and the method comprises the steps: determining a reference clock in a clock system, and determining a conversion relation expression between the clock time of the reference clock and the clock time of other clocks; substituting the clock time of other clocks except the reference clock into the conversion relation expression to obtain clock time, and taking the clock time as first synchronous detection time corresponding to the reference clock; time obtained based on a preset synchronization algorithm is used as second synchronization detection time corresponding to the reference clock; comparing the first synchronous detection time with the second synchronous detection time to obtain a comparison detection result; and if the comparison detection result is abnormal, carrying out abnormal processing on the clock system. According to the invention, the synchronization algorithm of the clock system is detected based on the first synchronization detection time, and related processing is carried out when abnormality is detected.

A privilege information issuing apparatus includes: an acquisition unit that acquires entry qualification information with which a person with a schedule of entry to an event venue can enter the event venue through identity authentication; a calculation unit that calculates an extra time until a clock time that is attributable to a start of the event from a clock time at which the person with the schedule of entry is scheduled to arrive or arrives in a predetermined region including the event venue on the basis of the entry qualification information; an issuing unit that issues privilege information that are able to be used in one or more commercial facilities in a neighborhood of the event venue on the basis of the extra time; and a notification unit that notifies a terminal of the person with the schedule of entry of the issued privilege information.

The invention relates to a computer-implemented method for co-simulation using an HIL emulator and an SIL emulator, comprising: predetermining a periodic clock, a) initiating an SIL simulation step; b) when the SIL emulation step is completed, generating a message and sending it from the SIL emulator to the HIL emulator; c) receiving the message in a queue of the HIL emulator; d) reading a message from the queue of the HIL emulator at a clock time point and deleting the message in the queue, such that the message received first by the queue is read before the message received later and then deleted in the queue; e) repeating steps a) to d) until the co-simulation ends, a first SIL simulation step being started at a first clock time point and for a subsequent SIL simulation step: if the duration of the previous SIL simulation step is the maximum clock duration, then the next SIL simulation step is started at the corresponding next possible clock time point, and if the duration of the next SIL simulation step is the maximum clock duration, then the next SIL simulation step is started at the corresponding next possible clock time point; otherwise, the next SIL simulation step is started immediately after the previous SIL simulation step is completed.

The invention relates to a method of reference clock time synchronization in a wireless network, comprising: performing a connection time synchronization process to synchronize with a central device reference clock based on an established connection to a central device; receiving a callback message for time synchronization from the central device at the start and / or end of the connection interval, including a central device reference time corresponding to a local reference time of the central device at a point in time at which the callback message is sent to the peripheral device; calculating the number of past connection intervals between the transmission of the callback message by the central device and the reception of the callback message by the peripheral device, the reception of the callback message by the peripheral device being represented by the recorded local peripheral device reference time; determining a current time drift between receiving the reference time of the central device and recording the reference time of the local peripheral device based on the calculated number of connection intervals; the peripheral device reference time is adjusted to synchronize with the central device local reference clock based on the time offset according to the connected time synchronization process and based on the determined time drift.

In one embodiment, a synchronized communication system includes a first network device and a second network device, wherein the first network device includes a first physical hardware clock, and is configured to recover a reference clock time from packets received from a remote clock, find a clock differential between a clock time output by the first physical hardware clock and the recovered reference clock time, provide a control signal to the second network device responsively to the clock differential, and the second network device includes a second physical hardware clock, and is configured to adjust a clock time output by the second physical hardware clock responsively to the control signal.

The application provides an automatic navigation driving system with multiple clocks, which comprises: a first system on chip, which obtains a starting clock based on a first clock from a GNSS receiving module and / or a central gateway, generates a second clock according to a first local crystal oscillator based on the starting clock; a camera, which is triggered to expose according to the second clock; a laser radar; a millimeter wave radar; a micro control unit, which generates a third clock based on a second local crystal oscillator, and uses the third clock to time the millimeter wave radar, and stamps the second clock and the third clock time stamp in the millimeter wave radar sensing data according to the second clock and the third clock; a perception fusion module, which fuses the millimeter wave radar sensing data with the second clock time stamp and the third clock time stamp, the laser radar sensing data with the second clock time stamp, and the image data with the second clock time stamp.

The embodiment of the invention relates to the technical field of industrial networks, and discloses a real-time optimization method for an IgH EtherCAT master station, and the method comprises the steps: carrying out the real-time analysis of an EtherCAT frame header in a received data frame, so as to extract the frame feature information; monitoring a reference clock timestamp returned from one or more EtherCAT slave stations, and calculating an actual drift value sequence on a plurality of communication periods; predicting a predicted drift value of the next communication period by using the historical drift vector; the IgH master station kernel module adjusts the reference clock time sent to the slave station by superposing the predicted drift value to the reference clock time so as to provide feed-forward compensation; and if the change of the indication frame length of the extracted frame feature information exceeds a set threshold value, a reconfiguration module executed on the processing system dynamically reconfigures direct access to the storage descriptor ring. According to the scheme provided by the embodiment of the invention, lower and more stable communication delay and higher clock synchronization precision are realized.

Embodiments of the present application disclose a time synchronization adjustment method, device and electronic equipment. Embodiments of the present application obtain at least two groups of initial path delay data, wherein the time length of each group of initial path delay data is the same; perform data filtering on each group of initial path delay data to generate candidate path delay data; generate a target path delay according to at least two groups of candidate path delay data; and adjust a slave clock time according to the target path delay, so that the slave clock time is synchronized with a master clock time. Through the above method, the accuracy of path delay can be improved, and the accuracy of time synchronization adjustment between the master clock and the slave clock can be improved.

The invention discloses an NTP-based cut tobacco production time synchronization control system, and the system comprises an enterprise-level time server which is used for obtaining UTC time through double time sources and converting the UTC time into Beijing time, and the UTC time serves as a system time reference source; the workshop-level high-precision clock server is used for keeping time synchronization with the enterprise-level time server according to a first preset frequency through an NTP protocol and sending an NTP message to the programmable logic controller through the NTP protocol; the programmable logic controller is used for analyzing the received NTP message and synchronizing a PLC system clock; and the cut tobacco making equipment controller is used for requesting and acquiring the PLC system clock time from the programmable logic controller according to a preset period, and acquiring the time deviation between the PLC system clock time and the local clock so as to calibrate the local clock. The system effectively solves the problem of time deviation of cut tobacco making equipment.

The invention provides a time service method and a vehicle, the method is applied to the technical field of vehicle control, and the method comprises the steps that after a TBox system is started, the TBox system determines first system time, and the first system time comprises undetermined system time determined by the TBox system based on a verification result or target system time obtained by the TBox system from a host entertainment system; the TBox system adopts a first priority rule to determine second system time from first clock time and first system time obtained from a first external clock source; and adopting the second system time to carry out time service on the TBox system. According to the method, a plurality of virtual systems can be constructed in a system-on-chip, the plurality of virtual systems comprise a host entertainment system and a TBox system, and under the condition that the plurality of virtual systems share the same microcontroller unit, high-precision time service is still performed on the TBox system by adopting a first priority rule.

Disclosed example configurations include a playback device configured to, among other features, (i) receive reference clock timing; (ii) receive two or more data streams, where each data stream includes audio content and playback timing; (iii) for each data stream, generate sample-rate adjusted audio content for the data stream by adjusting a sample rate of at least a portion of the audio content of the data stream to compensate for a difference between a rendering clock at the playback device and the reference clock; (iv) generate a mix of the sample-rate adjusted audio content of the two or more data streams at the playback device; and (v) play the mix of the sample-rate adjusted audio content of each data stream based on a clock time of the rendering clock at the playback device and the playback timing information for each data stream.

The invention relates to a method for determining the control unit temperature in a motor vehicle by means of Ethernet, comprising the steps of: determining a transit time of a first signal on a first connection path between a first server ECU of the Ethernet vehicle electrical system and a second server ECU of the Ethernet vehicle electrical system; determining a maximum speed of the first connection path on the basis of the transit time; identifying at least a first server ECU of the Ethernet vehicle electrical system; synchronising at least a first server ECU of the Ethernet vehicle electrical system; determining the synchronisation interval; determining a timestamp of the first server ECU; reading a timestamp or querying the clock time of the first server ECU; comparing the timestamp with a reference clock of the Ethernet vehicle electrical system; carrying out a transit time measurement; determining the speed of the associated clock generator; determining the time difference of the synchronisation interval; determining the last synchronisation.

The invention relates to the field of clock time service, in particular to a partition enhanced hybrid logic clock time service method and system under a distributed system, and the method comprises the steps: dividing system nodes into a plurality of independent areas, and deploying main and standby area clock service nodes in each area; physical clock synchronization of all districts is achieved through a hardware clock synchronization protocol, a transaction is received, the transaction type is judged, and a mixed logic clock timestamp is requested from a district clock service node; based on the local physical time of the district corresponding to the district clock service node, the time reference value and the logic counter of the associated district, the district clock service node generates a mixed logic clock timestamp of the cross-district transaction; based on the local physical time and the logic counter, the district clock service node generates a mixed logic clock timestamp of the local transaction; and storing the mixed logic clock timestamp, and executing the transaction. The regional architecture effectively balances the global consistency and the local performance, and the main and standby clock nodes guarantee the high availability of the time service.

The application relates to the field of wireless communication and clock time service technology, and discloses a smart clock time service method and system based on wireless communication, which comprises the following steps: acquiring original time synchronization data of each signal source, combining interference characteristic values and fluctuation characteristic values to calculate initial quality evaluation values; screening high-quality signal sources to form a source subset and filtering the same as required to obtain smooth quality characteristic values; calculating weights based on the characteristic values, eliminating poor sources and ranking to obtain a source reliability ranking; selecting primary and secondary optimal reference sources, calculating quality difference characteristic values, updating the ranking as required in combination with environmental parameters; weighting and fusing the data of the primary and secondary optimal reference sources, calculating a consistency characteristic value, and outputting a final time synchronization parameter after reaching the standard. The application can realize accurate and stable clock time service, and improve the time service reliability and anti-interference capability.

In one embodiment, a network device includes a network interface to share time synchronization packets with at least one remote device over a network, a hardware clock to maintain a clock time, and packet processing circuitry to process the time synchronization packets according to a two-way time synchronization protocol in order to cause clock synchronization between the hardware clock and at least one clock of the at least one remote device.