156 results about "Clock time" patented technology

A sensor head transitions between a retracted and extended state. While retracted, sensors are covered. While extended, the sensors are exposed and may be used to acquire sensor data about the physical space. A force applied by a user, or a received command, may initiate transition. For example, a user may press on the sensor head to initiate retraction or extension. A motor provides a force to move the sensor head and generate haptic feedback, while a position encoder determines a displacement of the sensor head due to an external force being applied. Different applications of force by the user to the sensor head may result in different operations by the device. For example, a short push may retract the sensor head and disable the sensors for a specified time interval. In comparison a long push may retract the sensor head and disable the sensors until a specified clock time.

Method includes receiving a first delay time and a first timing measurement by a TMV from a first receiver at a first node. The first timing measurement is generated by comparing a first time associated with a first signal to a first local clock time. The first signal is transmitted by a transmitter at a source. The TMV receives from a second receiver at a second node in a network, a second delay time and a second timing measurement. The second timing measurement is generated by comparing a second time associated with a second signal to a second local clock time. The second signal is transmitted by the transmitter at the source. The TMV generates a correction factor time based on the first timing measurement, the first delay time, the second timing measurement, and the second delay time. The TMV transmits the correction factor time to the second node.

In one embodiment, a method includes synchronizing, by a camera device, a clock of the camera device to a shared clock time and applying, by the camera device, one or more shared camera parameters to a camera of the camera device. The method further includes determining, by the camera device, a position of the camera device relative to at least one of one or more peer camera devices capturing video of a scene in an environment of the camera device; capturing, by the camera of the camera device, a video of the scene in the environment of the camera device; and transmitting, by the camera device, the captured video of the scene to at least one of the one or more peer camera devices to form a composite video of the scene.

Clock times may be stored at nodes of a database system that are used to provide access to database data using Multi-Version Concurrency Control (MVCC) and implement isolation for distributed transactions. When an access request is received at a processing node of a database, the snapshot time of the access request is determined. The snapshot may be a range of time, with an earliest and latest timestamp. If the snapshot time has a latest time stamp greater than a current timestamp in the clock time, then the clock time may be updated. The clock time and snapshot time may be used to implement time-based MVCC to select a version of a tuple stored in the database to use for performing the access request.

Provided herein are systems and methods for simulating testing environments for digital therapeutic applications to address conditions over spans of time. A computing system may select a trigger from a plurality of triggers of an event scheduler for addressing a condition. The computing system may set a clock to a timestamp of the trigger, wherein the clock is accessible to the service and to the user device. The computing system may cause the service to transmit a message for addressing the condition to the user device, responsive to the timestamp of the clock corresponding to the timestamp of the trigger. The computing system may identify that the message is communicated between the service and the user device in accordance with the trigger. The computing system may determine that the trigger of the event scheduler is validated, responsive to identifying that the message is communicated.

The invention discloses a clock calibration system and method, and relates to the technical field of clock calibration. According to the clock calibration method, the clock parameter display time and the real-time display time are obtained in real time for error analysis, if the error exceeds a preset threshold value, historical operation, external environment and interference time sequence data are obtained, correction analysis is carried out to obtain a correction coefficient set, and the display time is calibrated based on the correction coefficient at the next time point. According to the method, the accuracy and comprehensiveness of calibration are greatly improved by comprehensively analyzing the historical operation time sequence data, the external environment time sequence data and the external interference time sequence data; particularly, by calculating an internal circuit correction index, a frequency drift correction index, an environment correction index and an interference correction index, the influence of dynamic factors on the clock time precision in a complex environment can be effectively compensated, and the problems of error accumulation and insufficient correction possibly caused by a single correction model are avoided.

Provided may be a computer system for payroll management wherein the stored program instructions cause the processor to correlate each of a plurality of employees to one of a plurality of scheduled positions and a payroll type; determine a scheduled start time, a scheduled end time, a scheduled location-in location, and a scheduled location-out location based on a work schedule for each of the employees; receive, via an employee device, a first scan time and a clock-in time; determine an actual clock-in location based on a clock-in geolocation generated by the employee device upon the generation of the clock-in input; receive, via the employee device, a last scan time and a clock-out time; determine an actual clock-out location based on a clock-out geolocation generated by the employee device upon the generation of the clock-out input; and determine a location-in distance and determine a location-out distance.

[Object]To more exactly synchronize clock times of a plurality of imaging apparatuses.[Solving Means]An information processing apparatus configured to synchronize, on the basis of speed information included in respective pieces of ranging information regarding moving objects corresponding to each other measured by a plurality of imaging apparatuses with use of light subjected to frequency continuous modulation, respective clock times of the plurality of imaging apparatuses.

The invention discloses a timing control system and method for a server, and relates to the technical field of timing control, and the system comprises a power supply unit, a switch unit, a level setting unit, a substrate management control unit, a real-time clock unit, an energy storage unit and a logic control unit. The energy storage unit is used for supplying power to the real-time clock unit under the condition that the power supply unit is powered off; the real-time clock unit is used for enabling the power supply unit through the switch unit in a conducting state under the condition that the server is in a shutdown state and an alarm clock is triggered; the substrate management control unit is used for reading the clock time of the real-time clock unit after electrification, controlling the logic control unit to be electrified if the clock time of the real-time clock unit is the preset startup time, and controlling the switch unit to be switched off after the logic control unit is electrified; and the level setting unit is used for enabling the power supply unit when the switch unit is in the off state. The problem that the server cannot be automatically started in the power-off state is solved.

A method is provided for configuring an SIL simulation of a control unit running on a computer, software modules for the control unit, which have a plurality of tasks, being installed on the computer for the SIL simulation of the control unit, the tasks being processed in a predetermined clock cycle having a periodic period between the individual clock time points, and the computer including a plurality of processor cores, on which a plurality of virtual machines run, which each process predetermined tasks. A possibility is thus provided for minimizing the computing time of an SIL test.

In one embodiment, a system includes a peripheral device, which includes an interface to receive from a virtual machine (VM) running on a host device, over a communication data bus, a request for timing data derived from a time measurement dialogue, the host device maintaining a master clock time, a hardware clock to maintain a peripheral device clock time, and processing circuitry to transform the master clock time to a frame of reference of the VM, and provide to the VM, over the communication data bus, the timing data based on the peripheral device clock time, and the master clock time transformed to the frame of reference of the VM.

In one embodiments, a system includes a network device including a host interface to receive time synchronization messages generated by software executed by a processing unit of a host device, a hardware clock to maintain a clock time, scheduler circuitry to manage periodic transmission of the time synchronization messages according to the clock time and schedule data provided by the software, and a network interface to transmit the time synchronization messages to at least one clock synchronization follower according to the schedule data and the clock time.

The present disclosure provides for an architecture for a multi-interface card environment, such as a server that includes multiple network interface cards (NICs) or peripheral component interconnect express (PCIe) cards. The architecture includes a passive optical splitter coupled between a leader clock and the multiple interface cards or PCIes. The optical splitter can be used to distribute clock time from the leader clock to the interface cards. The architecture provides for distribution of timing in a scalable manner in the multi-NIC environments for cloud deployments.

1. The name of the product of this design: Time Manager (T5). 2. Purpose of this design product: used for time management such as displaying clock time, timing and countdown. 3. The key design point of this design product lies in the combination of shape and pattern. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The invention discloses a time service synchronization method, a computer readable storage medium and electronic equipment, and the method comprises the steps: starting a high-frequency SPXO clock source in each preset period based on the timing of a low-frequency SPXO clock source, and enabling the high-frequency SPXO clock source to be aligned with a low-frequency clock moment after buffering; calculating the planned output time of the pulse time service signal by combining the high-frequency clock receiving window, the synchronous packet sending duration, the preset ToF correction window timing value and the latest ToF value; the synchronization packet sent by the host is received before the plan time, correction output time is determined according to the receiving moment, the ToF correction window timing value and the ToF value, and the host sends a pulse to the slave after sending the synchronization packet and passing through the ToF correction window; calculating correction and plan time deviation; performing clock taming on a low-frequency SPXO clock source and a high-frequency SPXO clock source through a multi-cycle deviation value to realize time service synchronization of the slave and the host; and then the high-frequency SPXO clock source is closed.

Examples are disclosed that relate to fairly ordering financial market trades received from different market participant computers via a cloud computing network. In one example, a plurality of trades generated by a plurality of market participant computers are received. The trades are generated based at least on a financial market data point received by the plurality of market participant computers. Each trade is tagged with a delivery clock time stamp that tracks time in relation to financial market events that occur at a corresponding market participant computer. The trades are ordered based on the delivery clock time stamps and sent to a central exchange server computer. The central exchange server computer processes the trades.

In one embodiment, a peripheral device includes an oscillator, a counter to be driven by the oscillator and provide a peripheral device counter value, and processing circuitry to receive a host device counter value from a host device, read host device clock translation parameters from a host memory of the host device, the host device clock translation parameters providing translation between the host device counter value and a host device clock time, read peripheral device clock translation parameters providing a translation between the peripheral device counter value and a peripheral device clock time, read the peripheral device counter value, compute a clock correction as a function of a difference between the host device clock time and the peripheral clock time, based on the host device and peripheral device counter values and clock translation parameters, and correct the host device or peripheral device clock translation parameters based on the clock correction.

The application provides a high-precision timing method and device for Windows system real-time simulation, a storage medium and electronic equipment, and relates to the technical field of computers. The method comprises the following steps: comparing a first time corresponding to a current time with a second time corresponding to the current time, and generating a first comparison result; the first time is a processor clock time calculated based on an initial value of a high-resolution performance counter; the second time is calculated based on a sum of a simulation time of the current time and a timing precision control quantity; in the case that the first time corresponding to the current time is less than the second time corresponding to the current time, a preset time calibration algorithm is executed in a loop until the first time is greater than or equal to the second time; and a target simulation function is executed. The high-precision timing method and device for Windows system real-time simulation, the storage medium and the electronic equipment provided by the application are used for improving the timing precision of an operating system.

A power consumption metering terminal includes: a local clock; a clock compensation module configured to: receive a plurality of reference clock time updates output by a reference clock; recording the time of the local clock which receives the time update of the plurality of reference clocks; and determining an approximation function of error development between the local clock and the reference clock; wherein the clock compensation module is further configured to: obtain a time of a local clock; determining an error between the local clock and the reference clock using the time of the local clock and the approximation function; calculating a compensation time using (i) the time of the local clock and (ii) an error between the local clock and the reference clock; and transmitting at least one clock configuration message based on the compensated time to a local clock, the local clock outputting a time update based on the clock configuration message.

Disclosed herein are playback devices, groups of playback devices, and methods of operating playback devices and groupings thereof, wherein individual playback devices are configured to detect and correct clock rate drift by synchronizing a clock rate and perhaps clock time of a local clock to a remote time source.

This invention provides a method, system, device, and storage medium for in-baseband data synchronization. One method is applied to a master device, which is a baseband unit or its corresponding acceleration subsystem. The baseband unit and the acceleration subsystem form a master-slave relationship. The method includes: sending a 1pps+tod clock synchronization signal to the slave device via a reserved pin in a PCIe slot; acquiring clock time information from the master device based on the 1pps signal, and generating a first data synchronization pointer for the data to be transmitted based on the clock time information; and sending the data to be transmitted carrying the first data synchronization pointer to the slave device. This invention enables the transmission of clock synchronization signals between the master and slave devices using reserved pins in a PCIe slot. The slave device performs local clock synchronization based on the received synchronization signal and extracts data based on the synchronization pointer. This improves the synchronization accuracy of data processing and reduces the capacity of the processor chip.

The embodiment of the invention discloses an authentication method and device, equipment and a medium, and the method comprises the steps: obtaining the current time information according to a long-wave signal received by a long-wave receiving module; calibrating local real-time clock time according to the current time information, and generating a random temporary password based on the calibrated local real-time clock time and a set encryption algorithm; and authenticating the user according to the random temporary password.

A functional device (130) for controlling a variable physical quantity (QU1A) comprises a timer (342) and a processing unit (331), wherein the variable physical quantity (QU1A) is characterized by a physical quantity target state (JE1U). The timer (342) senses a clock time (TH1A) to generate a sensing signal (SY81), wherein the clock time (TH1A) is characterized by a clock time application interval (HR1EU) represented by a measurement value application range (RQ1U). The processing unit (331) is coupled to the timer (342), obtains a measurement value (NY81) in response to the sensing signal (SY81), and brings the variable physical quantity (QU1A) into the physical quantity target state (JE1U) on condition that the processing unit (331) determines the clock time application interval (HR1EU) in which the clock time (TH1A) is currently located by checking a mathematical relationship (KQ81) between the measurement value (NY81) and the measurement value application range (RQ1U).

[Problem] To provide an underwater acoustic communication system capable of realizing clock calibration by wireless means. [Solution] This underwater acoustic communication system comprises: a first wave transmission / reception unit which comprises a clock part and is configured so as to transmit a first ultrasound message at a first clock time measured in the clock part; and a second wave transmission / reception unit which is configured so as to receive the first ultrasound message, acquire a second clock time at which the first ultrasound message was received, calculate one-way propagation time between the first clock time and the second clock time, and transmit a second ultrasound message including the one-way propagation time. The first wave transmission / reception unit is further configured so as to: receive the second ultrasound message; extract the one-way propagation time from the second ultrasound message; acquire a third clock time at which the second ultrasound message was received and which is measured in the clock part; calculate a round propagation time between the first clock time and the third clock time; and adjust the clock time of the clock part on the basis of the one-way propagation time and the round propagation time.

The present invention discloses a virtual cluster time synchronization method based on PCIe passthrough, belonging to the technical fields of virtualization and network time synchronization. First, based on the PCIe passthrough technology, the virtual cluster nodes are bound to the underlying clock card to obtain the underlying physical clock time; then, a soft interrupt signal is generated through a timer to enable the virtual nodes to read the clock information of the underlying physical clock card at the same agreed time, while measuring the timer delay and correcting the time read from the clock card in real time; finally, the clock error between the virtual cluster nodes can be obtained by calculating the physical time values of the two clock cards. The present invention utilizes the high-precision hardware of the clock card and, with the help of the PCIe passthrough technology of the virtual machine, can accurately achieve the measurement of system time synchronization between virtual clusters.

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

The present disclosure provides for an architecture for a multi-interface card environment, such as a server that includes multiple network interface cards (NICs) or peripheral component interconnect express (PCIe) cards. The architecture includes a passive optical splitter coupled between a leader clock and the multiple interface cards or PCIes. The optical splitter can be used to distribute clock time from the leader clock to the interface cards. The architecture provides for distribution of timing in a scalable manner in the multi-NIC environments for cloud deployments.

The present application discloses a server timing control system and method, relating to the field of timing control technology, comprising a power supply unit, a switch unit, a level setting unit, a baseboard management control unit, a real-time clock unit, an energy storage unit, and a logic control unit; the energy storage unit is used to supply power to the real-time clock unit when the power supply unit is powered off; the real-time clock unit is used to enable the power supply unit via the switch unit in the on state when the server is in the off state and the alarm is triggered; the baseboard management control unit is used to read the clock time of the real-time clock unit after power-on, and if the clock time of the real-time clock unit is the preset power-on time, control the logic control unit to power on, and control the switch unit to disconnect after the logic control unit is powered on; the level setting unit is used to enable the power supply unit when the switch unit is in the disconnected state. The present application solves the problem that a server cannot automatically power on when it is powered off.

The application discloses a time updating method and system and a storage medium, relates to the technical field of vehicle-mounted distributed system consistency and time trust defense, and comprises the following steps: generating a time updating proposal entry; the time updating proposal entry comprises a proposed updating time; broadcasting the time updating proposal entry, so that a slave node calculates the difference between the proposed updating time and a local reference time and votes according to the difference and an acceptable interval radius; counting the number of votes in favor of the time updating proposal entry; when the number of votes in favor of the time updating proposal entry reaches a majority threshold, submitting the time updating proposal entry and broadcasting a time updating proposal entry submission notification, so that the slave node updates a wall clock time to the proposed updating time. The method can reduce the risk of false time diffusion.

A long-endurance high-precision timekeeping and time dissemination terminal and method of the present invention relate to the field of time synchronization, and include: a low-power MCU chip, a high-precision 1PPS phase discrimination chip, and a voltage-controlled crystal oscillator; the MCU chip includes a 1PPS generation module, a 1PPS phase discrimination control module, a PID control module, a temperature compensation module, and a time conversion module; the 1PPS generation module obtains an external standard 1PPS+ToD signal, and generates a local 1PPS signal and a delayed 1PPS signal; the 1PPS phase discrimination control module controls the 1PPS phase discrimination chip to compare the external standard 1PPS signal and the delayed 1PPS signal; the PID control module adjusts the voltage control value of the voltage-controlled crystal oscillator; the temperature compensation module performs frequency compensation on the voltage-controlled crystal oscillator according to the ambient temperature detected in real time; the voltage-controlled crystal oscillator provides a reference clock for the MCU chip; the time conversion module converts the external standard ToD signal into Beidou time to disseminate time to Beidou user equipment. The present invention can achieve a long-endurance timekeeping days and high timekeeping accuracy, meeting the requirements for accurate time of Beidou user equipment.