35 results about "Error detection code" patented technology

Redundant data storage includes performing a first data transfer to a first storage device as part of a redundant write operation. A first error detection code is generated for the first data transfer. A second data transfer is performed to a second storage device as part of the redundant write operation. A second error detection code is generated for the second data transfer. The first error detection code is compared with the second error detection code for a match indicating that data of the first data transfer matches data of the second data transfer.

Embodiments of the invention relate to a MAC PDU comprising MAC subheader and MAC SDU pairs encoded with error detection codes. More specifically, a first communication device (100) transmits a MAC PDU to a second communication device (300). The MAC PDU comprises at least one MAC subheader and MAC SDU pair. The at least one MAC subheader and MAC SDU pair comprises a plurality of data fields appended to the MAC subheader and being encoded with a first error detection code, and the plurality of data fields comprising a first data field indicating a length of a pay load of the MAC SDU and a second data field indicating a length of at least the MAC subheader and a header stack of the MAC SDU, and the MAC subheader and the header stack are encoded with a second error detection code. Furthermore, embodiments of the invention also relate to a first and a second communication device, corresponding methods and a computer program.

A method performed by a wireless device to determine how long the wireless device can operate in a different mode. The method includes receiving a physical layer protocol data unit (PPDU) carrying an initial control frame, determining whether contents of the PPDU leading up to an intermediate error detection code field are valid using an error detection code extracted from the intermediate error detection code field, responsive to determining that the contents are valid, switching from operating in a first operation mode to operating in a second operation mode before completely receiving the PPDU, and determining a duration for which the wireless device can operate in the second operation mode based on the duration from the start of the preamble of the PPDU to the end of the intermediate error detection code field and the duration of the PPDU.

A method for manufacturing a reused battery system (1) is provided with: a used battery management unit (10) receiving characteristic map data (1P) corresponding to the state after the start of reuse of the used battery; the management unit (10) verifies the received characteristic mapping data (1P) using the error detection code attached to the characteristic mapping data (1P); and if the received characteristic mapping data (1P) is correct, the management unit (10) stores the characteristic mapping data (1P) in the storage unit (101).

Disclosed are a method of transmitting and receiving image signals and an image processing device for implementing the same, by which an error detection code for verification of image related data can be provided in transmitting the image related data to a receiving side from a transmitting side. The disclosure includes generating a control field frame including Average Picture Level (APL) data of image data and an error detection code for the APL data, transmitting the generated control field frame in a vertical blanking period according to a serial interface system, and transmitting pixel data of the image data in a vertical non-blanking period according to the serial interface system.

This invention relates to a log management method and a log management system. Embodiments for reliable, safety-critical system logs are disclosed. In one embodiment, a method includes: obtaining data to be added to a log; creating entries for the data; and adding the entries to a linked sequence of entries in the log, wherein the linked sequence of entries includes a plurality of data entries and a plurality of sentinels intertwined with the plurality of data entries, wherein each data entry in the entry chain is appended to an error detection code calculated for that entry and a previously calculated error detection code or error detection root of the preceding data entry, and each sentinel in the entry chain includes an error detection code calculated for that sentinel and a previously calculated error detection code or error detection root of the preceding data entry, and each sentinel includes a previously calculated and encrypted blockchain value or blockchain root value of the preceding sentinel.

A completely de-energizable defibrillator is provided, allowing the electrical components of the defibrillator to be electrically unbiased while the defibrillator is not in use. The energizing of the defibrillator can be controlled through a power switch interfaced to a relay, with the microcontroller of the AED being able to de-energize the circuitry in case of unintended activation. Additionally, the microcontroller unit of the AED includes features to prevent computational errors due to external influences, electromagnetic interference, radio frequency interference, ionizing radiation, high energy particles, cosmic radiation, and / or solar radiation, or a combination thereof, including one or more pairs of lockstep processors, error detection code, and features that prevent tampering with the microcontroller.

A communication method according to one embodiment of the present invention is used in a mobile communication system. The communication method includes a step in which a reader device, which is a network node or a user device of the mobile communication system, receives a first message transmitted from an ambient Internet of Things (IoT) device. In addition, the communication method includes a step in which the reader device generates an error detection code on the basis of data included in the first message. Further, the communication method includes a step in which the reader device transmits a second message including an error detection code to the ambient IoT device. Further, in the ambient IoT device, a contention resolution is determined on the basis of the error detection code of the data included in the first message and the error detection code included in the second message.

A system and related method includes a memory and processing circuitry to receive data and corresponding expected error detection code values. The processing circuitry processes data in the at least two portions by calculating and storing error detection code values for the respective portions in the memory. The processing circuitry is then to calculate a total error detection code value based on the respective error detection code values of the at least two portions. When the total error detection code value does not match the expected error detection code value, the processing circuitry is to correct the at least one portion and to correct the at least one portion by calculating an updated error detection code value for a respective one of the corrected portions and calculating an updated total error detection code value based on the updated error detection code value for each corrected portion and the stored error detection code value. The corrected portion is processed.

Light-emitting diode (LED) packages and more particularly error detection in LED packages is disclosed. LED packages are arranged for cascade communication as part of a larger LED display. A separate active electrical element is integrated with each LED package for facilitating active matrix addressing from a data stream, checking input error detection codes, and generating new output error detection codes to the data stream. Each electrical element within each LED package is separately capable of changing one or more portions of received data in the data stream, transmitting the changed data to the next downstream LED package, and generating output error detection codes based on the changed data. When the active electrical element identifies corrupted data based on input error detection codes, the generated output error detection codes may be intentionally corrupted so downstream LED packages will also identify the respective data as being corrupted.

The invention discloses a digital phased-array antenna synchronization method and device, particularly relates to the field of digital communication, and is used for solving the problem that framing boundaries and time identifier mapping of service data streams are difficult to stably align under the conditions of cache jitter and clock micro-drift. The sending end inserts a first synchronous anchor frame and a second synchronous anchor frame after the calibration synchronization is triggered, writes an alignment element identifier and a count value of a sending sampling counter, and registers a sending cache record table; a receiving end verifies the error detection code, pairs anchor frames according to a fixed anchor spacing rule, calculates an alignment offset and a forward inter-anchor stepping steady-state length, and generates an alignment proof message; checking the sending cache record table and the proof code, counting that the return proof reaches consistent continuity, indexing an offline training confidence matrix and outputting an alignment credibility level, and when conditions are met, updating framing boundary and time identifier mapping and sending a mapping effective message; and the receiving end starts the mapping version identifier, rechecks the stability of the alignment offset by means of the monitoring anchor frame, and sends a resynchronization request when the alignment offset fails.

This invention discloses a data verification method, a distributed system, and a storage medium. The method includes: a first server receiving a first acquisition request from a second server for requesting target data, and converting the target data into first error detection information using a preset processing algorithm; the first error detection information includes a first parity error detection code; the second server receiving the first error detection information and the target data encapsulated and transmitted by the first server, and generating a second parity error detection code based on the received first error detection information; the second server confirming whether the second parity error detection code matches the first parity error detection code; if the second parity error detection code does not match the first parity error detection code, the second server determining that the target data transmission is erroneous, and resending a second acquisition request to the first server for requesting new target data. This invention ensures data transmission consistency and improves data verification speed and efficiency.

A first flit is generated according to a first flit format, where a first number of error detection codes are to be provided for an amount of data to be sent in the first flit, and the first flit is to be sent on a link by the transmitter while the link operates with a first link width. The link transitions from a first link width to a second link width, where the second link width is narrower than the first link width. A second flit is generated according to a second flit format based on the transition to the second link width, where the second flit is to be sent while the link operates at the second link width, and the second flit format defines that a second, higher number of error detection codes are to be provided for the same amount of data.

A self-managed DRAM module and method. The module includes a plurality of DRAM chips; and a controller chip configured to store a data block received from a host according to a process that includes: compressing the data block to generate a compressed data block; performing error detection code (EDC) encoding on the compressed block and adding an EDC redundancy to the compressed block; partitioning the compressed block with the EDC redundancy into a set of m data chunks; performing error correction code (ECC) encoding on each of the m data chunks to generate m codewords; and writing the m codewords to the DRAM chips.

A method, computer program product, and computing system for processing a plurality of packets transmitted from a first computing device to a second computing device. A packet sequence number associated with each packet is identified. An error-detecting code representation is generated using the packet sequence number of each packet. The error-detecting code representation is compared with an error-detecting code representation generated from a sequence of expected packet sequence numbers associated with transmission of a plurality of expected packets. A notification indicating that a packet is missing from the plurality of expected packets is generated when the error-detecting code representation is not equal to the error-detecting code representation generated from the sequence of expected packet sequence numbers.

The present disclosure provides a memory, a cartridge, and a printing system. These cartridges, equipped with the memory, can reduce the likelihood that a printing device will determine a product as non-authentic based on electronic signature verification results, regardless of authenticity, due to data corruption. The memory stores manufacturing information, including at least the number of times the liquid contained in the cartridge has been refilled after consumption (i.e., the refill count); an electronic signature for the manufacturing information; and a first error detection code for the manufacturing information.

A load control device includes a device that has a plurality of operation modes depending on applications and is electrically connected to a load. The device includes an operation mode determination circuit. The operation mode determination circuit is configured to: set a tentative operation mode indicating the operation mode before determination; obtain operation mode information regarding the operation mode via communication, the operation mode information including an error detection code for detecting an error of the tentative operation mode; determine whether or not a setting result of the tentative operation mode is correct using the error detection code; and determine the operation mode of the device based on a determination result.

Systems and methods for error detection in video data are described. An encoding computing system can receive a video frame. The encoding computing system can encode and decode the video frame based on an encoding scheme. The encoding computing system can generate a frame error detection code for the decoded video frame based on an error detection code generation scheme. The encoding computing system can send the encoded video frame and the error detection code to a decoding computing system. The decoding computing system can decode the encoded video frame and generate a second error detection code using the code generation scheme. The decoding computing system can detect a decoded video frame corruption by comparing the error detection code and the second error detection code.

A completely de-energizable defibrillator is provided, allowing the electrical components of the defibrillator to be electrically unbiased while the defibrillator is not in use. Additionally, the microcontroller unit of the AED includes features to prevent computational errors due to external influences, electromagnetic interference, radio frequency interference, ionizing radiation, high energy particles, cosmic radiation, and / or solar radiation, or a combination thereof, including one or more pairs of lockstep processors, error detection code, and features that prevent tampering with the microcontroller.

Embodiments refer to applications, platforms, architectures, etc., for authenticating and initializing a peripheral device. For example, one or more initialization operations may be performed on the peripheral device before it is authenticated. In these and other embodiments, authentication may be based on information maintained during initialization, such as error detection code values ​​and / or message counter values. Performing the authentication and initialization operations in the disclosed manner can reduce the time required for authenticating and initializing peripheral devices compared to the typical practice of authenticating first and then initializing.

A display control system includes: a processing device; and a circuit device configured to perform display control on a display device under control of the processing device. The processing device outputs an expected value of an error detection code of a specific still image in a predetermined frame of a video displayed on the display device, and the circuit device includes an error check circuit that receives image data of the video from the processing device, calculates an error detection code value of the specific still image in the predetermined frame, and checks an error by comparing the error detection code value with the expected value.

This communication device wirelessly communicates with a device to which power is supplied by energy harvesting, and comprises: a control unit that determines addition of an error detection code to both or one of a control signal and a data signal to be transmitted to the device; and a transmission unit that transmits, on one physical channel, the control signal and / or the data signal to which the error detection code is added.

A semiconductor device includes a first semiconductor die including a first interface circuit; and a second semiconductor die stacked with the first semiconductor die and including a second interface circuit connected to the first semiconductor die by a plurality of via structures, wherein the first interface circuit is configured to generate an error detection code for transmission data and transmit the data signal including the transmission data and the error detection code to the second interface circuit through at least some of the plurality of via structures, and the second interface circuit is configured to generate response data indicating whether the data signal is normally received and an error correction code of the response data, and transmit a response signal including the response data and the error correction code to the first interface circuit through at least one via structure among the plurality of via structures.

A fault detection system includes a state register, an error detection code (EDC) register, logic circuitry, an EDC generator, and an EDC checker. The state and EDC registers store first reference data and first checksum data, respectively. The logic circuitry executes a logic function based on the first reference data to iteratively generate second reference data that is different from the first reference data, and updates the first reference data of the state register with the second reference data of one iteration. The EDC generator iteratively generates second checksum data based on the iteratively generated second reference data and updates the first checksum data of the EDC register with the second checksum data of one iteration. The EDC checker detects a fault in the IC based on the updated first reference data and the updated first checksum data.

This quantum error detection device generates a logical state |+⟩ L, 1 of a first quantum error detection code that is a quantum error detection code representing one logical qubit by n1 physical qubits and is a quantum error detection code having a code distance d1. The quantum error detection device executes a logical Rz rotation gate operation of the first quantum error detection code with respect to the logical state |+⟩ L, 1 of the first quantum error detection code, thereby generating a logical state |+θ⟩ L, 1 of the first quantum error detection code. The quantum error detection device executes a sequence of unitary quantum gate operations with respect to the logical state |+θ⟩ L, 1 of the first quantum error detection code, thereby converting the logical state |+θ⟩ L, 1 of the first quantum error detection code into a second quantum error detection code representing one logical qubit by n2 (n2 > n1) physical qubits. The quantum error detection device acquires an error syndrome of a logical state |+θ⟩ L, 2 of the second quantum error detection code.

Light-emitting diode (LED) packages and more particularly error detection in LED packages is disclosed. LED packages are arranged for cascade communication as part of a larger LED display. A separate active electrical element is integrated with each LED package for facilitating active matrix addressing from a data stream, checking input error detection codes, and generating new output error detection codes to the data stream. Each electrical element within each LED package is separately capable of changing one or more portions of received data in the data stream, transmitting the changed data to the next downstream LED package, and generating output error detection codes based on the changed data. When the active electrical element identifies corrupted data based on input error detection codes, the generated output error detection codes may be intentionally corrupted so downstream LED packages will also identify the respective data as being corrupted.

A code generation device 1 which generates code in which parameter setting in an API call has been corrected comprises: a detection code addition unit 11 which generates second code by adding API error detection code for detecting an error related to a defect in API parameter setting to first code containing API call processing; a code execution unit 12 which executes the second code, and if said error is not detected, outputs the second code as code in which parameter setting in the API call has been corrected, and if said error is detected, stores the execution result of the code containing the error; a prompt creation unit 13 which creates a prompt containing the second code, the code execution result, and an instruction text for correcting the second code on the basis of the code execution result, and which inputs the prompt to a learning server; and a corrected code re-input unit 14 which re-inputs the corrected code output from the learning server to the code execution unit as second code.

A method of controlling memory access for an embedded computer program is proposed, in the development phase, the computer program being executed in a device comprising a memory unit (115), the memory unit comprising a useful data storage space (120) and a corresponding storage space for error detection codes or error correction codes (125), called error codes, the method comprising, storing a state indicator in a location of the error code storage space,the stored state indicator being independent of a useful data stored in a corresponding location of the useful data storage space and being representative of a state of the location of the useful data storage space and a detection of a memory access error in a location of the useful data storage space depending on a state indicator stored in a corresponding location of the error code storage space. Figure for the abstract: Fig. 1,

The invention relates to device initialization and authentication for computing systems and applications. Various embodiments relate to applications, platforms, architectures, and the like for authenticating and initializing peripheral devices. For example, before the peripheral device is authenticated, one or more initialization operations with respect to the peripheral device may be performed. In these and other embodiments, authentication may be based on information maintained during initialization, such as error detection code values and / or message counter values. Performing the authentication and initialization operations in the disclosed manner may reduce the amount of time used to authenticate and initialize the peripheral device as compared to as typically done to authenticate first and then initialize.