39 results about "Single cycle" patented technology

The invention is suitable for the technical field of computer processor design, and provides an instruction processing method and device, terminal equipment and a program product, and the method comprises the steps: obtaining instruction information of a to-be-processed instruction set in a processor; generating an index vector corresponding to the to-be-processed instruction set based on the original effective vector; each index value in the index vector is subjected to one-hot code conversion, a one-hot code matrix corresponding to the instruction set to be processed is generated, and each row of one-hot code vector in the one-hot code matrix corresponds to each path of input instruction; and according to the original effective vector and the one-hot code matrix, sorting operation codes of each path of input instruction to obtain processed operation code information, so that a processor executes corresponding operation based on the processed operation code information. The method can meet the requirement that the high-performance processor completes instruction processing in a single cycle, the processing delay is low, and therefore the instruction execution efficiency of the processor is improved.

Systems and methods are disclosed for reduced-power serial data links. A clock-forwarded serial link carries a clock lane and one or more data lanes. Every active serial data cycle is accompanied by its own serial clock edge: a clock delay allows the same clock edge to drive data at a transmitter and latch data at a receiver. Power is saved by idling the serial clock when data is not being transmitted. A valid signal can be omitted, providing a space saving. At the destination, similar clock-forwarding and delay enables a single parallel clock edge to drive data to the boundary of its clock domain, e.g. from a deserializer to a FIFO. The data link exhibits zero-cycle entry and exit. Variations with half- or single-cycle entry or exit are disclosed.

A multiple CPU pseudo 3D structure is provided that allows single clock cycle interrupt latency, requires no context storage while taking only a single cycle away from normal programs. Multiple interrupts are given flexible vectored parallel computing responses without timing interactions.

The present application relates to the technical field of multi-core heterogeneous computing, and discloses a storage coherent hub chip based on core integration, a storage coherent arbitration device and an adaptive control method, aiming to solve the technical problems of high cross-core memory access latency, low coupling degree of cache coherence maintenance and memory scheduling, and slow response of operation strategy adjustment under the existing multi-core architecture. The present application takes an independently packaged storage coherent core as a globally consistent unique maintenance node, integrates a single-cycle static addressing architecture, adopts a cache coherence state machine and a memory scheduling controller with deep fusion of logic layers, realizes automatic switching between robust mode and aggressive mode through a pure hardware MHM monitoring unit, and the atomic withdrawal process is transparent to the upper layer. The present application can reduce the cross-core memory access latency by more than 40%, improve the storage access throughput by 25%, while guaranteeing 99.999% operation reliability, adapting to various heterogeneous interconnection protocols, and being applicable to various application scenarios such as servers, high-frequency financial transactions, AR / VR wearable devices, edge computing, etc.

The invention relates to the technical field of integrated circuit design, in particular to a processing circuit architecture supporting multi-calculation precision dynamic switching, which comprises a control port module, a partial product generation module, a symbol compression module, an addition compression tree module and a final adder module. And single-cycle dynamic switching of various precisions is realized. The partial product generation module adopts a Booth coding algorithm to split an operation vector, and cooperates with boundary symbol selection logic to solve the problem of symbol expansion and auxiliary bit overlapping; the symbol compression module compresses the redundant extension bits through a preset coding mode; the addition compression tree module is formed by cascading multiple stages of compressors and inserting carry blocking logic; the final adder module is composed of a plurality of carry lookahead adders, and the output bit width is dynamically controlled through blocking logic. The architecture optimizes the parallel operation efficiency and the resource utilization rate, adapts to the deep learning training and reasoning full scene, and has the advantages of real-time performance and low power consumption.

Disclosed are a micro-controller chip containing a multi-protocol communication interface peripheral and an operation method thereof. The micro-controller chip comprises a multi-protocol communication interface peripheral, the multi-protocol communication interface peripheral is connected to a system bus, the multi-protocol communication interface peripheral is connected with an I / O port, the multi-protocol communication interface peripheral comprises an exclusively used RISC instruction set micro-kernel, a code memory and a code program stored on the code memory and executable by the RISC instruction set micro-kernel, the code program at least comprises two bit operation instructions of 1 setting and 0 clearing, the instructions are single-cycle instructions, and when the RISC instruction set micro-kernel executes the code program, the I / O port outputs 1 or 0.

The application discloses a multi-stage branch predictor supporting branch target buffer compression and a prediction method. The predictor comprises a three-stage structure. The first-stage branch predictor is a single-cycle predictor, which is used for giving a prediction result in one cycle. The second-stage branch predictor is a double-cycle predictor, which is used for giving a prediction result in the second cycle. The third-stage branch predictor is a triple-cycle predictor, which is used for giving a prediction result in the third cycle. A per-cycle PC multiplexer simultaneously sends the selected PC into the three-stage branch predictor, and the three-stage branch predictor respectively gives corresponding prediction results. The low delay of the low-stage predictor guarantees the continuous flow of instructions in the pipeline. The high accuracy of the high-stage predictor reduces the pipeline refresh times caused by branch prediction failure. The combination of the short prediction cycle of the low-stage branch predictor and the high prediction accuracy of the high-stage branch predictor optimizes and compresses the branch target buffer structure of the branch predictor, and reduces the area of the branch target buffer.

The invention discloses a multi-stage branch predictor supporting branch target cache compression and a prediction method, the predictor comprises a three-stage structure, the first-stage branch predictor is a single-period predictor and is used for giving a prediction result in a period, the second-stage branch predictor is a double-period predictor and is used for giving a prediction result in a second period, and the second-stage branch predictor is used for giving a prediction result in a third period. And the third-stage branch predictor is a three-period predictor and gives a prediction result in a third period. In each period, the PC multiplexer sends the selected PC to the three-stage branch predictor at the same time, the three-stage branch predictor gives corresponding prediction results, the low delay of the low-stage predictor is utilized to ensure that the instruction is not interrupted in the assembly line, and the high accuracy of the high-stage predictor is utilized to reduce the number of times of assembly line refreshing caused by branch prediction failure. The short prediction period of the low-level branch predictor and the high prediction precision of the high-level branch predictor are combined, the branch target cache structure of the branch predictor is optimized and compressed, and the area of the branch target cache is reduced.

The invention provides a scheduling control method, a scheduling control device, electronic equipment and a storage medium, and relates to the technical field of intelligent warehouse management, and the method comprises the steps: generating a plurality of groups of operation basic sequences in a full arrangement form based on Monte Carlo random sampling; aiming at each group of operation basic sequences, generating an initial operation sequence of each crane corresponding to the group of operation basic sequences, and replacing tail end tasks of each initial operation sequence; performing discrete event simulation on each operation sequence after replacement by taking a rigid demand period of a power generation side as a step length, and performing screening by taking single-period consumption meeting the power generation side in the whole process as a constraint condition to obtain a candidate operation sequence meeting the constraint condition; and selecting a sequence meeting a preset optimization index from the candidate operation sequences as a final scheduling sequence, and controlling each crane to operate based on the final scheduling sequence. According to the method and the device, the final scheduling sequence is generated to coordinate the operation of the multiple cranes, so that the congestion is avoided, and the working efficiency is improved.

The present invention discloses a single-cycle control method for a PFC circuit and related devices. The PFC circuit includes a PFC main loop, a voltage loop controller, and a control loop. The method, executed by the control loop, includes: obtaining a first regulated voltage value output by the voltage loop controller, and output voltage sampled values, output current sampled values, input voltage value, and input current value of the PFC main loop; determining a feedforward control variable based on the output voltage sampled values, output current sampled values, and input voltage value; summing the first regulated voltage value and the feedforward control variable to obtain a second regulated voltage value; determining a duty cycle based on the input voltage value, input current value, output voltage sampled value, and second regulated voltage value; and generating a pulse width modulation signal based on the duty cycle, the pulse width modulation signal being used to regulate and control the PFC main loop. The present invention enables rapid regulation and control of the PFC circuit, improves control effectiveness, and facilitates miniaturization of the PFC circuit.

The invention discloses a 32-bit processor based on an RISC-V instruction set architecture, and belongs to the field of computer system structures and microprocessor design. According to the technical scheme adopted by the invention, the 32-bit processor based on the RISC-V instruction set architecture comprises an instruction set extension module, two new instructions of'aggresgate 'and'disaggresgate' are introduced, an R-type coding format is adopted, and the 32-bit processor is used for realizing grouping and splitting operation of data bits; the data path unit comprises a general register group, an arithmetic logic unit ALU and a special adder and is used for executing various data operations and processing; the control unit is used for generating a control signal according to an instruction decoding result and controlling operation of the data path unit and the memory; according to the method, by adding the special instruction and optimizing the data flow control mechanism, the complex bit operation is completed in a single period, the cache pressure is reduced, and the method has the advantages of improving the bit operation efficiency, reducing the instruction cache pressure and reducing the dynamic power consumption.

This invention proposes a multi-cycle modulation driving component, method, system, and product. The multi-cycle modulation driving component includes a state division component, a synchronous multi-cycle configuration component, and a single-cycle modulation component. The state division component performs functional decoding based on the device's functional mode and generates timing-matched trigger signals according to the specific functional mode. The synchronous multi-cycle configuration component generates various types of periodic / aperiodic enable signals at different clock frequencies based on configuration information, realizing multi-cycle timing drive. The single-cycle modulation component can serve as a general-purpose modulation unit; each unit can generate periodic composite on-chip timing drive signals based on configuration information and multi-cycle drive signals, thereby meeting the driving requirements of digital and analog readout units of different device chips. This invention can greatly simplify the overall timing structure of the driving chip.

The present invention relates to the field of communication technology, and in particular to a single-cycle multi-data packet verification and retransmission method, electronic device, and medium. The method can perform parallel verification of data packets to be transmitted, and the verification process of each data packet to be transmitted has no mutual constraints. The logical operation is simple, which greatly reduces the time overhead of the logical operation and reduces the delay of single-cycle multi-data packet verification and retransmission. In addition, compared with the traditional verification method, the data verification method of the present invention does not require additional storage space, and provides the possibility for high-frequency, high-bandwidth, low-power, and small-area data transmission operation circuits. Compared with the traditional operation method, the present invention has small structural changes and simple integration, can effectively improve the operation efficiency of the communication system, and reduce data transmission delay. The larger the data bandwidth and the more data packets are transmitted in a single clock cycle, the more obvious the performance improvement. The present invention reduces the power consumption and area of ​​the verification and retransmission circuit, and improves the performance of the communication system.

The application discloses a kind of RISCV system memory debugging method and system, its method includes: the interrupt request function of RISCV kernel is configured, enter debugging action and exit debugging action do not trigger the exception mechanism of RISCV processor;With host computer connection RISCV system, enter debugging state;The single-cycle valid signal triggered by host computer execution enter debugging action is converted into long-time valid signal;When long-time valid signal is valid, judge whether RISCV kernel has read-write, if yes, determine that the read-write signal of debugging module is invalid, set the state flag bit of interactive register, notify host computer system busy;If no, determine that the read-write signal of debugging module is valid, debugging module executes read-write to memory;Debugging module completes memory read-write and receives host computer exit debugging signal after exit debugging action, and make long-time valid signal invalid.The application utilizes the gap that RISCV kernel does not read nor write, realizes the read-write of debugging module to memory, realizes no interrupt memory debugging.

This invention belongs to the field of active magnetic levitation bearing technology, and discloses a single-cycle delay compensation method and device for a magnetic levitation bearing switching power amplifier. The method includes: establishing a unipolar single-cycle control mathematical model and calculating the duty cycle of a single cycle; setting a state switching criterion for the charging and discharging cycle and determining the charging and discharging state of a single cycle; establishing a linear duty cycle prediction model and deriving the duty cycle d linearly through calculation. t And calculate the duty cycle value d j The total duty cycle of the corresponding switching transistor within the cycle is obtained and output to the corresponding switching transistor. This invention enables the tracking of the target under static conditions without steady-state error, and under dynamic conditions, it can effectively reduce the time delay problem of traditional digital single-cycle control algorithms.

Systems and methods are disclosed for reduced-power serial data links. A clock-forwarded serial link carries a clock lane and one or more data lanes. Every active serial data cycle is accompanied by its own serial clock edge: a clock delay allows the same clock edge to drive data at a transmitter and latch data at a receiver. Power is saved by idling the serial clock when data is not being transmitted. A valid signal can be omitted, providing a space saving. At the destination, similar clock-forwarding and delay enables a single parallel clock edge to drive data to the boundary of its clock domain, e.g. from a deserializer to a FIFO. The data link exhibits zero-cycle entry and exit. Variations with half- or single-cycle entry or exit are disclosed.

The application provides a RISC-V-based hardware development system, comprising an instruction tracking module, a waveform slicing module, a deadlock detection module, an emulated storage tracking module, a function call tracking module, a peripheral access tracking module, an instruction emulator, a differential debugging comparison module, a comprehensive debugging module and a calling module; wherein the waveform period recorded by the waveform slicing module each time can be configured by itself, greatly reducing the space occupied by the generated waveform file; the differential debugging comparison module can adaptively process the execution period of each instruction of a processor, that is, the module can be used for a processor with single period or a processor using multi-stage pipeline technology. Through the use of the RISC-V-based hardware development system of the application for RISC-V processor design, the development and debugging efficiency of the processor can be greatly improved.

Apparatuses, systems, and methods for setting termination impedance based on encoding bits are disclosed. A memory receives an access command including one or more encoding bits, which may be received via one or more CA pins. Based on the one or more encoding bits and a setting in a mode register, the memory determines whether it is a target of the access command, and the memory applies a termination impedance based at least in part on the determination of whether it is the target of the access command. In various embodiments, the determination of whether the memory is the target can be performed in a single cycle.

The application discloses a memory-computing integrated device, a memory-computing method, a processing device, a tile module and an accelerator, and relates to the technical field of electronic circuits, and comprises: each memory-computing integrated array realizes parallel computation within the array, the memory-computing integrated array can simultaneously perform multiplication operation on single-bit input pulses at each moment in the current cycle buffer and corresponding weights, and synchronously generate membrane potential increment values at each moment; and the parallel accumulation of the increment values by a summation tree forms an efficient computing link of "parallel multiplication + parallel accumulation". Compared with the delay caused by the step-by-step waiting of the row-by-row serial processing of a computing task, the parallel architecture greatly shortens the processing time of the "multiplication-accumulation" whole process in a single cycle under the premise of ensuring high computing precision, further improves the computing efficiency under unit energy consumption due to the reduction of repeated data scheduling and state switching overhead in serial computation, and finally realizes the double optimization of computing delay reduction and energy efficiency ratio.

A signal quantization module comprising: a combining module configured to combine an input signal and a feedback signal to generate a combined signal; an integrator module coupled to the combining module and configured to generate an integrated signal using the combined signal; and a quantizer configured to generate an output signal based at least in part on the integrated signal, wherein the output signal is fed back to provide the feedback signal to the combining module and the integrator module, and wherein the quantizer is further configured to, when the quantizer is triggered at a first point in time, compare an input to the quantizer to a threshold hysteresis, and in response to the input to the quantizer reaching the threshold hysteresis, adjust the threshold hysteresis by an amount that characterizes a difference between a target hysteresis and the input to the quantizer at the first point in time.

The invention discloses a dynamic load balancing mapping method and system based on interrupt transaction combination. The method comprises the following steps: an interrupt synchronization processing step; an interruption mark setting step; a load state acquisition step; a dynamic combination control step; a channel mapping step; a target source processing step; and a closed loop feedback step. The invention also comprises a system for implementing the method. According to the method, the transformation of an interrupt scheduling normal form is realized through'dynamic load perception + hardware closed-loop architecture + elastic scheduling strategy ', firstly, post statistics is replaced by real-time quantitative load perception, and the problem that a scheduling decision and a real-time demand are disjointed is solved; secondly, due to full-hardware implementation, software intervention overhead is eliminated, and scheduling delay is reduced to a single-cycle level; and finally, an elastic combination mechanism and a priority collaboration strategy ensure the deterministic response of the key interruption.

A bounded-carry partial-sum adder for FP8 accumulation in a pipelined mixed-precision processing element is disclosed. The adder limits carry propagation to a predetermined depth, ensuring deterministic fixed delay independent of operand magnitude. The accumulator forms the second stage of a two-stage fused multiply-add pipeline and supports a one-cycle initiation interval while accumulating products of FP4 weight operands and FP8 activation operands. The architecture enables uniform high-frequency timing across dense arrays of processing elements.

An encoder includes: a feedforward module configured to receive to-be-encoded data with a parallelism of n symbols per cycle, and perform calculation in a finite field based on a symbol of the to-be-encoded data in a current cycle, to obtain a single-cycle polynomial corresponding to the current cycle; and a feedback module configured to receive the single-cycle polynomial corresponding to the current cycle output by the feedforward module, and perform calculation in the finite field based on the single-cycle polynomial corresponding to the current cycle and a first polynomial indicating a symbol received in a historical cycle, to obtain a second polynomial, where the second polynomial is used to determine a target polynomial indicating the to-be-encoded data, and the target polynomial is to generate a check sequence of the to-be-encoded data, to obtain a codeword obtained by encoding the to-be-encoded data based on a forward error correction (FEC) encoding scheme.

The present disclosure relates to performing multi-point table lookups in a single cycle in a system on a chip. In various examples, a VPU and associated components can be optimized to improve VPU performance and throughput. For example, the VPU can include a min / max collector, an auto store prediction function, a SIMD data path organization that allows inter-channel sharing, a transpose load / store with a stride parameter function, a load with permute and zero insertion function, a hardware, logic, and memory layout function to allow two-point and two-point by one lookups, and a per-memory bank load cache function. Further, a decoupled accelerator can be used to offload VPU processing tasks to improve throughput and performance, and a hardware sequencer can be included in a DMA system to reduce programming complexity of the VPU and DMA system. The DMA and VPU can perform a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

The invention relates to an AI reasoning acceleration system based on RISC-V extension, which realizes integrated acceleration of operations such as matrix multiplication, activation and quantization by adding a U8 matrix multiplication acceleration component and an LUT (lookup table) component on the basis of RVV and expanding related instructions of an AI special instruction set. The AI special instruction set expands a VMMA instruction and a VLMMP instruction, comprises a coding format, a register interaction rule and a hardware scheduling strategy of the instructions, cooperates with the RVV to realize higher matrix multiplication efficiency, and can complete nonlinear transformation of U8 data in a single cycle when realizing parallel table lookup operation of quantization and activation functions through the LUT lookup table component, so that the efficiency of matrix multiplication is improved. The effect of quantitatively activating zero delay is achieved, the AI reasoning process is remarkably accelerated, and finally the overall effect of high-performance AI reasoning task acceleration is achieved.

A delay-isomorphic and mirror-symmetric physical layout for pipelined low-precision floating-point processing elements is described. Transistors and interconnects are arranged as mirrored halves about a central axis, with routing geometries matched to equalize propagation delay across corresponding functional paths. The layout supports one-result-per-cycle throughput in pipelined fused multiply-add units operating on formats including FP4 weights and FP8 activations. Power, ground, clock, and operand nets are routed symmetrically to maintain uniform timing and electrical characteristics. Arrays of such processing elements may use alternating mirrored orientation to reduce cumulative skew. The approach achieves deterministic multi-gigahertz operation suitable for large-scale inference architectures.

A semiconductor device includes a delay locked loop (DLL) configured to output a first correction value corresponding to a single cycle of a clock and a duty correction circuit including a divider configured to divide the clock in half to generate a divided clock, delay the divided clock by a delay value corresponding to a half cycle of the clock to generate a delayed clock, and generate an adjusted clock having a duty ratio of 5:5 based on the divided clock and the delayed clock. The delay value is adjusted or changed based on the first correction value.

To provide a VPU and associated components that are optimized to improve VPU performance and throughput.SOLUTION: A VPU includes a min / max collector, an automatic store predication function, a SIMD data path configuration allowing inter-lane sharing, a transposed load / store including a stride parameter function, a load including a permute and zero insertion function, a hardware, logic device, and memory layout function allowing two point and two by two point lookups, and per memory bank load caching ability. Decoupled accelerators are used to offload VPU processing tasks, and a hardware sequencer is included in a DMA system. The DMA and VPU execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for executing dynamic region-based data movement operations.SELECTED DRAWING: Figure 9A

The application discloses a fixed-length native ternary instruction set architecture, and belongs to the technical field of processor instruction set architecture and AI acceleration calculation. The application adopts a 32-bit fixed-length ternary instruction format, and instructions are fixedly divided into a 6-bit operation code domain, two groups of 5-bit register address domains and a 16-bit ternary immediate number domain from high bits to low bits; each ternary bit is jointly carried by NZ / NG double-line symbol mark coding composed of two CMOS two-state signal lines. The instruction set includes five types of native instructions of data transfer, arithmetic parallel, control branch, system privilege and accelerator cooperation, is equipped with single-cycle parallel decoding hardware logic, and synchronously completes instruction segmentation analysis and hardware unit scheduling. The architecture realizes 243-way super-large general register addressing, natively supports ternary symbol immediate number coding, internally builds a matrix multiplication and addition special acceleration instruction and a register context batch switching instruction, and reserves an operation code expansion space. The application can be widely applied to the fields of ternary AI reasoning chips, high-energy-efficiency embedded processors and autonomous controllable computing hardware.

Techniques for per allocation cycle micro-operation fusion are described. In an embodiment, an apparatus includes micro-operation (uop) fusion circuitry and an arithmetic-logic unit (ALU). The uop fusion circuitry is to analyze a line of uops to find a producer uop and a consumer uop meeting fusibility criteria and to morph the consumer uop into a fused uop, wherein the line of uops includes a number of uops corresponding to maximum number of uops that can be allocated in a single cycle. The ALU is to execute the fused uop.