89results about How to "Detecting error" patented technology

A novel and useful range extension and in-band noise mitigation mechanism that uses conventional CRC error detection codes to correct single and multiple bit errors in packets received over a communications link. The CRC error correction mechanism of the invention is particularly suitable for use with communication protocols with weak error correction capabilities. The mechanism uses the linearity property of the CRC calculation to detect the existence of errors in the received packet. The entire received packet is searched for single bit errors and are corrected in a single cycle. If no single bit errors are found, the mechanism then searches for multiple bit errors. Packet retransmissions are used to detect and mark the location of multiple bit errors. Multiple bit errors are corrected by trying a plurality of hypotheses of single bit error corrections. Each hypotheses pattern is investigated to find matching CRC patterns for correction using the single bit, single cycle CRC error correction method.

A device for detecting errors with an integrated self-check, on an integrated circuit comprising a serial link control function for constituting an input-output port (109) between a parallel bus (L2CB, C2LB) and a serial link. The integrated circuit comprises a serializer circuit (109T) on output and a deserializer circuit (109R) on input. An insertion buffer I-sb has each of its outputs connected to one input of an exclusive OR operation with two inputs. The second input of the exclusive OR operation receives a piece of information (o-s) to be transmitted in order to constitute, with the insertion information issuing from the insertion buffer, a piece of substitute information. An additional buffer (I-tb) makes it possible to compare the sequence supplied as output from the exclusive OR with a sequence stored in the additional buffer (I-tb) in order to validate the transmission of the substitute sequence. A history buffer (HIB) stores characters received from the deserializer and makes it possible to diagnose the error.

The present invention relates to a method, a computer program product and a system for performing functional formal verification. Error detection logic is verified by injecting errors in a hardware design description without any changes to the original design description. With the present invention both permanent and transient faults can be modelled, and the complete error space can be covered for all types of fault models that can be used at the RTL. The number of detected design errors is used to determine the overall coverage in relation to the number of injected errors. The error injection is prepared by adding additional circuits to an RTL netlist representation of the hardware logic design. Signal values for selected signals related to the error detection logic are compared for a modified netlist representation and for the original netlist using a formal verification tool.

A data transceiver including a self-test data generator for generating test data, which includes a first pseudo-random number generator programmable so as to allow the operator to input the test data values. The data transceiver further includes a transmitter section coupled to the self-test data generator, a receiver section coupled to the transmitter section, and a test data analyzer coupled to the receiver section, wherein the test data analyzer includes a second pseudo-random number generator, which allows the operator to input the data value via a data bus coupled to the test data analyzer. Both the self-test data generator and the test data analyzer are independently controllable.

Positions holding different bit values between a first code word, which is obtained by coding an information bit sequence based on a coding method utilizing quasi-cyclic codes, and a second code word, which has the close Hamming distance from the first code word and satisfies a parity check of the coding method, are identified. Thereafter, a code word is generated by inserting bit values known to the transmitter and receiver into the identified positions of the information bit sequence and coding the information bit sequence. Upon reception of a signal based on the generated code word, the receiver judges whether known bit values held by corresponding positions in a code word obtained by decoding the received signal are the same as preset bit values. If the judgment result is negative, the code word based on the received signal is judges as erroneous even when it satisfies the parity check.

Systems, methods, and computer program products that can be used concurrently or alternatively to detect errors in data as well as to protect access to data are provided. Embodiments enable a coherent data set (CDS) which is a data set guaranteed to be genuine and error-free at run-time. Embodiments provide systems, methods, and computer program programs to create a CDS, identify a CDS, and verify the coherency of a data set purported to be a CDS. Embodiments further enable privileged functions which are functions that can only be accessed by a restricted set of other privileged functions. Embodiments provide systems, methods, and computer program products to create, identify, and protect access to privileged functions.

A method of detecting a position of a rotation axis of a suction nozzle of an electric-component mounting apparatus, the suction nozzle holding, by suction, an electric component, and being rotated about the rotation axis thereof to rotate the electric component held thereby, so that the electric component rotated is mounted on a component-mounting surface of a circuit substrate, the method including the step of detecting, on a position-detecting plane including the component-mounting surface of the circuit substrate, the position of the rotation axis of the suction nozzle.

A swath printer includes a print head that is moveable along a scan direction for applying an ink image to a receiving medium. A transport mechanism is configured to move the receiving medium and the print head with respect to each other in a transport direction that is substantially orthogonal to the scan direction. A first sensor is arranged to detect a position of a first reference pattern present on the receiving medium in a first area thereof, and a second sensor is arranged to detect a position of a second reference pattern present on the receiving medium in a second area thereof. A controller is provided to control the printer on the basis of the detected positions of the reference patterns during use of the printer.

A belt type fixing device of the present invention includes a fix roller, a press roller rotatable in pressing contact with the fix roller, a heat roller accommodating a heat source therein and a belt passed over the fix roller and heat roller. A non-contact type temperature sensor is positioned in a sheet passing range corresponding to the width of a minimum sheet size and assigned to the heat roller while a contact type temperature sensor is positioned outside of the sheet passing range. A controller prevents the heat source from being turned on if temperature sensed by the non-contact type temperature sensor is short of preselected temperature B when temperature sensed by the contact type temperature sensor reaches preselected temperature A assigned to the non-contact type temperature sensor. A reflection type sheet sensor determines whether or not a sheet is present on the belt.

An interference-resistant wireless audio system includes a transceiver for transforming an audio signal into an RF signal, and a receiver for receiving RF signals in the air. The transceiver has an audio signal receiver, an audio data format converter, a frame and coding unit, a modulation module, an RF transceiver, a receiving/transmitting switch controller, an RF signal detector, and a channel switch controller electrically connected to the RF signal detector for controlling the RF transceiver to switch the used channel to another one after receiving a switch signal generated by the RF signal detector

A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

In a searchable cipher system, the security of ciphertext, the optimization of the size of ciphertext and the optimization of the network traffic are not examined enough. A registration client deposits encrypted data acquired by compressing the size of a search tag created for a search by a stochastic encryption using a mask by a hash value and an output value of a homomorphic function in a server, a search client similarly stochastically encrypts a search keyword and transmits it to the management server as a search keyword acquired by encrypting only a part of the encrypted data, the search client requests the management server to search data to be searched without making the management server release a mask by random numbers of the encrypted data and the encrypted keyword, the search client detects a wrong search in a search result, and decrypts the search result.

The invention relates to a network, in particular a PA PROFIBUS network having redundant properties and a linear topology. Two line ends are connected to a redundancy manager which disconnects said line ends in error-free conditions and connects them in error conditions. Said redundancy manager supplies voltage to the first line end for operating customers' mobile telephones each of which is connected to the network by a branching unit. After receiving a supply voltage on one connection thereof, said branching units check the state of a cable which is connected to the other network connection and transmit the supply voltage in the faultless condition thereof only. When the redundancy manager does not detect the supply voltage on the other end of the line end at least during a predetermined space of time after voltage supply, said redundancy manager supplies the voltage thereto. A cable having a disturbance is then disconnected from the line by the adjacent branching units.

A phase locked loop circuit and a phase locked loop control method in an optical disc reproducing system having a high ISI condition is capable of detecting a phase error and a frequency error of an input signal based on a pattern, such as a sync pattern, having a predetermined uniform distribution over an entire range. The phase locked loop circuit includes a sampler which samples an input signal according to a sampling clock output from the phase locked loop circuit; a pattern detection signal/phase error generation unit which generates a pattern detection signal indicating the detection of a predetermined pattern, detects a phase error between the sampled input signal and a zero crossing point of the input signal if the sampled input signal output from the sampler has the predetermined pattern, and outputs the detected phase error, and a sampling clock generation unit which generates the sampling clock based on the pattern detection signal and the phase error, wherein the predetermined pattern is a pattern which is uniformly distributed over the entire range where the input signal can be inputted.

A sample processing apparatus comprises an aspirating member which comprises a pump at one side and which is configured to aspirate a sample from the other side, a sensor which is configured to sense the presence or absence of a liquid at a predetermined position of the aspirating member, and a controller which is programmed to execute operations. The operations comprise controlling the aspirating member to aspirate a sample, obtaining a first sensing result by the sensor when the aspirating member aspirates a sample, controlling the aspirating member to aspirate air after aspirating a sample, obtaining a second sensing result by the sensor when the aspirating member aspirates air, and detecting an error in the aspirating operation, based on the first sensing result and the second sensing result.

Provided is an optical system for a thermal image microscope. The optical system includes an image forming unit and a relay unit. The image forming unit forms a focus. The relay unit elongates an optical path. Here, the image forming unit includes six lenses. The relay unit includes two lenses. Aspherical surfaces of the lenses are all convex surfaces.

A method and an apparatus for checking a pipelined parallel cyclic redundancy is disclosed. In accordance with the method and the apparatus of the present invention, after an entire CRC (cyclic redundancy check) logic is divided into a feedback portion and an input data portion, the input data portion is divided using a pipelined structure such that the input data portion is designed to have the pipelined structure based on an algorithm that maintains a logic level of each stage to be lower than that of the feedback portion and an algorithm that optimizes a size of a register inserted during the division to improve a speed thereof and to detect an error of a received data in a high speed data communication apparatus.