4277 results about "Zero crossing" patented technology

The present invention relates to a method and device for improving concealment of frame erasure caused by frames of an encoded sound signal erased during transmission from an encoder (106) to a decoder (110), and for accelerating recovery of the decoder after non erased frames of the encoded sound signal have been received. For that purpose, concealment/recovery parameters are determined in the encoder or decoder. When determined in the encoder (106), the concealment/recovery parameters are transmitted to the decoder (110). In the decoder, erasure frame concealment and decoder recovery is conducted in response to the concealment/recovery parameters. The concealment/recovery parameters may be selected from the group consisting of: a signal classification parameter, an energy information parameter and a phase information parameter. The determination of the concealment/recovery parameters comprises classifying the successive frames of the encoded sound signal as unvoiced, unvoiced transition, voiced transition, voiced, or onset, and this classification is determined on the basis of at least a part of the following parameters: a normalized correlation parameter, a spectral tilt parameter, a signal-to-noise ratio parameter, a pitch stability parameter, a relative frame energy parameter, and a zero crossing parameter.

In a method and apparatus for controlling power factor correction in mixed operation modes, a frequency of the input voltage is obtained by detecting the zero crossing points of the input voltage. A peak of the input voltage is obtained by detecting input voltage with 90 degree phase. Thus, the present invention predicts the input voltage by its frequency and peak and the characteristic of the sine wave. A digital signal processor computes the duty and frequency of a boost switch, switching the operation mode of the boost converter among continuous mode, critical mode and discontinuous mode according to input voltage or the load. According to another aspect, the operation is switched to critical mode from the average current mode when a zero current is detected before the charging and recharging cycle of the boost switch is finished.

A system and method for determining the relative phase of each of a plurality of load meters connected to a three-phase power distribution system. The system includes a gateway that communicates information to and from each of the individual load meters. The gateway generates a timing pulse that is received by each of the load meters. Based upon the delay from the receipt of the timing pulse to the next zero crossing of the single phase power supply received by the meter, the utility can determine the phase of the individual meter. The system can include a feeder meter connected to each phase of the electrical supply system to determine the energy consumption for each of the meters connected to a specific phase. The utility can compare the energy consumption information from the feeder meter to all of the load meters connected to the same phase to determine whether any energy theft is occurring.

Control methods for resonant converters offer improved performance in resonant converters that operate with a wide input-voltage range or a wide output-voltage range (or both) by substantially reducing the switching-frequency range. Reduction in the switching frequency range is achieved by controlling the output voltage with a combination of variable-frequency control and time-delay control. Variable-frequency control may be used to control the primary switches of an isolated resonant converter, while delay-time control may be used to control secondary-side rectifier switches provided in place of diode rectifiers. The secondary-side control may be implemented by sensing the secondary current or the primary current (or both) and by delaying the turning-off of the corresponding secondary switch with respect to the zero crossings in the secondary current or the primary current.

A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.

A combined power supply and driver control module includes rectifier circuitry, switching circuitry, and driver circuitry for providing output power to a load. Rectified output from an input power source is used to produce a DC power. The switching circuitry receives the DC power and modulates the input current drawn from the power source. An intelligent control module includes control circuitry, such as a digital processor, for controlling the switching circuitry. Power factor is improved by modulating the input current to be closer in phase with the voltage of the power source. Also disclosed is a power factor correction circuit in which a digital processor reads waveform values from a lookup table and modulates the input current waveform based on the values. A zero crossing detector connected to the input power source may direct the digital processor when to commence reading values from the lookup table.

An integrated circuit tester produces an output TEST signal following a pulse of a reference CLOCK signal with a delay that is a sum of an inherent drive delay and an adjustable drive delay. The tester also samples an input RESPONSE signal following a pulse of the reference CLOCK signal with a delay that is a sum of an inherent compare delay and an adjustable compare delay. The inherent drive and compare signal path delays within an integrated circuit tester are measured by first connecting a salphasic plane to transmission lines that normally convey signals between the tester and terminals of an integrated circuit device under test. A standing wave signal appearing on that salphasic plane is phase locked to the CLOCK signal so that a zero crossing of the standing wave occurs at a fixed interval after each pulse of the CLOCK signal. Each transmission line concurrently conveys the standing wave to the tester to provide timing references for measuring the inherent drive and compare signal path delays within the tester. Transmission line signal paths are also measured. Delays are added to the drive and compare signal paths to compensate for the measured inherent drive, compare and transmission line delays.

A circuit for powering high-efficiency lighting devices from a thyristor-controlled dimmer predicts a zero-crossing time of the AC power line supplying the dimmer and causes a glue impedance to be imposed at the output of the dimmer starting at the time of the zero-crossing, so that the timer in the dimmer will operate properly to generate the turn-on event at the correct time. At turn-on, a lower level of impedance is presented to absorb the energy associated with the turn-on event. A higher level of impedance may be presented after the energy is absorbed until all of the energy needed for the cycle is transferred. Then, a high impedance state is maintained until the next zero-crossing time. The impedance control may be provided by non-uniform operation of a power converter that supplies the lighting devices, or by a combination of non-uniform power converter operation and dissipative loading.

A sinusoidal R.F. carrier is modulated for the transmission of digital binary datastreams through the deletion of carrier wavelets. These wavelets are defined between zero crossover positions representing zero energy locations. One or more wavelets are switched out of the carrier at the zero crossing positions to avoid sideband generation occasioned by electromagnetic energy disturbance. Transmissional amplification as well as receptional amplification is carried out with non-resonating amplifier architecture.

The present invention relates to an audio signal controller adapted to receiving first and second digital audio signals and estimating a signal feature of the first or second digital audio signal. The estimated signal feature is compared with a predetermined feature criterion and the audio signal controller switches from conveying the first digital audio signal to conveying the second digital audio signal to a controller output, or vice versa, at a zero-crossing of the first digital audio signal or the second digital audio signal based on the comparison between the estimated signal feature and the predetermined feature criterion.

A power-conversion control system includes an inverter, a cycloconverter, and a sliding mode controller. The inverter is operable to receive a DC voltage input and produce a first AC voltage output having a first frequency. The cycloconverter has a plurality of bidirectional switches, and is operable to receive the first AC voltage and to synthesize a second AC voltage having a second frequency that is lower than the first frequency. The sliding mode controller is operable to provide a control signal to command the plurality of bidirectional switches to turn OFF and ON when the first AC voltage is at a zero crossing condition. The sliding mode controller is also operable to selectively adjust the frequency and amplitude of the second AC voltage.

A circuit for providing power factor correction in accordance with an embodiment of the present application may include a boost converter circuit and a control circuit receiving as inputs a rectified AC input voltage from a rectifier, a signal proportional to current through the boost inductor and the DC bus voltage across the capacitor of the boost converter. The control circuit provides a pulse width modulated signal to control the on time of a PFC switch. The control circuit further includes a voltage regulator and a current regulator. The current regulator includes a difference device operable to subtract a signal proportional to the inductor current from the current reference signal, a PI controller adapted to receive the output of the difference device and provide a first control signal, a feed forward device operable to receive the rectified AC input voltage and to provide a second control signal with a smaller dynamic range than the AC input voltage, and an adder operable to add the first control signal to the second control signal to provide a PWM reference signal for generating the pulse width modulated signal. A zero crossing detector and vector rotator may be provided to provide a clean sinusoidal reference to the current regulator. A partial PFC regulator may be provide to provide partial mode PFC if desired.

A method and system for intrinsic timescale decomposition, filtering, and automated analysis of signals of arbitrary origin or timescale including receiving an input signal, determining a baseline segment and a monotonic residual segment with strictly negative minimum and strictly positive maximum between two successive extrema of the input signal, and producing a baseline output signal and a residual output signal. The method and system also includes determining at least one instantaneous frequency estimate from a proper rotation signal, determining a zero-crossing and a local extremum of the proper rotation signal, and applying interpolation thereto to determine an instantaneous frequency estimate thereof. The method and system further includes determining at least one instantaneous frequency estimate from a proper rotation signal, extracting an amplitude-normalized half wave therefrom and applying an arc sine function to the amplitude-normalized half wave to determine an instantaneous frequency estimate of the proper rotation signal.

A method for pulse width modulated pulse synchronization in a parallel UPS system uses the locally measured critical bus voltage to detect a zero crossing and adjust the PWM pulse to coincide with the zero crossing. No communication between the units is required to perform synchronization, and no “master” and “slave” relationship exists to thereby increase the total system reliability.

A data alignment algorithm that automatically aligns data from multiple monitoring devices to the same zero-crossings at the same point in time. Cycle-by-cycle frequency data is received from each monitoring device and a cross-correlation algorithm is performed to determine a correlation coefficient between a reference monitoring device and another monitoring device. The data of the other monitoring device is shifted by one cycle and another correlation coefficient is calculated by the cross-correlation algorithm. The data of the two monitoring devices is aligned at the point at which the maximum correlation coefficient is calculated or the point at which the correlation coefficient exceeds a threshold value. The clocks of the monitoring devices can also be synchronized at the same point of alignment.

A PWM control section (1) gently changes phase currents (Iu, Iv, and Iw) under a current driving control over a pre-drive circuit (2) and an output circuit (3). The pre-drive circuit (2) suspends energizing of the specific motor coil (Mu, Mv, and Mw) according to a PWM disable signal (NPWM) at PWM disable periods. A self-commutation circuit (5) performs zero crossing detection according to a BEMF detection signal (DZC) during BEMF detection periods. A count section (7) selects either a self-commutation signal (SC) or a forced commutation signal (FC) as a commutation signal (CS), whichever enters earlier, and, based on its intervals, generates the PWM disable signal (NPWM) and the BEMF detection signal (DZC). The BEMF detection period starts after the start of the PWM disable period, and finishes together with the PWM disable period at the switching of the energization phases.

The configurations of a resonant converter system and a controlling method thereof are provided. The proposed resonant converter system includes a resonant converter receiving an input voltage for outputting an output voltage, a rectifying device having a first rectifying switch and a synchronous rectification control circuit coupled to the resonant converter and including a signal generation apparatus generating a weighted turn-off signal to turn off the first rectifying switch at a zero crossing point of a first current flowing through the first rectifying switch.

The invention provides a method for injecting a harmonic voltage to restrain a harmonic current of a PMSM (permanent magnet synchronous motor), which is characterized in that a ring to restrain the harmonic current is added to realize the closed-loop control for the harmonic current on the basis of extracting harmonic current components in the PMSM in real time, thus calculating to obtain harmonic voltage components which are required to be injected to restrain 5-order and 7-order harmonic currents of the PMSM; and then the obtained harmonic voltage components are injected into a three-phase control voltage in a speed control system of the PMSM so as to offset the 5-order and 7-order harmonic components in a motor current when the PMSM runs, thereby reaching the purpose of restraining the 5-order and 7-order harmonic currents. The method is used to solve the technical difficulty that current ZCP (zero crossing point) is required to detect accurately in a traditional mode to restrain the harmonic current, remarkably improves the current waveform of the motor, effectively restrains the 5-order and 7-order harmonic currents caused by the nonlinear characteristics of an inverter and the air-gap field distortion of the motor, effectively reduces the additional loss caused by the 5-order and 7-order harmonic current components, reduces the electromagnetic torque and the revolving speed pulse of the PMSM and improves the running efficiency and the running reliability of the PMSM.