902 results about "Phase detector" patented technology

System and method for controlling one or more light emitting diodes. For example, the system includes: a voltage detector configured to receive a rectified voltage associated with a TRIAC dimmer and generated by a rectifying bridge and generate a first sensing signal representing the rectified voltage; a distortion detector configured to receive the first sensing signal, determine whether the rectified voltage is distorted or not based at least in part on the first sensing signal, and generate a distortion detection signal indicating whether the rectified voltage is distorted or not; and a phase detector configured to receive the first sensing signal and generate a phase detection signal indicating a detected phase range within which the TRIAC dimmer is in a conduction state based at least in part on the first sensing signal.

The invention discloses an ultra-low phase noise microwave signal generation method and system based on an electro-optical comb. The method comprises the following steps: 1) locking two lasers with continuously tunable wavelengths in the same FP cavity through two links with different modulation frequencies to realize a dual-wavelength laser with a frequency interval of (v2-v1); 2) reducing the electronic noise of each link to a quantum noise limit by using a residual amplitude modulation noise control technology; 3) coupling the lasers with the center frequencies of v1 and v2 into one path, inputting the laser into an electro-optical frequency comb generator, and generating two sets of electro-optical frequency combs with spectrum overlapping; (4) beat frequency signals of the two electro-optical frequency combs are obtained; the beat frequency signal and a reference signal from a reference signal source are accessed to a phase discriminator for phase discrimination; an output signal of the phase discriminator is sent to a proportional-integral-differential control circuit; and 5) controlling the phase noise of the radio frequency source by using the output feedback of the proportional-integral-differential control circuit to obtain an ultra-low phase noise microwave signal.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The invention relates to a phase-locked loop circuit, a clock generator, a chip and electronic equipment, and the phase-locked loop circuit mainly comprises a phase frequency detector which is used for generating a phase detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; the proportional path module is used for generating a first control current according to the phase discrimination output signal; the integral path module is used for generating a second control current according to the phase discrimination output signal; the current control oscillation module is used for generating a clock output signal according to the first control current and the second control current; and the feedback frequency divider is used for obtaining a feedback clock signal through frequency division of the clock output signal. According to the phase-locked loop, the advantages of the analog charge pump phase-locked loop and the full-digital phase-locked loop are combined, the generation of a high-performance clock which is small in area, high in bandwidth, stable in loop and low in quantization noise is facilitated, the applicability of the phase-locked loop to the high bandwidth requirement is facilitated, the quantization noise is reduced, and the performance of the phase-locked loop is improved. And unconditional stability of the phase-locked loop is realized theoretically.

A self-adaptive high-dynamic spread spectrum tracking receiver relates to the technical field of satellite communication and comprises an AGC loop, an A / D converter, a PN code capturing and tracking loop, a single carrier loop, a despreading device, a phase discriminator, a phase shift signal generator and a low-pass processor. The method comprises the following steps of: converting a signal into a digital signal, subsequently generating an output tracking signal through a PN code capturing and tracking loop, processing through a single carrier loop to obtain a captured tracking signal and an amplitude excitation signal, and finally carrying out de-spreading and phase discrimination to generate an azimuth error voltage signal and a pitching error voltage signal; the receiver can stably receive and process spread spectrum signals sent by a high-speed target.

The invention belongs to the field of electronic devices, particularly relates to an anti-SET reinforced phase frequency detector, and aims to solve the problems that the existing SET injection can change the output logic state of a PFD (phase frequency detector), and a post-stage circuit obtains a wrong phase difference indication signal. According to the invention, an output UP signal and an output DOWN signal of a first-stage unit are used as the input of an input control logic, and the input control logic outputs four indication signals; the input of the first output control logic is four indication signals, and the output of the first output control logic is a first conduction control signal; the second-stage unit is used for carrying out rising edge sampling on the UP signal and the DOWN signal respectively and outputting two indication signals; the input of the phase selector is a reference clock signal, a feedback clock signal and two indication signals, the output of the phase selector is the input of the second output control logic, and the second output control logic outputs a second conduction control signal. According to the invention, the output logic state is not changed during SET injection, and a correct phase difference indication signal is obtained at a rear stage.

The invention discloses a frequency measurement circuit and a frequency measurement method, belongs to the technical field of frequency measurement, and mainly solves the problems that the existing frequency measurement is large in frequency error, low in frequency measurement speed and narrow in frequency measurement bandwidth, and cannot meet the requirements of radar communication. The frequency measurement circuit comprises an FPGA control module, a reference clock circuit connected with the FPGA control module, a DDS frequency output circuit, a phase discrimination frequency control circuit, a frequency mixer connected with the phase discrimination frequency control circuit, and a radio frequency input circuit connected with the frequency mixer. According to the frequency measurement technology, the DDS output frequency is directly collected according to the characteristic that the FPGA collects the low frequency, the DDS output frequency serves as the phase discriminator phase discrimination frequency, frequency measurement is conducted in a phase locking mode, and the frequency measurement precision is high; the phase discriminator is set to have a fixed frequency dividing ratio, the phase discriminator is configured with a fixed register, a DDS frequency sweeping mode is adopted, and the frequency measurement time is short by changing the phase discrimination frequency of the phase discriminator to the output frequency of the phase-locked loop; and the frequency measurement bandwidth is increased by using a radio frequency input frequency division mode.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

A solution for generating a clock using a quadrature delay can include a first plurality of in-phase (I) inverter pairs configured to output an I signal according to a first input and an inverted in-phase (inverted I) signal according to a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution can include a second plurality of quadrature (Q) inverter pairs configured to output a Q signal according to a third clock signal input and an inverted Q signal (inverted Q) according to a fourth clock signal input and a phase detector including a plurality of cells, each of which can receive at least one of the I signal, the inverted I signal, the Q signal or the inverted Q signal and include at least one or more transistors having a gate connected to a ground.

The invention provides a reference-clock-free clock data recovery device and a clock data recovery method thereof, and relates to the technical field of electronics. The reference-clock-free clock data recovery device comprises a linear phase discriminator used for carrying out phase discrimination processing on received four-level pulse amplitude modulation data and outputting a phase discrimination signal voltage; the frequency discriminator is used for carrying out frequency discrimination processing on the received phase discrimination voltage signal and outputting a frequency discrimination signal voltage; the first voltage-current converter is used for outputting pulse signal current; the loop filter is used for converting the pulse signal current into control voltage; the inductance-capacitance oscillator is used for converting the control voltage into an orthogonal clock signal; the self-biased multiphase clock generator is used for outputting a multiphase clock signal according to the orthogonal clock signal; and the starting circuit is used for discharging the control voltage to zero during power-on starting, so that the orthogonal clock signal is at the initial frequency, and traversal search of the control voltage is realized.

The embodiment of the invention discloses a numerical control oscillator calibration system. The system comprises a signal detection assembly, a phase discriminator, a numerically-controlled oscillator gain module, a digital filter and a numerically-controlled oscillator, the numerically-controlled oscillator is connected with the signal detection assembly, the signal detection assembly is connected with the phase discriminator, the phase discriminator is connected with the numerically-controlled oscillator gain module, the numerically-controlled oscillator gain module is connected with the digital filter, and the digital filter is connected with the numerically-controlled oscillator. The digital filter is connected with the numerically-controlled oscillator. According to the embodiment of the invention, the initial control word is not directly adjusted, and the tuning control word is additionally generated for adjustment, so that the adjustment process is not influenced by the size of the initial control word, adjustment can be carried out with a smaller code value, and the calibration precision is improved.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention belongs to the technical field of optical communication, and particularly relates to a high-stability photo-generated millimeter wave system based on a phase-locked loop, which comprises a first laser, a second laser, an acousto-optic frequency shifter, a dense wavelength division multiplexer, an inner loop feedback control loop and an outer loop signal output branch, the inner loop feedback control loop comprises a phase modulator, an optical filter, a photoelectric detector, a frequency division arithmetic unit, a phase frequency detector, a loop filter, a voltage-controlled oscillator and a first power amplifier which are sequentially connected in series, and the output of the first power amplifier is connected with an acousto-optic frequency shifter; the inner loop feedback control loop further comprises a cesium atomic clock, a microwave source and a second power amplifier; wherein the cesium atomic clock is connected with the microwave source and the phase frequency detector, and the output of the microwave source is connected with the phase modulator after passing through the second power amplifier.

The present invention discloses a clock data recovery circuit and recovery method suitable for high-speed SerDes, including: an analog front end, inputting a received signal and outputting a phase detector result; a phase detector accumulator, used to accumulate the phase detector result; a gain control unit, used to adjust the gain of the trunk signal; a first branch, including a ratio decision device and a phase gain unit; a second branch, including a weight decision device and a frequency integration unit; an adder, used to add the output results of the phase gain unit and the frequency integration unit, and the adder output passes through a phase accumulator and a phase interpolator in turn; the phase interpolator is used to output a sampling clock for use by the analog front end. The present invention can respond in time under small error conditions, with fast CDR locking speed and short time; reduce the cumulative error of the system, strengthen the tracking effect of clock jitter, and ensure the overall performance improvement of the system.

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

The invention discloses a monitoring system for improving the anti-interference capability of converter transformer partial discharge ultrasonic monitoring. According to the system, a first coupler divides continuous narrow-band light emitted by a laser into a sensing light signal and a reference light signal; the sensing optical signal is reflected by the Faraday rotating mirror, then returns along an original optical path, and enters the second coupler through the circulator; a reference light signal generates a fixed frequency shift through an acousto-optic modulator and then enters a second coupler to interfere with the sensing light, two beams of interference light are converted by a balanced photoelectric detector for differential detection, and a measurement signal is output; the radio frequency driving signal is divided into a first driving signal and a second driving signal by the power divider, the first driving signal is used for driving the acousto-optic modulator, and the second driving signal enters the RF gain phase detector as an electrical synchronization reference signal; and the RF gain phase detector performs difference processing on the phase quantity of the measurement signal and the phase quantity of the electrical synchronous reference signal to obtain a partial discharge ultrasonic signal of the converter transformer, and outputs the partial discharge ultrasonic signal to the acquisition card system.

Apparatus and methods for clock synchronization and frequency translation are provided herein. Clock synchronization and frequency translation integrated circuits (ICs) generate one or more output clock signals having a controlled timing relationship with respect to one or more reference signals. The teachings herein provide a number of improvements to clock synchronization and frequency translation ICs, including, but not limited to, reduction of system clock error, reduced variation in clock propagation delay, lower latency monitoring of reference signals, precision timing distribution and recovery, extrapolation of timing events for enhanced phase-locked loop (PLL) update rate, fast PLL locking, improved reference signal phase shift detection, enhanced phase offset detection between reference signals, and / or alignment to phase information lost in decimation.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

The invention relates to a low-jitter charge pump phase-locked loop circuit. According to the circuit, a digital integral path and an analog proportion path are connected behind a phase frequency detector module, and both the digital integral path and the analog proportion path are connected with a combined voltage-controlled oscillator module; the combined voltage-controlled oscillator module is connected to the frequency divider to output a feedback clock signal and input the feedback clock signal to the phase frequency detector again; the combined voltage-controlled oscillator module comprises two voltage-controlled oscillators, one of the voltage-controlled oscillators works when the rate of frequency increasing along with voltage exceeds a linear proportion area, and the other voltage-controlled oscillator works when the rate of frequency increasing along with voltage is lower than the linear proportion area; and the output frequencies of the two voltage-controlled oscillators are processed, nonlinear characteristics are mutually suppressed, and a linear voltage-frequency characteristic is obtained. The linear output can suppress the output jitter problem, thereby further reducing the output jitter problem of the phase-locked loop.

The invention relates to a calculation method and device for an intermediate frequency domain amplitude phase angle in a memristor array, and the method comprises the steps: obtaining a time domain input signal corresponding to a target memristor array, and calculating a cosine frequency mixing signal and a sine frequency mixing signal based on the time domain input signal, a preset cosine signal and a preset sine signal; respectively applying the cosine frequency mixing signal and the sine frequency mixing signal to corresponding row lines of the target memristor array so as to calculate cosine current data and sine current data based on discrete Fourier transform matrixes of the corresponding row lines; and obtaining current information of each frequency point in the target memristor array based on the cosine current data and the sine current data, and reading phase information and amplitude information corresponding to each frequency point in the current information through a preset phase discriminator and a peak detector. Therefore, the problems that in the prior art, the amplitude and the phase cannot be directly calculated under the condition that extra hardware overhead and operation delay are not increased, and the frequency domain amplitude phase angle calculation efficiency is greatly affected are solved.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

A phase-locked loop circuit comprises a clock signal loss detection module, a time-to-digital converter, a digital-to-time converter, a phase discriminator, a charge pump, a loop filter, a comparator, a voltage-controlled oscillator, a frequency divider, a reference voltage generation module and a switch; a capacitor array of the voltage-controlled oscillator is adjusted by using an output of the comparator, so that a control voltage Vctrl of the voltage-controlled oscillator is constantly equal to a reference voltage after a phase-locked loop is locked and does not change along with a change of a PVT condition; after a reference clock signal is lost, the circuit directly adopts the reference voltage as the control voltage of the voltage-controlled oscillator, and after the reference clock signal is re-accessed, an output delay of the digital-to-time converter is adjusted, clock edge alignment of a new reference clock signal and a feedback clock signal is realized.

The invention relates to the technical field of space optical communication and distance measurement, in particular to a distance measurement method and device based on a non-equal sampling digital phase discriminator and a storage medium. A non-equal sampling method is used for carrying out sampling and phase discrimination on data bit clocks on two asynchronous clock domains for sending and receiving GTX, and hardware resources required for processing all use an FPGA internal digital logic block; the clock processing rate and the GTX sending and receiving clock rate are kept in a non-integer multiple relationship, so that the measurement precision of the phase difference between the two clock rates is improved, and the purpose of improving the laser ranging precision on the basis of simplifying the hardware design of a ranging system is achieved.

The invention discloses a phase-locked loop quantization noise calibration method and system, electronic equipment and a storage medium. The method comprises the following steps: a phase frequency detector performs correlation processing on a feedback signal output by a modulator and a reference signal output by a phase discriminator to generate a gain coefficient; multiplying the gain coefficient by a feedback signal output by the modulator to output a first gain signal; subtracting the first gain signal from a reference signal output by the phase discriminator to output a second gain signal; the second gain signal is filtered by the digital loop filter to obtain a filtered signal and the filtered signal is output to the digital time converter; and the digital time converter processes the filtering signal to obtain a pulse signal suitable for being processed by the phase discriminator and outputs the pulse signal to the phase discriminator. The LMS algorithm is adopted, and on the basis of the complementary digital time converter calibration technology, quantization noise is eliminated through a low-energy-consumption circuit.

A phase locked loop (PLL) includes a phase detector configured to receive a reference signal and a feedback signal, wherein the reference signal has a reference frequency, sample the feedback signal, and output a phase detection signal indicative of a phase of the feedback signal. A voltage controlled oscillator is configured to generate an output signal based on the phase detection signal. The output signal has an output frequency greater than the reference frequency. Feedback circuitry is configured to detect a signal edge of the output signal and selectively supply, once per cycle of the reference signal, the detected signal edge of the output signal as the feedback signal.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

The invention relates to the technical field of single-phase phase-locked loops, and discloses an improved single-phase phase-locked loop based on a generalized second-order integral and a wave trap, which comprises a phase discriminator, the wave trap, a loop filter and a voltage-controlled oscillator which are electrically connected in series in sequence, the input end of the phase discriminator is connected with a power grid voltage sampling signal, and the phase discriminator processes the power grid voltage sampling signal to obtain an error voltage signal; the phase discriminator inputs the error voltage signal into a wave trap for processing to obtain a voltage signal; the wave trap inputs the voltage signal into a loop filter for processing to obtain a control voltage signal; the loop filter inputs the control voltage signal into the voltage-controlled oscillator to obtain a phase-locked loop output signal; and the voltage-controlled oscillator inputs the phase-locked loop output signal into the phase discriminator. The improved phase-locked loop provided by the invention can effectively solve the problem of large phase locking error under low sampling frequency, improves the performance and stability of the system, and avoids the problems of large error and insufficient precision of the existing phase-locked loop.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

According to the low-orbit satellite signal broadband tracking method based on the square difference phase discriminator, a frequency discriminator and the square difference phase discriminator are designed according to a signal modulation mode of a star network low-orbit satellite, accurate frequency discrimination and phase discrimination can be carried out on star network low-orbit satellite signals, and the low-orbit satellite signal broadband tracking method based on the square difference phase discriminator is obtained. The high accuracy can be kept even in a complex and rapidly changing signal environment; in addition, the method adopts a second-order frequency locking auxiliary third-order phase locking design, so that high-dynamic frequency offset change caused by high-speed movement of a low-orbit satellite of the star network can be processed more effectively, and the stability and the accuracy of signal tracking are ensured. According to the invention, the tracking capability of the satellite network low-orbit satellite signal is obviously improved, stable frequency and phase locking can be realized under a high dynamic condition, reliable receiving and processing of the signal are ensured, a solid guarantee is provided for efficient operation of a satellite network low-orbit satellite system, and an important foundation is laid for development of a future space-ground integrated network.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.