3973 results about "Phase detector" patented technology

A double gate semiconductor device (2006) is used beneficially as a multiplier (2000). The double gate semiconductor device (2006) has a lateral fin (105) as the channel region with the gates formed opposite each other on both sides of the fin. The lateral positioning of the fin provides symmetry between the two gates. To increase drive current, multiple transistors are easily connected in parallel by having a continuous fin structure (2106) with alternating source/drain terminals (2120, 2122, 2124, 2126) in which the sources are connected together and the drains are connected together. Gates (2116, 2110) are positioned between each pair of adjacent source/drain terminals and electrically connected together. The multiplier (2000) may also be used as a mixer and further as a phase detector.

A near field RF communicator (100) has an inductive coupler (102) and a first signal provider (109, 110, 111) to cause the inductive coupler to provide a first signal that when inductively coupled to the inductive coupler of another near field RF communicator in near field range is insufficient to cause initiation of communication with that other near field RF communicator. A sensor (116) senses a change in an impedance of the inductive coupler (102) due to inductive coupling of the first signal between the inductive couplers of the said near field RF communicator and a said other near field RF communicator in near field range. A controller (107) determines whether or not another near field RF communicator is in near field range on the basis of any change in impedance sensed by the sensor and, if another near field RF communicator is determined to be in near field range, causes a second signal to be inductively coupled to the other near field RF communicator to initiate communication between the two near field RF communicators. The sensor may use a phase detector (118) to enable a change in impedance to be sensed by detecting a change in a current-voltage phase relationship resulting from a change in impedance.

High dynamic range brightness information is acquired by inputting detection current to a high (adjustable) gain resettable integrator whose output V(t) is compared to a Vth threshold by a comparator whose output is counted by a reset counter as V(t).gtoreq.Vth. When a desired count is attained, data acquisition ends, the counter is read, and the entire circuit is reset. A TOF data acquisition circuit includes first and second sequences of series-coupled delay units, and a like number of latch units coupled between respective delay units. A phase discriminator compares output from each chain and feedback a signal to one of the chains and to a comparator and can equalize delay through each chain. A control voltage is coupled to the remaining chain to affect through-propagation delay time. The latch units can capture the precise time when V(t).gtoreq.Vth. Successive measurement approximation can enhance TOF resolution.

A device (10, 50, 60, 70, 80, 90) is used to apply an electric pulse or spike to a patient to treat the patient. The device can have a series of preset treatments programmed therein. A user can select a treatment from menus displayed on a display (100). The impedance of the skin and underlying tissue to be treated can be measured prior to the treatment to locate active areas on the skin for treatment. The impedance measurement can be made at a sufficiently low level to avoid treatment of the patient that could cause a change in the impedance. A phase detector can be used to isolate the capacitance value in the impedance. The charge delivered to the patient can be measured and the device can adjust the charge as the skin impedance varies during treatment to deliver uniform charges to the skin. A variety of probes can be used with the device, with the device automatically detecting the type of probe attached. Multiple electrodes can be used on the probe, which allows the active areas in contact with the probe to be identified prior to treatment to allow the treatment to concentrate on the active areas.

Aspects of the disclosure relate generally to a circuit for sustaining an radio frequency (RF) modulated optical signal. The circuit may comprise a self injection locking component having a fiber optic delay line over which a portion of the optical signal propagates. The circuit may also comprise a self phase locked loop component having at least two fiber optic cables having different lengths and over which another portion of the optical signal propagates and a phase detector coupled to the at least two fiber optic cables and configured to determine a phase difference between the signals propagating over one of the respective fiber optic cables. The circuit may further comprise a voltage controlled oscillator configured to generate a stable oscillating signal in response to signals generated by each of the self injection locking and self phase locked loop components, the stable oscillating signal being configured to sustain the optical signal.

A novel interpolating phase detector for use in a multiphase PLL is described comprising an array of individual phase comparators, all operating at essentially the same operating point which permits the circuits to be designed simultaneously for high speed and for low power consumption. Two adjacent phase outputs of a multi-phase VCO may be selected and interpolated in between, by selectively attaching a variable number of phase comparators to each phase output and summing their phase error outputs. By varying the number of phase comparators attached to each phase output, interpolation can be achieved with high linearity.

A warning system (20) includes a central control unit (CCU), and a plurality of local units (LU) connected to the central control unit (CCU). Each local unit (LU) includes a plurality of input trips (An), such as smoke detector, an earthquake detector, and gas detector, and a plurality of programmable responses, such as a bypass relay (C), a message delivered by a record/playback unit (D), an emergency light (E), and a strobe light (F). The input trips (An) also include a disconnect trip (A1), which is activated by a detector input signal (DI) sent from the central control unit (CCU), and indicates that the central control unit (CCU) has malfunctioned. The programmable responses include a warning output signal (WO) which is sent from the local unit (LU) to the central control unit (CCU) to indicate the presence of a local emergency at the local unit (LU).

A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

A phase locked loop, PLL, is described with multiple parallel charge pumps that are selectively disabled as phase lock is approached. A lock detection circuit is described that enabled reference currents to be fed to the parallel charge pumps. The error signal from a phase detector is arranged as UP and a DOWN signals that are averaged in the lock detector. When the average error is large, all the reference currents feed the charge pumps that provide a high loop gain to reduce the lock time. As the lock becomes closer selective reference currents are disabled to reduce loop gain so that a smooth transition to lock is made. Selectively switching currents into a low pass filter that usually follows a charge pump in a PLL circuit automatically reduces switching noise by the operation of the low pass filter.

Methods and apparatus are provided for generating one or more clock signals for a decision-feedback equalizer using DFE detected data. A received signal is sampled using a data clock and a transition clock to generate a data sample signal and a transition sample signal, respectively. A DFE correction is obtained for each of the data sample and transition sample signals to generate DFE detected data and a DFE transition data. The DFE detected data and DFE transition data are then applied to a phase detector that generates a signal to adjust a phase of one or more of the data clock and transition clock. In a multi-level implementation, the received signal is sampled using a clock associated with each of the levels and the samples are latched using a vertical slicing technique to generate DFE data associated with each of said levels.

A self-aligned clock recovery circuit for synchronizing a local clock with an input data signal includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector obtains samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and obtains a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples. Logic circuitry determines whether the local clock appears to be early or late based on a comparison of the logic levels of the symbol samples and the associated data crossover sample, and provides a corresponding output signal through a filter to the local clock to adjust the clock accordingly. Since the relative sampling instants of successive data crossover samples are varied with time, the phase detector output signal amplitude is substantially proportional to the amount of phase error between the local clock and the symbol timing, thereby improving jitter properties of the clock recovery circuit.

this invention relates to power in direct-current circuits. The invention takes gallium arsenide as foundation (1). On the foundation has power divider, power synthesizer, 90deg phaser, solid beam structure. Power divider and power synthesizer composed by port one (7), port two(8), port three(8), dissymmetry coplane band line(10), nitride tantalum electric resistance. Solid beam structure includes signal input port(16), pier(5), solid beam(13), pedestal structure(6), sensing electrode(4), sensing electrode leader(12), capacitance detecting port(15), air bridge(14). There are nitriding silicon medium layer on the transmission line, pedestal structure and sensing electrode under solid beam, and sensing electrode leader under Air Bridge.

A motion detection device is provided. The motion detection device includes a first antenna, a voltage-controlled oscillator, a phase detector and a signal processing unit. The first antenna receives a first signal generated by a second signal reflected by a target object, so as to output the first signal to the phase detector or the voltage-controlled oscillator. The voltage-controlled oscillator receives first signal or the second signal and receives a frequency adjustment signal, so as to generate an oscillating signal according to the frequency adjustment signal and the one of the first signal and the second signal. The phase detector receives the oscillating signal and another one of the first signal and the second signal, and generates a first phase output signal and a second phase output signal. The signal processing unit estimates motion parameters of the target object according to the first and the second phase output signal.

An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.

Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

A reference timing signal apparatus with a phase-locked loop (PLL) has a computer algorithm which adaptively models the multiple frequencies of an oscillator following a training period. The oscillator is part of a PLL and the oscillation frequency thereof is controlled in response to the phase detector output. The computer algorithm processes the control signal applied to the oscillator. The computer algorithm updates the characteristics of the model relating to the aging and temperature of the oscillator, using for example, a Kalman filter as an adaptive filter, in accordance with a cumulative phase error in the PLL calculated during a given time interval. By the algorithm, the subsequent model predicts the future frequency state of the oscillator on which it was trained. The predicted frequency of the model functions as a reference to correct the frequency of the oscillator in the event that no input reference timing signal is available. Also, the calculated phase error is stored and is used while no input reference timing signal or accurate predicted frequency value is available. With the model updating algorithm, oscillators of low stability performance may be used as cellular base station reference oscillator, which is based on satellite systems, for example, GPS, GLONASS or Galileo systems.

A quadrature oscillator with phase error correction including a local oscillator that generates a single-ended clock signal, a single-ended to differential converter that converts the clock signal to a differential clock signal, a quadrature generator that converts the differential clock signal into I and Q carrier signals, a phase error detector that measures a phase error between the I and Q carrier signals, and a feedback amplifier that modifies the differential clock signal based on measured phase error. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal. A transconductor converts the differential clock voltage signal into two pairs of differential current clock signals, where the quadrature generator generates I and Q current signal outputs from the two pairs of differential current clock signals. The phase error detector generates a phase error voltage, and the feedback amplifier includes a transconductance stage that converts phase error voltage into a DC correction current and that adds the correction current to each of the two pairs of AC differential current clock signals.