1681 results about "Phase detector" patented technology

A near field RF communicator (100) has an inductive coupler (102) and a first signal provider (109, 110, 111) to cause the inductive coupler to provide a first signal that when inductively coupled to the inductive coupler of another near field RF communicator in near field range is insufficient to cause initiation of communication with that other near field RF communicator. A sensor (116) senses a change in an impedance of the inductive coupler (102) due to inductive coupling of the first signal between the inductive couplers of the said near field RF communicator and a said other near field RF communicator in near field range. A controller (107) determines whether or not another near field RF communicator is in near field range on the basis of any change in impedance sensed by the sensor and, if another near field RF communicator is determined to be in near field range, causes a second signal to be inductively coupled to the other near field RF communicator to initiate communication between the two near field RF communicators. The sensor may use a phase detector (118) to enable a change in impedance to be sensed by detecting a change in a current-voltage phase relationship resulting from a change in impedance.

A device (10, 50, 60, 70, 80, 90) is used to apply an electric pulse or spike to a patient to treat the patient. The device can have a series of preset treatments programmed therein. A user can select a treatment from menus displayed on a display (100). The impedance of the skin and underlying tissue to be treated can be measured prior to the treatment to locate active areas on the skin for treatment. The impedance measurement can be made at a sufficiently low level to avoid treatment of the patient that could cause a change in the impedance. A phase detector can be used to isolate the capacitance value in the impedance. The charge delivered to the patient can be measured and the device can adjust the charge as the skin impedance varies during treatment to deliver uniform charges to the skin. A variety of probes can be used with the device, with the device automatically detecting the type of probe attached. Multiple electrodes can be used on the probe, which allows the active areas in contact with the probe to be identified prior to treatment to allow the treatment to concentrate on the active areas.

Aspects of the disclosure relate generally to a circuit for sustaining an radio frequency (RF) modulated optical signal. The circuit may comprise a self injection locking component having a fiber optic delay line over which a portion of the optical signal propagates. The circuit may also comprise a self phase locked loop component having at least two fiber optic cables having different lengths and over which another portion of the optical signal propagates and a phase detector coupled to the at least two fiber optic cables and configured to determine a phase difference between the signals propagating over one of the respective fiber optic cables. The circuit may further comprise a voltage controlled oscillator configured to generate a stable oscillating signal in response to signals generated by each of the self injection locking and self phase locked loop components, the stable oscillating signal being configured to sustain the optical signal.

A warning system (20) includes a central control unit (CCU), and a plurality of local units (LU) connected to the central control unit (CCU). Each local unit (LU) includes a plurality of input trips (An), such as smoke detector, an earthquake detector, and gas detector, and a plurality of programmable responses, such as a bypass relay (C), a message delivered by a record/playback unit (D), an emergency light (E), and a strobe light (F). The input trips (An) also include a disconnect trip (A1), which is activated by a detector input signal (DI) sent from the central control unit (CCU), and indicates that the central control unit (CCU) has malfunctioned. The programmable responses include a warning output signal (WO) which is sent from the local unit (LU) to the central control unit (CCU) to indicate the presence of a local emergency at the local unit (LU).

A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

A self-aligned clock recovery circuit for synchronizing a local clock with an input data signal includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector obtains samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and obtains a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples. Logic circuitry determines whether the local clock appears to be early or late based on a comparison of the logic levels of the symbol samples and the associated data crossover sample, and provides a corresponding output signal through a filter to the local clock to adjust the clock accordingly. Since the relative sampling instants of successive data crossover samples are varied with time, the phase detector output signal amplitude is substantially proportional to the amount of phase error between the local clock and the symbol timing, thereby improving jitter properties of the clock recovery circuit.

this invention relates to power in direct-current circuits. The invention takes gallium arsenide as foundation (1). On the foundation has power divider, power synthesizer, 90deg phaser, solid beam structure. Power divider and power synthesizer composed by port one (7), port two(8), port three(8), dissymmetry coplane band line(10), nitride tantalum electric resistance. Solid beam structure includes signal input port(16), pier(5), solid beam(13), pedestal structure(6), sensing electrode(4), sensing electrode leader(12), capacitance detecting port(15), air bridge(14). There are nitriding silicon medium layer on the transmission line, pedestal structure and sensing electrode under solid beam, and sensing electrode leader under Air Bridge.

A motion detection device is provided. The motion detection device includes a first antenna, a voltage-controlled oscillator, a phase detector and a signal processing unit. The first antenna receives a first signal generated by a second signal reflected by a target object, so as to output the first signal to the phase detector or the voltage-controlled oscillator. The voltage-controlled oscillator receives first signal or the second signal and receives a frequency adjustment signal, so as to generate an oscillating signal according to the frequency adjustment signal and the one of the first signal and the second signal. The phase detector receives the oscillating signal and another one of the first signal and the second signal, and generates a first phase output signal and a second phase output signal. The signal processing unit estimates motion parameters of the target object according to the first and the second phase output signal.

An adaptive equalizer system for use in a serial communication link uses timing information generated by a phase detector of a clock and data recovery circuit of the serial communication link and a frequency pattern of the recovered data to determine whether the data received over the serial communication link is over-equalized or under-equalized. The equalizer strength of the adaptive equalizer system is adjusted based on such determination.

Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

A quadrature oscillator with phase error correction including a local oscillator that generates a single-ended clock signal, a single-ended to differential converter that converts the clock signal to a differential clock signal, a quadrature generator that converts the differential clock signal into I and Q carrier signals, a phase error detector that measures a phase error between the I and Q carrier signals, and a feedback amplifier that modifies the differential clock signal based on measured phase error. The feedback amplifier applies the measured phase error as a DC offset to an AC differential clock signal. A transconductor converts the differential clock voltage signal into two pairs of differential current clock signals, where the quadrature generator generates I and Q current signal outputs from the two pairs of differential current clock signals. The phase error detector generates a phase error voltage, and the feedback amplifier includes a transconductance stage that converts phase error voltage into a DC correction current and that adds the correction current to each of the two pairs of AC differential current clock signals.

A method and circuitry for a delay lock loop useful in synchronizing the accessing of a memory array with a system clock is disclosed. In a preferred embodiment, the delay lock loop includes a variable delay element. The delay of the variable delay element is initially set to a minimum delay value. The system clock is then frequency divided and sent to the variable delay element, the output of which will ultimately be used to access the memory array in a synchronized manner with the system clock. The frequency divided clock and the output of the variable delay element are input to a phase detector, which creates a control signal for adjusting the delay of the variable delay element. After the signals are determined to be locked by the phase detector, an undivided clock signal version of the clock signal is sent to the variable delay element, and a frequency divided version of the output of the variable delay element is sent to the phase detector in lieu of the previous output of the variable delay element.

A clock and data recovery circuit, for tracking frequency-modulated input data, comprises a phase detector for receiving a data signal and a synchronous clock signal, detecting a phase delay or a phase advance, and outputting an UP1/DOWN1 signal, first and second integrators for integrating the UP1/DOWN1 signal and outputting an UP2/DOWN2 signal and an UP3/DOWN3 signal, respectively, a pattern generator for receiving the UP3/DOWN3 signal from the second integrator to output an UP4/DOWN4 signal, a mixer for receiving the UP2/DOWN2 signal from the first integrator and the UP4/DOWN4 signal from the pattern generator and generating an UP5/DOWN5 signal for output, and a phase interpolator for interpolating the phase of an input clock signal based on the UP5/DOWN5 signal from the mixer, for output are provided. A clock signal output from the interpolator is fed back to the phase detector as the clock.

A timing recovery circuit and related method is disclosed. The timing recovery circuit encompasses a converter, an interpolator, a phase error detector, an adjustment circuit, and a calculation circuit. The converter samples an input signal to generate an intermediate signal carrying samples of the input signal, while the interpolator inserts an interpolating sample into the intermediate signal in response to a control value to generate an output signal. The phase error detector outputs a phase error of the output signal. The adjustment circuit updates an over-sampling ratio according to a pair of first and second thresholds, and a counting value adjusted in response to the phase error and a median reference value. Finally, the calculation circuit derives the control value from the updated over-sampling ratio, and transferring the control value to the interpolator.

A position detecting device which can increase accuracy in detecting the pole position of a motor used to perform quick acceleration and deceleration over the range from a zero speed to a high rotation speed, and a synchronous motor driving device using the position detecting device. A position detector detects basic-wave component signals in sensor signals and executes position calculation. A correcting unit calculates signal information representing at least one of a gain, an offset and a phase by a phase detector from the basic-wave component signals detected by an error calculator, and makes correction based on the calculated signal information such that a position detection error is zero.

A laser displacement measurement system including a radiation source for transmitting radiation to a target, an R.F. transmitter oscillator for modulating the amplitude of the radiation at a first frequency, a detector for sensing the radiation reflected from the target, an R.F. local oscillator for providing an R.F. signal at a second frequency, a first mixer circuit, responsive to the oscillators for providing a local I.F. signal which is the difference between the first and second frequencies, a second mixer circuit, responsive to the detector and the R.F. local oscillator, for providing a reflected I.F. signal which is the difference between the second frequency and the modulation frequency of the reflected radiation, and a phase detector, responsive to the local and reflected I.F. signals, for detecting a first phase difference between the signals representative of the distance of the target.

A timing circuit generates timing signals for a synchronous rectifier directly from the transformer power output winding. A phase detector detects the phase of the voltage on the output winding. A switched current source generates a digital timing signal responsive to the phase detector. The output from the current source is applied to the gate of the rectifier to control the on/off condition of the rectifier.

Phase-locked loop (PLL) circuitry in which a sampling phase detector samples the output signal in accordance with the reference signal and a frequency detector detects the output signal frequency in accordance with the reference signal.

A synchrocyclotron includes magnetic structures that define a resonant cavity, a source to provide particles to the resonant cavity, a voltage source to provide radio frequency (RF) voltage to the resonant cavity, a phase detector to detect a difference in phase between the RF voltage and a resonant frequency of the resonant cavity that changes over time, and a control circuit, responsive to the difference in phase, to control the voltage source so that a frequency of the RF voltage substantially matches the resonant frequency of the resonant cavity.

A pulse radar is provided with a filter for eliminating a transmission waveform interfered with an answering signal from a received waveform, and a harmonic detector or a phase delay detector for detecting arrival and end of the answering signal reflected on a target.

PCT No. PCT/AU95/00793 Sec. 371 Date Sep. 30, 1997 Sec. 102(e) Date Sep. 30, 1997 PCT Filed Nov. 28, 1995 PCT Pub. No. WO96/17435 PCT Pub. Date Jun. 6, 1996A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCP)(20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency ( omega 'r). Applications of the SFPLL include demodulation in CW modulation systems and timing recovery from NRZ data. Three advantages of the SFPLL are that the output frequency is equal or close to the reference frequency when no input signal is present, and the range of frequencies to which the SFPLL can lock is confined to a region around the reference frequency, and the phase and frequency instabilities of the VCO can be reduced.

A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.

A novel mechanism that is operative to observe and compare the differentiated phase of the reference and variable PLL loop signals using a frequency detector. The resultant phase differentiated error is then accumulated to yield the phase error. The operation of the loop with the frequency detector is mathematically equivalent to that of the phase detector. A frequency error accumulator is used to generate the integral of the frequency error. The frequency error accumulator also enables stopping the accumulation of the frequency upon detection of a sufficiently large perturbation, effectively freezing the operation of the loop as subsequent frequency error updates are not accumulated. Upon removal of the phase freeze event, accumulation of the frequency error and consequently normal loop operation resumes.

The invention discloses a micromechanical silicon-based clamped beam-based phase detector and a detection method. The phase detector comprises a silicon substrate (1), a source (2), a drain (3), a first clamped beam-anchoring area (61), a second clamped beam-anchoring area (62), a grid (5) and a clamped beam (7), wherein the source (2) and the drain (3) are grown on the surface of the silicon substrate (1) and used for outputting saturation current, the source (2) is arranged opposite from the drain (3), and the clamped beam (7) is arranged upon the grid (5) and is opposite to the grid (5). The detection method includes the following steps: when a direct-current offset is loaded on a first pull-down electrode (81) and a second pull-down electrode (82) and the clamped beam (7) is pulled down and is in contact with the grid (5), two microwave signals which have the same frequency and certain phase difference are simultaneously loaded on the grid (5); the saturation current of the drain (3) is processed, so that high-frequency signals are filtered, and therefore the current signal of phase difference information is obtained. The structure of the phase detector is simple, and measurement is easy.

Multiple-level phase amplitude (M-PAM) clock and data recovery circuitry uses information from multiple phase detectors to generate one or more data sampling clocks that are optimized for each of the data slicers. One possible 4-PAM implementation includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The phase detector outputs are combined (e.g., via weighted voting, weighted average, minimum error, and/or minimum variance) to determine an optimized phase estimate for the clock used to sample the data at all three data slicers. Another 4-PAM implementation similarly includes 3 data slicers, 3 edge slicers, 3 phase detectors, and a single VCO. The mid-amplitude edge slicer and phase detector are used in combination with the VCO to generate a central phase while a multiple-tap delay line provides N phase variants before and after the central phase. Information from the non-mid-amplitude edge slicers and phase detectors is used to choose a phase from among the phase variants that best suits the other data slicers. In yet another implementation, a single edge slicer, single phase detector, and single VCO is used to generate a key clock which is used by the edge slicer to track the symbol timing. A clock generator provides a single optimized clock (that is offset from the key clock) that is used by the data slicers. Bit error rates from the data slicers are used to adjust the offset until the data slicer clock is optimized with respect to all the slicers. Alternatively, multiple clocks are generated via offsets from the key clock, each being optimized to the data slicer group that it drives.

The present invention includes apparatus and methods to calibrate a phase detector and an analog-to-digital converter (ADC) offset and gain. In one such embodiment, an apparatus includes a phase detector to generate an error pulse and a reference pulse, a combiner to combine the pulses, and an ADC to receive the combined pulses, where the ADC has a full scale set by an average of the reference pulse. Still further, a calibration loop may be coupled between the output of the ADC and the phase detector to generate and provide a phase adjust signal to reduce or eliminate phase offsets. Other embodiments are described and claimed.

A digital DLL apparatus and a method for correcting a duty cycle are disclosed. The digital DLL apparatus for correcting a duty cycle, includes: a buffer for producing a clock input signal; a delay line unit for receiving/delaying the clock input signal and outputting the clock input signal; a blend circuit for bypassing the first clock signal or producing a blended clock signal; a delay model unit for compensating a time difference of an external clock and an internal clock and generating a compensate clock signal; a direct phase detector for generating a first comparison signal; and a phase detector for generating a second comparison signal. The disclosed apparatus can correct the duty error by using the blend circuit and generate an internal clock signal having 50% of duty cycle.

A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10⁻¹².

A reduced complexity Turbo multi-user detector (MUD) processing system in multiple access communications channels that decreases the likelihood of improper decoding of the final values of interest and decreases the computation complexity for each iteration, thereby allowing for a reduction in the number of iterations performed and lowers the overall complexity without negatively impacting performance. In one form the present invention comprises a multi-user detector coupled to two or more decoder sections, two ore more recoders, and a compare and adjust section in such a manner that data flows iteratively to correct for errors in a computationally efficient manner.

The invention relates to an intermediate frequency direct sequence spread spectrum receiver for satellite ranging, which consists of 37 parts of a front-end A/D, an FFT module, a local PN code generator, a correlator, an automatic threshold calculation module and the like. The connection relationship is as follows: the output of the front-end A/D and the output of a carrier tracking loop NCO are respectively connected to an in-phase branch multiplier and an orthogonal branch multiplier, the input of the front-end A/D and the input of the carrier tracking loop NCO enter into an in-phase branch FIR low-pass filter and an orthogonal branch FIR low-pass filter, consequently, on the one hand, the output is sent to an integral zero clearing device, then the output which is sent to the FFT module, a branch 1 local PN code memory ROM and a branch 2 local PN code memory ROM enters into a branch 1 complex multiplier and a branch 2 complex multiplier, the output is sent to a branch 1 root mean square module and a branch 2 root mean square module, the output is sent to the threshold calculation module and a capturing and judging module for carrying out code catching; and on the other hand, the output is sent to the correlator and the local PN code generator for carrying out code tracking. The output of the correlator is simultaneously sent into a frequency discriminator/phase discriminator of the carrier tracking loop and then enters into a loop filter of the carrier tracking loop, and the output of the loop filter of the carrier tracking loop enters into the carrier tracking loop NCO for carrying out carrier tracking.