263 results about "Phase detector" patented technology

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

Embodiments described herein are directed to a position sensor that includes a first receiver coil electrically coupled to a first multiplier to generate a first output, a second receiver coil electrically coupled to a second multiplier to generate a second output, a transmitter coil electrically coupled to an oscillator, the oscillator electrically coupled to a third multiplier to generate a third output, a phase-locked loop electrically coupled to the oscillator and the transmitter coil, a summing circuit configured to receive the first output and the second output and configured to generate a signal, a phase detector configured to receive the signal and the third output, the phase detector outputting a sense signal that is indicative of an angle of the motor position sensor, and a pair of op amps electrically coupled to the phase detector. The op amps configured to output an analog differential signal and a differential phase signal.

The invention relates to the technical field of servo system control, in particular to a noise measurement suppression method and device based on axial angle tracking angular position estimation. The method comprises the following steps: determining a first measurement angle after sine transformation and a second measurement angle after cosine transformation based on the first measurement angle and the second measurement angle; simplifying the first measurement angle after sine transformation and the second measurement angle after cosine transformation to obtain a simplified first measurement angle and a simplified second measurement angle; based on the simplified first measurement angle and the simplified second measurement angle, determining a representation relation between a phase discriminator tracking error of the servo system and a phase-locked loop output angle; determining an input of the servo system based on the representation relationship; determining an estimated angle value based on the input of the servo system and a preset closed-loop transfer function; and controlling the servo system based on the estimated angle value. Therefore, the control precision of the servo system can be improved.

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

A clock compensation circuit of a first integrated circuit includes a phase detector circuit. The phase detector circuit includes a first input operative to receive a first clock signal from a second integrated circuit and a second input operative to receive a second clock signal for a circuit of the first integrated circuit. The phase detector circuit is configured to output a first control signal indicating whether the first and second clock signals are synchronized, and a second control signal indicating whether a phase of clock signals is different. The clock compensation circuit also includes a control circuit, responsive to one or more of the first and second control signals, and configured to generate one or more delay control signals. The clock compensation circuit also includes a delay circuit configured to apply a delay to the second clock signal based on the one or more delay control signals.

This invention discloses a pilot-type carrier phase recovery circuit and a reverse antenna array system, belonging to the field of 5G millimeter-wave communication. The pilot-type carrier phase recovery circuit includes a digital phase detector, a quadrature mixer, a quadrature voltage-controlled oscillator, a low-pass filter, a high-pass filter, a polyphase filter, a loop filter, a first intermediate frequency amplifier, a second intermediate frequency amplifier, a first shaping circuit, and a second shaping circuit. Applied to a reverse antenna array system, this invention performs carrier phase recovery on the data signal and pilot signal output from the receiver, separating the data signal without spatial phase information and the spatial phase information used for reverse transmission. This invention enables high-order modulation full-duplex communication and real-time tracking of moving targets, featuring high integration, small area, high communication speed, and strong anti-interference capability.

The invention provides a PLL loop bandwidth adjusting circuit, a control method and a circuit board. The PLL loop bandwidth adjusting circuit comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage-controlled oscillator. The input end of the phase frequency detector is connected with a reference signal; the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter; the second output end of the phase frequency detector is connected with the second input end of the adjustable voltage-controlled oscillator through the phase-locked loop proportional path module; the phase-locked source has the beneficial effects of high flexibility and low power consumption, and is suitable for the technical field of phase-locked sources.

The application discloses a double feedback branch current compensation type charge pump circuit, which comprises a core circuit, a double feedback branch and a bias circuit connected in sequence, wherein the input node of the double feedback branch is connected with the core circuit for detecting the potential change of the output voltage, the first output node of the first feedback branch in the double feedback branch is connected with the gate of the bias circuit, the second output node of the second feedback branch is connected with the bias circuit, and the up and down charging and discharging currents are carried out phased current compensation through the bias circuit according to the degree of the output voltage deviating from the center potential. The application solves the mismatching problem of the up and down charging and discharging currents when the output voltage deviates from the center potential through the double feedback branch, can convert the phase error output by the frequency discriminator into the difference between the charging and discharging currents, charges and discharges the loop filter to generate the control voltage of the voltage controlled oscillator, thereby realizing the lower charging and discharging current mismatching in the wider control voltage range, the smaller ripple on the output voltage, and the optimization of the jitter performance of the output clock of the phase-locked loop.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.

An N-antenna array zero-balance phase measurement apparatus, where N is an integer greater than two, includes: N couplers, each of the couplers including an input for receiving a radio frequency (RF) signal from a corresponding receiving element, a non-phase shifted output, and a phase-shifted output; and N phase detectors, each of the phase detectors including first and second inputs, and an output for generating a phase difference signal indicative of a difference in phase between respective signals provided to the first and second inputs. Adjacent couplers of the N couplers are connected to corresponding adjacent phase detectors of the Nphase detectors in a cross-coupled configuration. The N-antenna array zero-balance phase measurement apparatus is configured to generate a zero-balance phase output signal as a function of first to N-th phase difference signals generated by the N phase detectors, respectively.

The invention provides a phase-locked loop rapid locking circuit structure and a control method thereof, the circuit structure comprises a voltage-controlled oscillator, a frequency divider, a phase discriminator and a rapid locking loop filter, and the rapid locking loop filter comprises a capacitive digital-to-analog conversion module. According to the invention, the capacitive digital-to-analog converter module is adopted, and the control voltage of the voltage-controlled oscillator can be rapidly and accurately set based on the charge sharing principle, so that rapid locking is realized; moreover, the structure multiplexes the capacitor in the loop filter, and does not need an extra area. The method has the advantages of high precision, low power consumption and low cost, and has extremely high application value and potential.

The invention relates to a device and method for evaluating the influence of a power supply noise group on phase noise of a phase-locked loop, and relates to the technical field of phase-locked loops, and the device comprises a sine phase discriminator which detects the phase difference between an external reference signal and a feedback signal of a voltage-controlled oscillator; the input end of the loop filter is connected with the output end of the sine phase discriminator; the input end of the voltage-controlled oscillator is connected with the output end of the loop filter; establishing a phase-locked loop simulation model composed of a sine phase discriminator, a loop filter and a voltage-controlled oscillator; selecting a linear voltage-stabilized power supply series, and calculating a phase noise matrix with power supply noise corresponding to each model; different types of linear voltage-stabilized power supplies are respectively used for supplying power, and actually measured phase noise data corresponding to each type are tested and recorded; power supply noise group distribution is fitted by adopting a power law function, and optimal linear voltage-stabilized power supply model selection under the phase-locked loop architecture is determined. The method has the beneficial effects that the accuracy of predicting the phase noise is improved, the optimal solution is realized, and the model most suitable for the phase-locked loop architecture in the LDO series is selected.

The invention discloses a high-precision digital double-mixing phase discriminator, and belongs to the technical field of time transfer. Comprising a sampling amplification module, the output end of the sampling amplification module is connected with a signal processing module, and the output end of the signal processing module is connected with a result output module; the sampling and amplifying module is used for receiving two paths of input clock signals fCLKA and fCLKB, and sampling and amplifying the fCLKA and fCLKB by cascading two paths of multi-stage D triggers, so that the phase difference of the two paths of input clock signals is reserved and amplified, and the probability of metastable state occurrence is reduced; the signal processing module is used for carrying out jitter optimization processing on the two paths of sampled and amplified signals and extracting stable signal edges; and the result output module is used for measuring the amplified phase difference according to the two paths of signals subjected to jitter optimization, and obtaining the original phase difference through scaling down. Digital amplification is adopted, analog devices are not needed, noise introduction and delay uncertainty are avoided, and therefore the linearity and reliability of measurement are improved.

The invention relates to a delay-locked loop with a compensation circuit. The delay phase-locked loop comprises a delay circuit for generating multiple paths of auxiliary delay clock signals; the compensation circuit compensates the fixed delay in the delay phase-locked loop circuit, adjusts the initial phase difference of the multiple paths of auxiliary delay clock signals, and outputs a delay clock; and the phase discriminator inputs the delay clock and outputs a phase comparison result. By introducing the compensating circuit, the influence of fixed delay in the delay phase-locked loop on the adjustment range of the signal phase difference is solved, and the adjustable range of the signal phase difference is increased, so that the working frequency range of the delay phase-locked loop is further increased.

A contactless power feeding facility includes a coupling unit electromagnetically coupling a target feeder line and an adjacent feeder line. A target power supply apparatus includes: a phase detector detecting the induced current phase which is the phase of an induced current flowing through the target feeder line by the electromagnetic induction via the coupling unit while an alternating current is supplied to the adjacent feeder line by an adjacent power supply apparatus; an alternating-current generator generating the alternating current to be supplied to the target feeder line; and a phase controller controlling the alternating-current generator such that the phase of the alternating current to be supplied to the target feeder approaches the induced current phase detected by the phase detector.

The utility model discloses a Ka wave band broadband transmit-receive front end comprising a local oscillator source module, an X frequency conversion module, a Ka wave band frequency conversion module and an antenna module, the local oscillator source module is respectively connected with the X frequency conversion module and the Ka wave band frequency conversion module, and the X frequency conversion module, the Ka wave band frequency conversion module and the antenna module are connected in sequence. The local oscillator source module comprises a crystal oscillator module, a phase frequency detector, a loop filter, a voltage-controlled oscillator, an N frequency divider and a frequency doubling processing module, the crystal oscillator module, the phase frequency detector, the loop filter, the voltage-controlled oscillator and the frequency doubling processing module are connected in sequence, and the N frequency divider is connected with the phase frequency detector and the voltage-controlled oscillator. The local oscillation source module can stably generate high-quality signals, the transmitting-receiving front end adopts a superheterodyne structure and uses two times of frequency conversion, the first time of frequency conversion is Ka-X wave band frequency conversion, the second time of frequency conversion is X wave band frequency conversion, and mirror image frequency interference is well inhibited by using the two times of frequency conversion.

The application relates to a method and device for calculating frequency domain amplitude and phase angle in a memristor array, wherein the method comprises the following steps: obtaining a time domain input signal corresponding to a target memristor array, and calculating a cosine mixing signal and a sine mixing signal based on the time domain input signal, a preset cosine signal and a sine signal; applying the cosine mixing signal and the sine mixing signal to corresponding row lines of the target memristor array respectively, so as to calculate cosine current data and sine current data based on a discrete Fourier transform matrix of the corresponding row lines; obtaining current information of each frequency point in the target memristor array based on the cosine current data and the sine current data, and reading phase information and amplitude information corresponding to each frequency point in the current information through a preset phase discriminator and a peak value detector respectively. Thus, the problems that the prior art cannot directly calculate the amplitude and the phase without increasing additional hardware overhead and operation delay, and the efficiency of frequency domain amplitude and phase angle calculation is greatly affected are solved.

This invention relates to the field of phase-locked loop (PLL) technology, specifically to a method for achieving low jitter over a wide locking range by optimizing the PLL structure. The method includes: outputting a first error signal through a phase detector, obtaining the characteristics of the first error signal, and constructing a first error signal function; obtaining a first adaptive loop bandwidth; constructing a multi-band voltage-controlled oscillator (VCO) matching mechanism, including VCOs in multiple frequency bands; during PLL locking, selecting a frequency band based on the input signal frequency and the center frequency band of the VCO to obtain a first matching frequency band; and calculating the root mean square (RMS) of the first error signal based on further analysis of the first error signal characteristics, and combining the initial feedback gain and the initial error signal RMS to obtain a first feedback gain adjustment value. This invention achieves low jitter over a wide locking range through adaptive loop bandwidth adjustment, a multi-band VCO matching mechanism, and adaptive feedback gain adjustment.

Embodiments described herein are directed to a position sensor that includes a first receiver coil electrically coupled to a first multiplier to generate a first output, a second receiver coil electrically coupled to a second multiplier to generate a second output, a transmitter coil electrically coupled to an oscillator, the oscillator electrically coupled to a third multiplier to generate a third output, a phase-locked loop electrically coupled to the oscillator and the transmitter coil, a summing circuit configured to receive the first output and the second output and configured to generate a signal, a phase detector configured to receive the signal and the third output, the phase detector outputting a sense signal that is indicative of an angle of the motor position sensor, and a pair of op amps electrically coupled to the phase detector. The op amps configured to output an analog differential signal and a differential phase signal.

The application discloses a frequency modulation rate variable laser linear frequency modulation device and a frequency modulation method thereof. The device comprises a wideband tunable laser, a micro-optical lens, a beam splitter, an adjustable optical delay unbalanced MZ interferometer, a balanced photodetector, a phase discriminator, a loop filter, an up / down switch control circuit and an integrator. The adjustable optical delay unbalanced MZ interferometer comprises two couplers and an adjustable optical fiber delay line unit. According to the relationship between the linear frequency modulation light frequency and time of the upper and lower arms of the interferometer, when the delay amount of the adjustable optical fiber delay line unit changes, the frequency modulation rate of the output laser can be changed. The application changes the time delay of the light by using the adjustable optical fiber delay line, so that the frequency modulation rate can be changed.

The invention discloses an ice layer thickness sensor based on a dual-frequency antenna and a measuring method, belongs to the technical field of radio frequency sensing, and aims to solve the problems of small measuring range, misjudgment in a transition area and poor environmental interference resistance of a single-frequency microwave phase detection method. The sensor comprises a metal shell, a radio frequency board, a core control board, a double-frequency microstrip patch antenna, a double-frequency signal generator, a power division circuit, an amplitude-phase detector and an algorithm processing module. The dual-frequency microstrip patch antenna adopts a transmitting-receiving integrated structure, a reference signal and an incident signal are separated through a power division circuit, a dual-path phase difference is extracted through an amplitude-phase detector, and an algorithm processing module is used for solving the thickness of an ice layer based on a bilinear interpolation algorithm in combination with a thickness-phase difference two-dimensional characteristic plane. Through dual-frequency signal physical cooperation and algorithm fusion, large-range, high-precision and high-robustness ice layer thickness non-contact detection is realized, and the method is suitable for real-time monitoring of scenes such as road ice layers and the like.

Aspects of the subject disclosure may include, for example, obtaining, from a sampling device of a receiver, samples of a signal that is received from a transmitter, and facilitating acquisition between the receiver and the transmitter by deriving, based on the samples, a phase error output for centering a sampling clock of the sampling device with respect to a transmitter clock, wherein the deriving involves estimating group delay using a detection algorithm that is based on a blind Godard LMS algorithm.

A phase detector is provided according to this disclosure. The phase detector of this disclosure comprises a first transistor leg and a second transistor leg. Each of the first and second transistor legs includes a pair of transistors connected to each other at a plurality of common nodes. The phase detector of this disclosure further comprises an input section connected to the first transistor leg. The input section is configured to receive a first input signal and a second input signal. The phase detector of this disclosure further comprises an output section connected to the second transistor leg. The output section is configured to provide an output signal. The output signal includes a component indicating the phase difference between the first input signal and the second input signal.

The application claims a MEMS frequency accurate tracking and locking method based on a resonant phase-locked loop (R-PLL). The application relates to the technical field of MEMS (micro-electro-mechanical system) resonator control and frequency tracking, and the method takes the output of a voltage-controlled oscillator as an interference signal, takes the physical response (such as weak electromagnetic leakage or acoustic radiation) of a disturbed MEMS device as a feedback signal, compares the phase difference between the feedback signal and a reference signal through a phase detector, adjusts the interference frequency, and forms a closed-loop locking system. The application adjusts the interference source frequency through a phase detector and a filter, can track the target resonant frequency drift caused by factors such as temperature change in real time, makes the MEMS resonator keep in a phase-locked state with the target resonant frequency, and ensures that the interference energy is always efficiently coupled.

The invention discloses a device and a method for adjusting PLL (Phase Locked Loop) loop bandwidth based on VCO (Voltage Controlled Oscillator) working voltage. The device comprises a phase frequency detector, a digital filter, a digital oscillator and a frequency divider, the phase frequency detector is used for comparing the input signal with the output signal to obtain an error signal; the digital filter is used for processing the error signal; the digital filter comprises a proportional path; the digital oscillator is used for generating an output signal based on the processed error signal; the digital oscillator comprises a switch variable capacitor array; the switch variable capacitor array is used for adjusting the working voltage of the digital oscillator based on the error signal; the proportion path is directly connected with the phase frequency detector and the switch variable capacitor array; the frequency divider is used for carrying out frequency division on the output signal and feeding back the output signal to the phase frequency detector; by modifying the gain coefficient of the proportional path in the phase-locked loop, the adjustment of the loop bandwidth is realized, and the adjustment flexibility is improved.

This invention discloses a radio frequency millimeter-wave phase-to-voltage converter, belonging to the field of radio frequency microwave integrated circuit technology. The converter includes: a first and second frequency divider chain for dividing two input signals to achieve phase compression; a first and second quadrature generator for providing a -90° linearized bias; a three-state coupling network connected between the two frequency divider chains to eliminate phase mode ambiguity introduced by the frequency dividers through reconfigurable coupled phase; and a symmetrical phase detector for converting the linearized phase difference into a voltage signal output. This invention compresses the ±180° phase difference to a small angle range using phase compression technology, combined with linearized bias to allow the phase detector to operate in the linear region, and utilizes the three-state coupling network to achieve unambiguous detection across the entire 360° phase range. Implemented using a 40nm CMOS process, it requires no external clock, has no inductor design, a core area of ​​only 0.016mm², power consumption of 22mW, a response speed of 120ns, and a linearity of 1.05% FSR.

The embodiment of the invention provides a dual-phase-discriminator phase-locked loop control method and a grid-connected inverter, and the method comprises the steps: obtaining the voltage of a power grid, and determining the sampling frequency of the voltage of the power grid; determining at least one sampling period according to the sampling frequency; determining phase sine values and phase cosine values of a plurality of sampling periods according to the power grid voltage; determining a first phase difference signal through a first phase discriminator; determining a matching frequency and an output phase value corresponding to the matching frequency according to the first phase difference signal; determining a second phase difference signal through a second phase discriminator; determining a total phase adjustment amount according to the first phase difference signal and the second phase difference signal; and determining a phase-locked phase value according to the total phase adjustment quantity so as to update the output phase value. According to the scheme of the invention, high-stability technical guarantee is provided for realizing grid connection of high-performance energy storage equipment.

A system and method for performing digital calibration of non-linearity in a circuit is presented. The circuit includes a phase detector, a statistics gathering device, and a feedback device. The phase detector provides information regarding a relationship between a clock from the programmable clock phase circuit and a reference signal. The statistics gathering device is coupled to the phase detector. The statistics gathering device receives an output of the phase detector to measure linearity of the programmable clock phase circuit. The feedback device is coupled to the statistics gathering device. The feedback device controls a delay and adjusts a phase of the clock based on measured values received from the statistics gathering device.