715 results about "Phase detector" patented technology

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The invention relates to a phase-locked loop circuit, a clock generator, a chip and electronic equipment, and the phase-locked loop circuit mainly comprises a phase frequency detector which is used for generating a phase detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; the proportional path module is used for generating a first control current according to the phase discrimination output signal; the integral path module is used for generating a second control current according to the phase discrimination output signal; the current control oscillation module is used for generating a clock output signal according to the first control current and the second control current; and the feedback frequency divider is used for obtaining a feedback clock signal through frequency division of the clock output signal. According to the phase-locked loop, the advantages of the analog charge pump phase-locked loop and the full-digital phase-locked loop are combined, the generation of a high-performance clock which is small in area, high in bandwidth, stable in loop and low in quantization noise is facilitated, the applicability of the phase-locked loop to the high bandwidth requirement is facilitated, the quantization noise is reduced, and the performance of the phase-locked loop is improved. And unconditional stability of the phase-locked loop is realized theoretically.

A self-adaptive high-dynamic spread spectrum tracking receiver relates to the technical field of satellite communication and comprises an AGC loop, an A / D converter, a PN code capturing and tracking loop, a single carrier loop, a despreading device, a phase discriminator, a phase shift signal generator and a low-pass processor. The method comprises the following steps of: converting a signal into a digital signal, subsequently generating an output tracking signal through a PN code capturing and tracking loop, processing through a single carrier loop to obtain a captured tracking signal and an amplitude excitation signal, and finally carrying out de-spreading and phase discrimination to generate an azimuth error voltage signal and a pitching error voltage signal; the receiver can stably receive and process spread spectrum signals sent by a high-speed target.

The invention discloses a frequency measurement circuit and a frequency measurement method, belongs to the technical field of frequency measurement, and mainly solves the problems that the existing frequency measurement is large in frequency error, low in frequency measurement speed and narrow in frequency measurement bandwidth, and cannot meet the requirements of radar communication. The frequency measurement circuit comprises an FPGA control module, a reference clock circuit connected with the FPGA control module, a DDS frequency output circuit, a phase discrimination frequency control circuit, a frequency mixer connected with the phase discrimination frequency control circuit, and a radio frequency input circuit connected with the frequency mixer. According to the frequency measurement technology, the DDS output frequency is directly collected according to the characteristic that the FPGA collects the low frequency, the DDS output frequency serves as the phase discriminator phase discrimination frequency, frequency measurement is conducted in a phase locking mode, and the frequency measurement precision is high; the phase discriminator is set to have a fixed frequency dividing ratio, the phase discriminator is configured with a fixed register, a DDS frequency sweeping mode is adopted, and the frequency measurement time is short by changing the phase discrimination frequency of the phase discriminator to the output frequency of the phase-locked loop; and the frequency measurement bandwidth is increased by using a radio frequency input frequency division mode.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

The invention belongs to the technical field of optical communication, and particularly relates to a high-stability photo-generated millimeter wave system based on a phase-locked loop, which comprises a first laser, a second laser, an acousto-optic frequency shifter, a dense wavelength division multiplexer, an inner loop feedback control loop and an outer loop signal output branch, the inner loop feedback control loop comprises a phase modulator, an optical filter, a photoelectric detector, a frequency division arithmetic unit, a phase frequency detector, a loop filter, a voltage-controlled oscillator and a first power amplifier which are sequentially connected in series, and the output of the first power amplifier is connected with an acousto-optic frequency shifter; the inner loop feedback control loop further comprises a cesium atomic clock, a microwave source and a second power amplifier; wherein the cesium atomic clock is connected with the microwave source and the phase frequency detector, and the output of the microwave source is connected with the phase modulator after passing through the second power amplifier.

Embodiments of the present disclosure include techniques for synchronizing processors. In one embodiment, one or more processors on different integrated circuit die are synchronized using a synchronization circuit on one of the die. The synchronization circuit receives count phases and adjusts clock signals, and counts in some embodiments, to synchronize the processors. In one embodiment, the synchronization circuit comprises a phase detector that receives particular bits of the count signal as the count phases.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

The invention relates to the technical field of space optical communication and distance measurement, in particular to a distance measurement method and device based on a non-equal sampling digital phase discriminator and a storage medium. A non-equal sampling method is used for carrying out sampling and phase discrimination on data bit clocks on two asynchronous clock domains for sending and receiving GTX, and hardware resources required for processing all use an FPGA internal digital logic block; the clock processing rate and the GTX sending and receiving clock rate are kept in a non-integer multiple relationship, so that the measurement precision of the phase difference between the two clock rates is improved, and the purpose of improving the laser ranging precision on the basis of simplifying the hardware design of a ranging system is achieved.

The invention discloses a phase-locked loop quantization noise calibration method and system, electronic equipment and a storage medium. The method comprises the following steps: a phase frequency detector performs correlation processing on a feedback signal output by a modulator and a reference signal output by a phase discriminator to generate a gain coefficient; multiplying the gain coefficient by a feedback signal output by the modulator to output a first gain signal; subtracting the first gain signal from a reference signal output by the phase discriminator to output a second gain signal; the second gain signal is filtered by the digital loop filter to obtain a filtered signal and the filtered signal is output to the digital time converter; and the digital time converter processes the filtering signal to obtain a pulse signal suitable for being processed by the phase discriminator and outputs the pulse signal to the phase discriminator. The LMS algorithm is adopted, and on the basis of the complementary digital time converter calibration technology, quantization noise is eliminated through a low-energy-consumption circuit.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

According to the low-orbit satellite signal broadband tracking method based on the square difference phase discriminator, a frequency discriminator and the square difference phase discriminator are designed according to a signal modulation mode of a star network low-orbit satellite, accurate frequency discrimination and phase discrimination can be carried out on star network low-orbit satellite signals, and the low-orbit satellite signal broadband tracking method based on the square difference phase discriminator is obtained. The high accuracy can be kept even in a complex and rapidly changing signal environment; in addition, the method adopts a second-order frequency locking auxiliary third-order phase locking design, so that high-dynamic frequency offset change caused by high-speed movement of a low-orbit satellite of the star network can be processed more effectively, and the stability and the accuracy of signal tracking are ensured. According to the invention, the tracking capability of the satellite network low-orbit satellite signal is obviously improved, stable frequency and phase locking can be realized under a high dynamic condition, reliable receiving and processing of the signal are ensured, a solid guarantee is provided for efficient operation of a satellite network low-orbit satellite system, and an important foundation is laid for development of a future space-ground integrated network.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

The invention relates to a delay locked loop circuit comprising: a voltage controlled delay line (VCDL); a phase detector circuit configured to process the first and last output signals of the VCDL to provide: i) an uplink pulse signal; and ii) a downlink pulse signal; a charge pump configured to provide a feedback voltage signal based on the uplink pulse signal and the downlink pulse signal; a phase signal processor configured to process the uplink pulse signal and the downlink pulse signal to provide a delay code lock signal representing whether the first output signal is out of phase with the last output signal by 2 [pi] radian; and a delay code setter configured to provide a delay code setting signal representing one candidate delay code in the sequence of different candidate delay codes. When the delay locked loop circuit is in a calibration operation mode: the fixed voltage source provides a fixed voltage signal as a control voltage signal of the voltage controlled delay line; when the delay code lock signal indicates that the first output signal and the last output signal have no out-of-phase 2 [pi] radians: the delay code setter applies a delay code setting signal to the VCDL such that the delay code setter sequentially applies different candidate delay codes to the voltage controlled delay line until a selected delay code is allocated; and when the delay locked loop circuit is in an active operation mode: the charge pump provides a feedback voltage signal as a control voltage signal of the voltage controlled delay line; and the VCDL uses the selected delay code as the delay code.

A circuit detects a voltage droop exhibited by a power supply. A first signal delay line outputs a first delayed signal. A second delay line outputs a second delayed signal. A phase detector compares the first and second delayed signals and outputs a comparison signal indicating which of the first and second signal delay lines exhibits a shorter delay. A reset circuit resets the first and second signal delay lines in response to the comparison signal, and a clock controller outputs a command to adjust a clock frequency or engage in other mitigation measures based on the comparison signal.

The present disclosure provides an apparatus and method of discriminating a phase of reflected waves. The apparatus includes a sensing impedance circuit disposed between a signal source and a load and having a variable sensing impedance, a directional coupler disposed between the signal source and the sensing impedance network, and a controller configured to detect intensities of an input signal transmitted from the signal source to the load and a reflected signal reflected from the load, determine a magnitude of the reflection coefficient based on the intensities of the signals, determine a difference in the magnitude of the reflection coefficient based on a plurality of magnitudes of the reflection coefficients obtained with respect to different sensing impedances, discriminate a range of the phase of the reflected waves based on the difference in the magnitude of the reflection coefficient, and control the sensing impedance network to change the sensing impedance.

An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

The invention belongs to the technical field of clock synchronization, and provides a clock synchronization device and a clock synchronization method of a distributed system. Wherein the distributed system comprises a master node and a plurality of slave nodes, the master node and the slave nodes are in two-way communication, and the clock synchronization device comprises a single-core optical cable, an optical switch and a double-frequency-mixing phase discriminator and is used for connecting the master node and the slave nodes; the optical switch is switched between a communication mode and a short circuit mode; when the optical switch is in a communication mode, the single-core optical cable is connected with the master node for transmitting and the slave node for receiving, or is connected with the slave node for transmitting and the master node for receiving; when the optical switch is in a short-circuit mode, the single-core optical cable is connected with transceiving of the master node or transceiving of the slave node; and the dual-mixing phase discriminator is used for measuring the phase difference between the local clock and the received data recovery clock. According to the invention, respective transmit-receive delays of the master and slave nodes and bidirectional transmission delays between the master and slave nodes can be obtained, the clock difference can be conveniently obtained according to the unidirectional transmission delays, and the synchronization precision is improved.

Systems and methods are disclosed for clock phase calibration between source logic and a coupled serial data link transmitter, enabling low-latency synchronization into the transmitter. In calibration mode, a phase relationship is monitored between a first clock, driving the source logic, and a second clock, tightly synchronized with a serial clock of the data link. The first clock is adjusted to a first phase at which the first and second clocks are aligned. The first clock phase is set for operation mode based on the first phase. Monitoring uses a D-type flip-flop as a phase detector. Adjustment is in steps of half the serial clock period. Variations are disclosed.

A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.

The invention discloses a digital signal controlled phase interpolator, which comprises a digital control module, a phase rotator, a mirror image phase rotator and a clock selection module, and is characterized in that the digital control module receives a phase discrimination result from a phase discriminator and obtains a control signal, and the phase discrimination result comprises a high-level Early signal and a low-level Late signal; the phase rotator receives the four-phase orthogonal clock signal and generates a first clock signal with a fixed phase according to the control signal, and the mirror image phase rotator receives the four-phase orthogonal clock signal and generates a second clock signal with a fixed phase according to the control signal; the clock selection module selectively outputs the first clock signal or the second clock signal. The digital control module is adopted to control the phase interpolator, the octagonal phase rotator is adopted to realize high linearity of phase interpolation, and the mirror image phase rotator is adopted to effectively eliminate clock jitter generated during conversion of a phase interpolation quadrant.

The utility model discloses a broadband low-phase-noise small-step frequency source, which comprises a large step ring and a small step ring, and is characterized in that the large step ring comprises a first power divider, a frequency multiplier, a first frequency mixer, a second power divider, a first voltage-controlled oscillator and a first phase discriminator; and the small step ring comprises a direct digital frequency synthesizer, a second phase discriminator, a second frequency mixer, a third power divider, a loop filter, a second voltage-controlled oscillator and a programmable frequency divider. According to the utility model, a reference signal is divided into three paths of reference signals after being subjected to power division by the first power divider, and the three paths of reference signals are respectively sent to the frequency multiplier, the first phase discriminator and the direct digital frequency synthesizer, so that the homology of the whole circuit is ensured; a broadband low-phase-noise small-stepping signal is generated through multi-stage frequency doubling and phase locking of the large stepping ring and the small stepping ring and a digital frequency synthesis device, and no fractional stray exists, so that the problems that the frequency coverage is not wide enough, the fractional stray exists, and the phase noise is large are solved.

The invention provides a signal data synchronization method for a multi-microphone array, and the method comprises the steps: generating a digital synchronization signal through a main control processing unit, generating an analog synchronization signal through a digital-to-analog converter, and transmitting the analog synchronization signal to each microphone array unit; each microphone array unit obtains a respective synchronizing signal and transmits the synchronizing signal to the main control processing unit; the re-sampler adjusts the sampling interval of the synchronizing signal, and the phase discriminator detects the phase difference between the re-sampled synchronizing signal and the local high-frequency synchronizing signal and feeds back the phase difference to the re-sampler until the re-sampled synchronizing signal and the local high-frequency synchronizing signal have the same frequency and keep a stable phase difference; and performing mobile cross-correlation on the resampled synchronizing signal and a local high-frequency synchronizing signal in the delay estimator, and compensating delay deviation through a delayer. And the main control processing unit performs synchronization processing by using the local synchronization signal and the received return synchronization signal, and further adjusts the microphone signal of the array unit to achieve strict sample synchronization.

Systems, methods, and circuitry for determining a delay through a modem of a transceiver are provided. An integrated circuit system may include a transmit signal path, delay calibration circuitry, and a phase detector. The delay calibration circuitry may allow determination of a delay through a transmit signal path between a calibration sequence signal source and an output of the transmit signal path. The transmit signal path may include a number of processing stages having a possible delay variation under different conditions. The phase detector may determine a fractional baud rate difference between the calibration sequence signal source and a signal representative of the output of the transmit signal path

The embodiment of the invention discloses a phase discriminator circuit, a phase-locked loop circuit and a memory. The phase discriminator circuit comprises a phase discriminator unit which is connected with a first input path and a second input path; the first input path is used for inputting a reference clock signal to the phase discriminator unit; the second input path is used for inputting a feedback clock signal to the phase discriminator unit; the control unit is connected with the second input path of the phase discriminator unit and used for delaying the feedback clock signal for a preset time length to obtain a delayed clock signal, and the delayed clock signal is input to the phase discriminator unit through the second input path; wherein the phase discriminator unit obtains a first phase discrimination signal based on the feedback clock signal and the reference clock signal, and obtains a second phase discrimination signal based on the delay clock signal and the reference clock signal, and the first phase discrimination signal and the second phase discrimination signal are both used for representing the sequential relationship of clock signals input by different input paths of the phase discriminator unit.

The invention discloses a GNSS deception jamming suppression method based on inertial navigation auxiliary tracking, and the method specifically comprises the steps: carrying out the signal modeling through coherent integration after a radio frequency front end of a GNSS receiver receives a signal, and obtaining a coherent integration value of an in-phase branch and an orthogonal branch; constructing an observation equation and a state equation through coherent integration values of the orthogonal branch and the in-phase branch, and constructing a code loop phase discriminator error and a carrier loop frequency discriminator error by using coherent integration to obtain the observation equation and the state equation; obtaining deception jamming of different traction speeds by using combined detection quantity of constructed SQM and satellite and inertial information; on the basis of an NEYMAN-PEARSON detection theory framework, the optimal detection performance is sought under the constraint condition that the maximum false alarm probability PFAMAX is met, and robust Kalman filtering suitable for deception jamming suppression is designed; and inputting the state equation and the observation equation into robust Kalman filtering to obtain an interference coefficient and an anti-deception adaptive factor for deception interference suppression. According to the method, deception jamming of slow traction is effectively suppressed.

System and method for controlling one or more light emitting diodes. For example, the system includes: a phase detector configured to process information associated with a rectified voltage generated by a rectifier and related to a TRIAC dimmer, the rectified voltage corresponding to a first waveform during a first half cycle of an AC voltage and corresponding to a second waveform during a second half cycle of the AC voltage, the phase detector being further configured to generate a phase detection signal representing a first time duration during which the first waveform indicates that the rectified voltage is larger than a predetermined threshold and representing a second time duration during which the second waveform indicates that the rectified voltage is larger than the predetermined threshold; and a mode detector configured to process information associated with the rectified voltage.