493 results about "Phase detector" patented technology

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

An interface device is adapted for a semiconductor device including a first die and a second die. The first die and the second die are electrically connected to each other to be stacked into a 3D structure. The interface device includes a controllable delay line, a clock generator, and a phase detector (PD) arranged on the second die. The controllable delay line receives a source clock signal of the first die. The controllable delay line delays the source clock signal to generate a first delayed clock signal. The clock generator generates a second delayed clock signal according to the first delayed clock signal. The PD detects a phase difference between a gained clock signal of the first die and the second delayed clock signal to generate phase relationship information. Based on the phase relationship information, the controllable delay line adjusts a delay amount to the source clock signal.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

The invention discloses a fractional frequency division frequency synthesizer with output signal phase synchronization and frequency modulation continuous wave functions, and the basic structure is a charge pump phase-locked loop. Comprising a phase frequency detector, a first charge pump, a second charge pump, a low-pass filter, a voltage-controlled oscillator, a first buffer, a second buffer, a two-frequency divider chain, an IQ undersampling circuit, a local oscillator generator, a programmable multimode frequency divider, a Delta-Sigma modulator (DSM), a first selector, a second selector, a third selector, a tracking phase accumulator, a numerical control oscillator, an accumulation phase difference register and an atan2 logic circuit. The device comprises a main phase control circuit, a phase adjusting circuit, an enabling control circuit, a waveform generator and a serial peripheral interface. The decimal frequency-division frequency synthesizer can be applied to a general-inductance integrated system, ensures that output signals provided by a plurality of decimal frequency-division frequency synthesizers are consistent in phase in a multi-channel radio frequency transceiving system adopting a multi-chip splicing mode, and can also be applied to the general-inductance integrated system as a sensing signal source; and the speed and the distance of an object can be quickly sensed by the high linearity and the quick chirp capability of an output signal. The decimal frequency division frequency synthesizer is applied to a linear frequency modulation continuous wave radar system, initial phase synchronization can be carried out firstly, then frequency continuous modulation is carried out, and measurement errors can be eliminated. In view of functional similarity of partial modules of the synchronous loop and the FMCW loop, such as a phase frequency detector, a charge pump, a voltage-controlled oscillator and the like, the modules can be shared, so that the power consumption and area cost of the system are remarkably reduced.

The invention relates to the technical field of analog integrated circuits, and discloses a reference clock frequency multiplier circuit and a chip, and the reference clock frequency multiplier circuit comprises a phase discriminator, a charge pump, a loop filter, a voltage-controlled delay unit, a multiphase injection locked ring oscillator and an edge combiner. And the voltage-controlled delay unit, the phase discriminator, the charge pump and the loop filter form a multi-phase clock generator. The multi-phase injection clock signal is generated by adopting the voltage-controlled delay unit, and the multi-phase injection locking ring oscillator is further adopted as an input clock source of the edge combiner, so that the phase error of the multi-phase injection clock signal generated by the voltage-controlled delay unit is suppressed; therefore, a frequency multiplication clock signal with an accurate duty ratio and low noise is obtained.

An example apparatus includes a phase detector, a digital discriminator, and a logic circuit. A status signal of the phase detector is at least partially based on a phase relationship between a reference clock and a feedback clock, the feedback clock generated by a clock tracking circuit to track the reference clock. The digital discriminator may sample the status signal of the phase detector. The logic circuit may determine a locked status of the clock tracking circuit at least partially based on samples of the status signal of the phase detector.

Systems and methods are disclosed for clock phase calibration between source logic and a coupled serial data link transmitter, enabling low-latency synchronization into the transmitter. In calibration mode, a phase relationship is monitored between a first clock, driving the source logic, and a second clock, tightly synchronized with a serial clock of the data link. The first clock is adjusted to a first phase at which the first and second clocks are aligned. The first clock phase is set for operation mode based on the first phase. Monitoring uses a D-type flip-flop as a phase detector. Adjustment is in steps of half the serial clock period. Variations are disclosed.

A receiver includes an analog to digital converter circuit, a phase detector circuit, a digital loop filter circuit, a phase interpolator circuit, and a bias adaption circuit. The analog to digital converter circuit is configured to convert a first signal into a second signal according to a clock signal. The phase detector circuit is configured to detect a phase of the second signal to generate a phase detection signal. The digital loop filter circuit is configured to scale the phase detection signal with a proportional path gain coefficient and a bias value to generate a third signal. The phase interpolator circuit is configured to generate the clock signal according to the third signal. The bias adaptation circuit is configured to accumulate the phase detection signal to generate the bias value.

Systems, methods, and circuitry for determining a delay through a modem of a transceiver are provided. An integrated circuit system may include a transmit signal path, delay calibration circuitry, and a phase detector. The delay calibration circuitry may allow determination of a delay through a transmit signal path between a calibration sequence signal source and an output of the transmit signal path. The transmit signal path may include a number of processing stages having a possible delay variation under different conditions. The phase detector may determine a fractional baud rate difference between the calibration sequence signal source and a signal representative of the output of the transmit signal path

The embodiment of the invention discloses a phase discriminator circuit, a phase-locked loop circuit and a memory. The phase discriminator circuit comprises a phase discriminator unit which is connected with a first input path and a second input path; the first input path is used for inputting a reference clock signal to the phase discriminator unit; the second input path is used for inputting a feedback clock signal to the phase discriminator unit; the control unit is connected with the second input path of the phase discriminator unit and used for delaying the feedback clock signal for a preset time length to obtain a delayed clock signal, and the delayed clock signal is input to the phase discriminator unit through the second input path; wherein the phase discriminator unit obtains a first phase discrimination signal based on the feedback clock signal and the reference clock signal, and obtains a second phase discrimination signal based on the delay clock signal and the reference clock signal, and the first phase discrimination signal and the second phase discrimination signal are both used for representing the sequential relationship of clock signals input by different input paths of the phase discriminator unit.

The invention discloses a GNSS deception jamming suppression method based on inertial navigation auxiliary tracking, and the method specifically comprises the steps: carrying out the signal modeling through coherent integration after a radio frequency front end of a GNSS receiver receives a signal, and obtaining a coherent integration value of an in-phase branch and an orthogonal branch; constructing an observation equation and a state equation through coherent integration values of the orthogonal branch and the in-phase branch, and constructing a code loop phase discriminator error and a carrier loop frequency discriminator error by using coherent integration to obtain the observation equation and the state equation; obtaining deception jamming of different traction speeds by using combined detection quantity of constructed SQM and satellite and inertial information; on the basis of an NEYMAN-PEARSON detection theory framework, the optimal detection performance is sought under the constraint condition that the maximum false alarm probability PFAMAX is met, and robust Kalman filtering suitable for deception jamming suppression is designed; and inputting the state equation and the observation equation into robust Kalman filtering to obtain an interference coefficient and an anti-deception adaptive factor for deception interference suppression. According to the method, deception jamming of slow traction is effectively suppressed.

A clock calibrator comprises an input port configured to receive a two-level symbol from a quarter-rate transmitter, the two-level symbol having a period of P unit intervals with a first rising edge launched by one quarter-rate clocks. The clock calibrator includes a clock generator configured to generate four calibration clocks based on the quarter-rate clocks, each calibration clock having the period of P UIs and sequentially having a calibration rising edge delayed by M UIs. The clock calibrator includes a delay-tuner configured to retime the calibration rising edge and a phase detector configured to determine a coarse parameter and a k-th fine parameter based on alignment between the retimed calibration rising edge and the first rising edge with (k−1)M UIs delay. Here P is an integer multiple of 4, M is one less than an integer multiple of 4, and k is selected from 1, 2, 3, and 4.

A clock recovery system for recovering an in-band communication clock in a wireless power transfer system can in include: a phase locked loop; and a bit decision block and a multiplexer that cooperate to selectively provide the error signal to the loop filter responsive to detected bits in the in-band communication bitstream. The phase locked loop can further include: a phase detector that computes an error signal from a difference between an instantaneous peak location and an estimated peak location correlated to a symbol in an in-band communication bitstream; a loop filter that selectively receives the error signal; and a voltage controlled oscillator that adjusts its output frequency responsive to an output of the loop filter.

The utility model provides a phase-locked loop circuit, which relates to the technical field of phase-locked loops and comprises a reference frequency multiplication filtering unit, an auxiliary mixing frequency-locked phase loop unit and a main mixing frequency-locked phase loop unit. The reference frequency multiplication filtering unit is used for receiving the first reference signal, performing frequency division processing on the first reference signal, performing frequency multiplication filtering on one path of signal after frequency division processing, and outputting a low-phase noise signal; the auxiliary frequency-mixing phase-locked loop unit is used for receiving the low-phase noise signal output by the reference frequency-doubling filtering unit and the other path of signal obtained by frequency division of the reference frequency-doubling filtering unit, and outputting an LO reference signal after frequency mixing and phase discrimination; and the main frequency mixing phase-locked loop unit is used for receiving the second reference signal and the LO reference signal output by the auxiliary frequency mixing phase-locked loop unit, and outputting a coherent signal after frequency mixing and phase discrimination. According to the utility model, the LMX2820 is used as the phase discriminator, the phase detection range is small, the locking detection can be easier, and the practicability is strong.

Embodiments described herein are directed to a position sensor that includes a first receiver coil electrically coupled to a first multiplier to generate a first output, a second receiver coil electrically coupled to a second multiplier to generate a second output, a transmitter coil electrically coupled to an oscillator, the oscillator electrically coupled to a third multiplier to generate a third output, a phase-locked loop electrically coupled to the oscillator and the transmitter coil, a summing circuit configured to receive the first output and the second output and configured to generate a signal, a phase detector configured to receive the signal and the third output, the phase detector outputting a sense signal that is indicative of an angle of the motor position sensor, and a pair of op amps electrically coupled to the phase detector. The op amps configured to output an analog differential signal and a differential phase signal.

A clock data recovery circuit includes a phase detector, a first signal processing path, a second signal processing path, an oscillator circuit, and a phase control circuit. The phase detector samples an input data signal according to a first clock signal to generate an up control signal and a down control signal. The first signal processing path includes at least one first signal processing device to generate a phase control signal according to the up control signal and the down control signal. The second signal processing path includes at least one second signal processing device to generate a frequency control signal according to the up control signal and the down control signal. The oscillator circuit generates a plurality of second clock signals according to the frequency control signal. The phase control circuit controls a phase of the second clock signals according to the phase control signal to generate the first clock signal.

The invention discloses a phase-locked loop system based on high-speed low-jitter double-edge sampling phase discrimination. The phase-locked loop system comprises a sampling phase discriminator which comprises a first sampling path, a second sampling path and a non-overlapping sampling clock generation circuit used for generating a first sampling clock signal and a second sampling clock signal; alternately sampling and updating the phase error voltage signal through the first sampling path and the second sampling path; the transconductance amplifier is used for receiving the phase error voltage signal and a reference voltage and inputting an output current signal into the filter so as to output an integral voltage signal; the filter is also used for receiving the phase error voltage signal and outputting a proportional voltage signal; the voltage-controlled oscillator is used for receiving the integral voltage signal and the proportional voltage signal and outputting a feedback clock signal. According to the phase-locked loop system provided by the invention, the rising edge and the falling edge of the clock signal are fully utilized to update the control voltage at double reference frequency.

The invention relates to the technical field of servo system control, in particular to a noise measurement suppression method and device based on axial angle tracking angular position estimation. The method comprises the following steps: determining a first measurement angle after sine transformation and a second measurement angle after cosine transformation based on the first measurement angle and the second measurement angle; simplifying the first measurement angle after sine transformation and the second measurement angle after cosine transformation to obtain a simplified first measurement angle and a simplified second measurement angle; based on the simplified first measurement angle and the simplified second measurement angle, determining a representation relation between a phase discriminator tracking error of the servo system and a phase-locked loop output angle; determining an input of the servo system based on the representation relationship; determining an estimated angle value based on the input of the servo system and a preset closed-loop transfer function; and controlling the servo system based on the estimated angle value. Therefore, the control precision of the servo system can be improved.

This application discloses an automatic calibration circuit and method for mismatch compensation current of a phase-locked loop (PLL) charge pump, relating to the field of integrated circuit technology. The calibration circuit includes: a frequency and phase detector, a charge pump, an XOR module, a filter capacitor, a digital-to-analog converter (DAC) module, and a digital logic state machine. The first output terminal of the frequency and phase detector is connected to the first input terminal of the charge pump and the first input terminal of the XOR module, respectively. The second output terminal of the frequency and phase detector is connected to the second input terminal of the charge pump and the second input terminal of the XOR module, respectively. The output terminal of the XOR module is connected to the first terminal of the filter capacitor and the input terminal of the DAC module, and the second terminal of the filter capacitor is grounded. The output terminal of the DAC module is connected to the input terminal of the digital logic state machine, and the output terminal of the digital logic state machine is connected to the third input terminal of the charge pump. The output terminal of the charge pump is used to connect to the input terminal of the low-pass filter in the PLL. This application can compensate for the mismatch current of the charge pump in real time.

The present invention provides phase interpolator including a phase detector, a filter and an oscillator is disclosed. The phase detector is configured to receive a first clock signal and a second clock signal, and sample the first clock signal and the second clock signal to generate a detection result, wherein phases of the first clock signal and the second clock signal are different. The filter is configured to filter the detection result to generate a filtered detection result. The oscillator is configured to control frequencies of the first clock signal and the second clock signal, or control a frequency of a sampling clock signal of the phase interpolator according to the filtered detection result.

A clock compensation circuit of a first integrated circuit includes a phase detector circuit. The phase detector circuit includes a first input operative to receive a first clock signal from a second integrated circuit and a second input operative to receive a second clock signal for a circuit of the first integrated circuit. The phase detector circuit is configured to output a first control signal indicating whether the first and second clock signals are synchronized, and a second control signal indicating whether a phase of clock signals is different. The clock compensation circuit also includes a control circuit, responsive to one or more of the first and second control signals, and configured to generate one or more delay control signals. The clock compensation circuit also includes a delay circuit configured to apply a delay to the second clock signal based on the one or more delay control signals.

This invention discloses a pilot-type carrier phase recovery circuit and a reverse antenna array system, belonging to the field of 5G millimeter-wave communication. The pilot-type carrier phase recovery circuit includes a digital phase detector, a quadrature mixer, a quadrature voltage-controlled oscillator, a low-pass filter, a high-pass filter, a polyphase filter, a loop filter, a first intermediate frequency amplifier, a second intermediate frequency amplifier, a first shaping circuit, and a second shaping circuit. Applied to a reverse antenna array system, this invention performs carrier phase recovery on the data signal and pilot signal output from the receiver, separating the data signal without spatial phase information and the spatial phase information used for reverse transmission. This invention enables high-order modulation full-duplex communication and real-time tracking of moving targets, featuring high integration, small area, high communication speed, and strong anti-interference capability.

The invention provides a PLL loop bandwidth adjusting circuit, a control method and a circuit board. The PLL loop bandwidth adjusting circuit comprises a phase frequency detector, a charge sharing filter, a phase-locked loop proportional path module and an adjustable voltage-controlled oscillator. The input end of the phase frequency detector is connected with a reference signal; the first output end of the phase frequency detector is connected with the first input end of the adjustable voltage-controlled oscillator through the charge sharing filter; the second output end of the phase frequency detector is connected with the second input end of the adjustable voltage-controlled oscillator through the phase-locked loop proportional path module; the phase-locked source has the beneficial effects of high flexibility and low power consumption, and is suitable for the technical field of phase-locked sources.

The application provides an equivalent sampling circuit and device, and an equivalent sampling method, and relates to the field of circuits.The equivalent sampling circuit comprises a frequency discriminator, a voltage-controlled oscillator, a first frequency divider, a second frequency divider and a sampling unit; wherein the frequency discriminator is used to obtain a reference signal and a first frequency division signal, compare the frequency and phase of the first frequency division signal and the reference signal respectively, and obtain the frequency difference and phase difference of the first frequency division signal and the reference signal; the voltage-controlled oscillator is used to generate a second oscillation signal based on the frequency difference and the phase difference; the second frequency divider is used to perform integer frequency division on the second oscillation signal by using an integer frequency division coefficient to generate a second frequency division signal; and the sampling unit is used to perform equivalent sampling on a to-be-tested signal based on the second frequency division signal.The equivalent sampling circuit in the application can greatly improve the time delay step of the second frequency division signal, does not increase the circuit cost, and ensures the accuracy of sampling.

The application discloses a double feedback branch current compensation type charge pump circuit, which comprises a core circuit, a double feedback branch and a bias circuit connected in sequence, wherein the input node of the double feedback branch is connected with the core circuit for detecting the potential change of the output voltage, the first output node of the first feedback branch in the double feedback branch is connected with the gate of the bias circuit, the second output node of the second feedback branch is connected with the bias circuit, and the up and down charging and discharging currents are carried out phased current compensation through the bias circuit according to the degree of the output voltage deviating from the center potential. The application solves the mismatching problem of the up and down charging and discharging currents when the output voltage deviates from the center potential through the double feedback branch, can convert the phase error output by the frequency discriminator into the difference between the charging and discharging currents, charges and discharges the loop filter to generate the control voltage of the voltage controlled oscillator, thereby realizing the lower charging and discharging current mismatching in the wider control voltage range, the smaller ripple on the output voltage, and the optimization of the jitter performance of the output clock of the phase-locked loop.

The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.

The application relates to a delay calibration circuit for a time-to-digital converter. The delay calibration circuit comprises a frequency discriminator, a charge pump, a filtering capacitor, a bias voltage generating unit and a voltage-controlled delay chain; the voltage-controlled delay chain is used for receiving a starting signal and outputting a feedback signal after time delay; the frequency discriminator is used for receiving the starting signal and the feedback signal, converting a phase difference between the starting signal and the feedback signal into a voltage pulse signal, and outputting the voltage pulse signal to the charge pump; the charge pump is used for outputting a current signal with a corresponding pulse width to the filtering capacitor under the control of the voltage pulse signal; the filtering capacitor is used for converting the current signal into a time delay control voltage, and applying the time delay control voltage to an input end of the bias voltage generating unit; the bias voltage generating unit is used for generating a bias voltage under the action of the time delay control voltage, and controlling a delay time of the voltage-controlled delay chain by using the bias voltage. The delay calibration circuit is convenient to realize and high in precision.

The present invention discloses a primary-secondary delay-locked loop (DLL) with dual delay lines, comprising a power-on reset module (POR), a primary delay-locked loop (DLL1), a secondary delay-locked loop (DLL2), and a lock indication module (LI). The power-on reset module is connected to the reset control module of the primary delay-locked loop (DLL), the output voltage signal (V1) of the primary delay-locked loop (DLL) is connected to the short link of the secondary dual-chain voltage-controlled delay line, an external input clock signal (CLK) is connected to the primary and secondary delay-locked loops, a total reset signal generated by the primary delay-locked loop is connected to the secondary delay-locked loop filter module, and the output signals of the phase frequency detector (PFD) module (PFD1) and the phase frequency detector (PFD) module (PFD2) are respectively connected to the lock indication module. The DLL of the present invention has the advantages of accurate locking and small area overhead.

A digital phase-locked loop that tunes frequency and corrects phase errors using a variable capacitance based on a pulse signal is provided. The digital phase-locked loop comprises: a phase detector for comparing a phase of a reference signal with a phase of a feedback signal; a digital loop filter for outputting an adjustment signal for adjusting the duty ratio of the first time period based on the lifting signal of the phase detector; the variable capacitance controller is used for outputting a capacitance control signal with a duty ratio based on the feedback signal, the adjusting signal and the lifting signal; a digitally controlled oscillator for changing a first capacitance of the capacitor bank circuit based on the capacitance control signal and adjusting a phase based on an average of the first capacitance during a first time period; and the frequency divider is used for carrying out frequency division on the output signal.