56results about "Receiver initialisation" patented technology

The embodiment of the invention relates to a method, equipment and device for communication and a computer readable storage medium. In some embodiments, a first security frame may be generated to be transmitted in a time slot in a first round belonging to a first block according to a block-based time structure or a superblock-based time structure, where the block-based time structure or the superblock-based time structure includes a plurality of blocks, and where the block-based time structure includes a first block and a second block. Each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of time slots, the first security frame is protected by a first random number, the first random number is constructed according to identification information associated with the first security frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the second round. The block index is an index of the first block. Accordingly, a secure operation may be performed, and it may be ensured that communication is secure.

An electronic device includes a first sample circuit configured to generate a first sampling signal by sampling an input signal in response to edges of a clock signal, a first comparator configured to generate a first logic decision signal by comparing a voltage level of the first sampling signal with a reference voltage level, an analog bang-bang phase detector configured to generate a first detection signal by executing an exclusive OR (XOR) operation on successive samples of the first logic decision signal, and a digitally controlled oscillator configured to vary a frequency of the clock signal according to the first detection signal.

A method includes that a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block.

Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

Embodiments of the present application provide a time synchronization method and apparatus, a computer readable medium, and an electronic device. The time synchronization method comprises: receiving a trigger delivery service request message transmitted by an application function (AF) entity, wherein the trigger delivery service request message comprises the identifier of a target user equipment and a time sensitive network (TSN) trigger container, the TSN trigger container is used for indicating a TSN time synchronization trigger condition; and transmitting a submission triggering message to a short message service-service center (SMS-SC), wherein the submission triggering message is used for requesting the SMS-SC to transmit a short message containing the TSN trigger container to the target user equipment, so that the target user equipment performs a TSN time synchronization operation based on the TSN trigger container.

According to a first aspect, a method for processing a time synchronization packet is provided, including: A terminal device receives a time synchronization packet of a first clock source from an external device; receiving first indication information from a network device, where the first indication information indicates the terminal device to enter a time synchronization activated state of the first clock source, or the first indication information indicates the terminal device to enter a time synchronization deactivated state of the first clock source; and processing the time synchronization packet of the first clock source based on the first indication information. When a clock source is activated and deactivated, the terminal device processes a time synchronization packet of the clock source in different manners, and signaling indicates whether the clock source is activated or deactivated. This can allow the terminal device to perform processing in different manners, reduce power consumption of a communications device, and improve performance of the communications device while ensuring a service requirement on time synchronization precision.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

The invention relates to a device and a transmission system for synchronizing symbol clocks during data transmission between a sender and a receiver, the device having an estimation means (30) and a symbol synchronizer (40). An estimation unit (30) receives a first signal (S1) generated by a sender (10) and estimates a phase deviation (POFF) and / or a frequency deviation (FOFF) between a symbol clock of the sender (10) and a symbol clock of a receiver (20) on the basis of the first signal, generates the first signal (S1) on the basis of the symbol clock of the sender, and analyzes and evaluates the first signal in the receiver on the basis of the symbol clock of the receiver. The device (5) initializes the symbol synchronizer (40) on the basis of the evaluated phase deviation (POFF) and / or the evaluated frequency deviation (FOFF). The symbol synchronizer (40) receives a second signal (S2) generated by the sender (10) in order to generate, on the basis of the second signal (S2), an output signal (SO) representing symbols transmitted inside the second signal (S2) synchronized with the symbol clock of the receiver (20).

This application provides a time synchronization packet processing method and apparatus. The method includes: A terminal device receives first indication information, where the first indication information indicates the terminal device to enter an activation state of time synchronization for a first clock source, or the first indication information indicates the terminal device to enter a deactivation state of time synchronization; and processes a time synchronization packet of the first clock source based on the first indication information. The clock synchronization packet is processed in different manners when the time synchronization of the first clock source is in the activation state and the deactivation state, so that the terminal device can perform processing in different manners when signaling indicates that the clock source is activated or deactivated. For example, when the first clock source is in the deactivation state, the terminal device does not need to perform processing that needs to be performed when the first clock source is in the activation state. Therefore, power consumption of a communication device is reduced, and performance of the communication device is improved.

A method for initializing a self-synchronizing coherent network Primary Reference Time Clock (cnPRTC) mesh includes: a self-synchronizing cnPRTC mesh is initialized during a start-up period; and a Universal Time Coordinated (UTC(k)) node connected to a selected cnPRTC node of the self-synchronizing cnPRTC mesh sets the selected cnPRTC node to a UTC(k) time provided by the UTC(k) node during the start-up period when a Global Navigation Satellite System (GNSS) system fails to provide the selected cnPRTC node with a GNSS time during the start-up period, wherein setting the selected cnPRTC node comprises directly inserting the UTC(k) time into a clock combiner module of the selected cnPRTC node, the inserted UTC(k) time replacing weighted times provided to the selected cnPRTC node by local time sources and remote time sources.

The present invention relates to a device for generating a high frequency clock 303, which comprises a controller 311, a first FLL or PLL control loop 323, a fixed frequency reference clock oscillator 1101, an input signal 308, a divider ratio calculator 1110 and a measuring device 509. The first FLL or PLL control loop 323 has a first divider 520. The fixed frequency reference clock oscillator 1101 generates a reference clock 306. The measuring device 509 measures the reference signal occasionally present in the input signal 308 and determines the associated effective measurement value 517. The divider 520 divides the high frequency clock 303 into the frequency of the divided high frequency clock 521 by a frequency division ratio and divides it into the auxiliary clock 1112 by a second frequency division ratio. The divider ratio calculator 1110 determines the measurement value of the auxiliary clock 1112 and compares the effective measurement value 517 with the measurement value of the auxiliary clock 1112, and thereby determines a ratio value reflecting the ratio and / or difference between the measurement value 517 and the measurement value of the auxiliary clock 1112. The frequency divider ratio calculator 1110 changes the target frequency dividing ratio 1111 of the first frequency divider 520 according to the deviation.

A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.

The invention relates to a frequency / phase lock detector for a clock and data recovery circuit. A circuit includes a phase and frequency detector circuit (102) to generate a first phase detection signal indicating whether a polarity of a first clock is the same as a polarity of a second clock when an edge of a data signal appears. The second clock is 90 degrees out of phase relative to the first clock. A lock detection circuit (137) determines, based on the first phase detection signal, that the third clock is one of a frequency and phase locked to the data signal, a frequency and quadrature locked to the data signal, and a non-frequency locked to the data signal.

A clock recovery circuit includes a clock detector configured to receive a serial data stream from a remote device over a reverse channel, wherein the serial data stream includes clock reference data, reverse channel data, or a combination of the clock reference data and the reverse channel data, and the clock detector configured to output a clock detect signal in response to detecting the clock reference data in the serial data stream; a phase lock loop including a first detector configured to receive the serial data stream and to detect phase and frequency; and a controller configured to receive the clock detect signal and to selectively enable the first detector based on the clock detect signal.

Examples of a receiver, a controller unit (e.g., for a receiver), and related methods (e.g., for a receiver) are provided. A receiver is provided that includes a tunable sample provider configured to provide samples of an input signal using tunable sample timing, a feedback path configured to provide a feedback signal to the tunable sample provider based on a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the tunable sample provider, and a replacement value provider configured to provide replacement sample timing information that replaces the sample timing information provided by the feedback path when the input signal does not satisfy predetermined requirements for feedback-based sample timing adjustment, wherein the replacement value provider is configured to provide the replacement sample timing information taking into account timing error information or a quantity derived from the timing error information over a longer period of time than a period of time taken into account by the loop filter for providing the sample timing information.

Exemplary embodiments of this disclosure relate to methods, apparatus, devices, and computer-readable storage media for communication. In some embodiments, a first protective frame to be transmitted in a slot within a first round belonging to a first block may be generated based on a block-based time structure or a hyperblock-based time structure, wherein the block-based time structure or the hyperblock-based time structure comprises a plurality of blocks, each block comprising a plurality of rounds, and each round comprising a plurality of slots, and the first protective frame is protected by a first nonce comprising identification information, a round index, and a block index associated with the first protective frame, wherein the round index is the index of the first round, and the block index is the index of the first block. In this way, security operations can be performed and the security of the communication can be ensured.

In some implementations, a node (510) may receive one or more communications (210), wherein the one or more communications include time information, and wherein the one or more communications are associated with a peer-to-peer network (205). The node (510) may identify (215) a primary node associated with the peer-to-peer network (205) based on an indicator included in a communication, from the one or more communications, that is associated with the primary node. The node (510) may synchronize (220) a time stored by the node based on time information included in the communication that is associated with the primary node. The node (510) may receive (230) an indication that the node has successfully joined the peer-to-peer network based on synchronizing the time to the time information. The node (510) may selectively update (320) the time stored by the node based on a reference time included in periodic data transfer communications that are associated with the primary node.

This document discloses an oscillator calibration structure and method. A short-range data link receiver includes: an edge detector configured to generate pulses on the edges of a data input; a first clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; a second clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; and a controller configured to alternate between the first and second clock data recovery paths to use one path to recover clock and data while calibrating the other path. The controller can switch paths whenever calibration of one path is complete. This can include starting calibration of the next path immediately after switching paths. Alternatively, power consumption can be reduced by delaying calibration of the next path after switching paths.

A clock and data recovery circuit includes a voltage-controlled oscillator (VCO), a frequency detector, and a control circuit. The VCO generates a clock signal based on a voltage signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a first rising control signal accordingly. The control circuit is coupled to the VCO and the frequency detector and adjusts the voltage signal based on the first rising control signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in a data recovery mode, and the frequency detector detects whether the frequency of the clock signal needs to be increased in the data recovery mode.

The present application discloses a data phase recovery method, system, device and storage medium for burst code stream, which includes: when it is detected that a data burst transmission occurs in the target counterpart device and the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by the transmission protocol, and when it is detected that the CDR completes data locking, decreasing the increased data transmission bandwidth. In the embodiment of the present application, by combining fast locking and slow tracking, the data transmission bandwidth is increased only within a preset time specified by the protocol, and the bandwidth is not continuously increased, so that the link stability is not significantly affected, and the locking time requirement is met while the link stability is met.

The present invention relates to a device (5) for synchronizing a symbol clock during data transmission and to a transmission system, the device comprising: an estimation component (30) and a symbol synchronizer (40), the estimation component (30) being configured to receive a first signal (S1) generated by the transmitter (10) and, on the basis of the first signal, to estimate a phase offset (POFF) and / or a frequency offset (FOFF) between a symbol clock of the transmitter (10), on the basis of which the first signal (S1) is generated, and a symbol clock of the receiver (S2), on the basis of which the first signal (S1) is evaluated in the receiver (20), the device (5) being configured to initialize the symbol synchronizer (40), which is designed as a feedback symbol synchronizer (40), on the basis of the estimated phase offset (POFF) and / or the estimated frequency offset (FOFF),and wherein the symbol synchronizer (40) is configured to receive a second signal (S2) generated by the transmitter (10) in order to generate, on the basis of the second signal (S2), an output signal (S0) representing symbols synchronized with the symbol clock of the receiver (20) that are transmitted within the second signal (S2).

The present invention relates, inter alia, to a method for compensating a systematic error in symbol clock synchronization between a transmitter (10) and a receiver (20), the method comprising: a step for receiving a first signal (S1) in the receiver (20), a step for determining an estimated initial phase offset (POFF1) between a symbol clock of the transmitter (10) and a symbol clock of the receiver (20) using the first signal (S1), a step for initializing a symbol synchronizer (40) of the receiver (20) based on the estimated initial phase offset (POFF1), a step for receiving a second signal (S2) in the receiver (20), a step for determining and storing a plurality of phase offset values ​​(µ(n)) based on a plurality of sample values ​​representing the second signal, by means of the initialized symbol synchronizer,a step for determining an approximated initial phase offset of the symbol clocks based on an approximation over the plurality of stored phase offset values ​​(µ(n)), a step for determining a compensation value representing a difference between the approximated initial phase offset (POFF2) and a phase offset based on the estimated initial phase offset (POFF1), and a step for calculating the compensation value (COMP) with a subsequently determined estimated initial phase offset.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

An optical receiver, configured to receive optical burst signals in a passive optical network, PON; wherein the optical receiver comprises a clock-and-data-recovery, CDR, circuitry configured to synchronise a reference clock signal with a received optical burst signal starting from a configurable initial clock phase, thereby obtaining a synchronised data signal and a synchronised clock phase; wherein the optical receiver further comprises a phase estimation circuitry configured to estimate a phase of a received optical burst signal with respect to the reference clock signal and wherein the optical receiver is further configured to: receive a first optical burst signal; determine a phase estimate correction; receive a second optical burst signal; and obtain a corrected phase estimate; and, synchronise the reference clock signal with the corrected phase estimate as the configurable initial clock phase.

Systems and methods for synchronizing with and decoding radio frequency signals are provided. In one aspect, a radio receiver includes an antenna configured to receive a radio frequency signal and digital signal processing circuitry configured to receive the radio frequency signal from the antenna and perform a first synchronization algorithm and a second synchronization algorithm on the radio frequency signal in parallel. The digital signal processing circuitry is further configured to determine which of the first synchronization algorithm and the second synchronization algorithm completes first and begin playback on the radio frequency signal based on synchronization with the radio frequency signal based on the determination of which of the first synchronization algorithm and the second synchronization algorithm completed first.

A phase determining method and an apparatus are provided, which are applied to the field of communication technologies, for example, applied to a UWB-based WPAN system, for example, an 802.15.4a protocol, an 802.15.4z protocol, or an 802.15.4ab protocol in 802.15 series protocols, and also applied to a sensing system. The method includes: A transmit end generates a first frame, and then sends the first frame. In this way, a receive end may receive the first frame, and determine phase information based on the first frame. The first frame may include a first CTS, the first CTS includes at least two segment groups, a time interval between adjacent segments in each segment group is a first time interval, and a time interval between adjacent segment groups is a second time interval. Coverage of the first frame is effectively improved.

A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.