5results about "Receiver initialisation" patented technology

Examples of a receiver, a controller unit (e.g., for a receiver), and related methods (e.g., for a receiver) are provided. A receiver is provided that includes a tunable sample provider configured to provide samples of an input signal using tunable sample timing, a feedback path configured to provide a feedback signal to the tunable sample provider based on a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the tunable sample provider, and a replacement value provider configured to provide replacement sample timing information that replaces the sample timing information provided by the feedback path when the input signal does not satisfy predetermined requirements for feedback-based sample timing adjustment, wherein the replacement value provider is configured to provide the replacement sample timing information taking into account timing error information or a quantity derived from the timing error information over a longer period of time than a period of time taken into account by the loop filter for providing the sample timing information.

Exemplary embodiments of this disclosure relate to methods, apparatus, devices, and computer-readable storage media for communication. In some embodiments, a first protective frame to be transmitted in a slot within a first round belonging to a first block may be generated based on a block-based time structure or a hyperblock-based time structure, wherein the block-based time structure or the hyperblock-based time structure comprises a plurality of blocks, each block comprising a plurality of rounds, and each round comprising a plurality of slots, and the first protective frame is protected by a first nonce comprising identification information, a round index, and a block index associated with the first protective frame, wherein the round index is the index of the first round, and the block index is the index of the first block. In this way, security operations can be performed and the security of the communication can be ensured.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

Provided is a transmitter adopting correlated signaling. The transmitter includes serializers and a phase interpolator configured to select a reference phase of a clock as any one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase, in which the phase selected using the second code is any one of 0°to 90°, and the differential clocks are used as synchronization clocks of each of the serializers.