28results about "Receiver initialisation" patented technology

A method includes that a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

According to a first aspect, a method for processing a time synchronization packet is provided, including: A terminal device receives a time synchronization packet of a first clock source from an external device; receiving first indication information from a network device, where the first indication information indicates the terminal device to enter a time synchronization activated state of the first clock source, or the first indication information indicates the terminal device to enter a time synchronization deactivated state of the first clock source; and processing the time synchronization packet of the first clock source based on the first indication information. When a clock source is activated and deactivated, the terminal device processes a time synchronization packet of the clock source in different manners, and signaling indicates whether the clock source is activated or deactivated. This can allow the terminal device to perform processing in different manners, reduce power consumption of a communications device, and improve performance of the communications device while ensuring a service requirement on time synchronization precision.

Systems include a receiver configured to detect signals corresponding to a stream of digital symbols, a signal demodulator coupled to the receiver and configured to process an incoming stream of digital symbols, and a computing device connected to the receiver and to the signal demodulator, and featuring a set of software instructions that, when executed by the computing device, causes the computing device to determine an estimated time delay associated with the stream of digital symbols, transmit control instructions to the signal demodulator to configure the signal demodulator according to the estimated time delay, and process at least a second subset of the stream of digital symbols using the configured signal demodulator.

A method of reducing the effects of variation in latency in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sublayer circuitry having a first clock in a first clock domain and physical medium attachment circuitry having a second clock in a second clock domain, comprising: during initial training of the link, determining a transmit latency value in a transmission direction from the first clock domain to the second clock domain; during initial training of the link, separately from determining the transmit latency value, determining a receive latency value in a reception direction from the second clock domain to the first clock domain; and using the transmit latency value and the receive latency value to calculate latency in data transfer between the first clock domain and the second clock domain after the initial training until a subsequent training.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

This application provides a time synchronization packet processing method and apparatus. The method includes: A terminal device receives first indication information, where the first indication information indicates the terminal device to enter an activation state of time synchronization for a first clock source, or the first indication information indicates the terminal device to enter a deactivation state of time synchronization; and processes a time synchronization packet of the first clock source based on the first indication information. The clock synchronization packet is processed in different manners when the time synchronization of the first clock source is in the activation state and the deactivation state, so that the terminal device can perform processing in different manners when signaling indicates that the clock source is activated or deactivated. For example, when the first clock source is in the deactivation state, the terminal device does not need to perform processing that needs to be performed when the first clock source is in the activation state. Therefore, power consumption of a communication device is reduced, and performance of the communication device is improved.

A method for initializing a self-synchronizing coherent network Primary Reference Time Clock (cnPRTC) mesh includes: a self-synchronizing cnPRTC mesh is initialized during a start-up period; and a Universal Time Coordinated (UTC(k)) node connected to a selected cnPRTC node of the self-synchronizing cnPRTC mesh sets the selected cnPRTC node to a UTC(k) time provided by the UTC(k) node during the start-up period when a Global Navigation Satellite System (GNSS) system fails to provide the selected cnPRTC node with a GNSS time during the start-up period, wherein setting the selected cnPRTC node comprises directly inserting the UTC(k) time into a clock combiner module of the selected cnPRTC node, the inserted UTC(k) time replacing weighted times provided to the selected cnPRTC node by local time sources and remote time sources.

Examples of a receiver, a controller unit (e.g., for a receiver), and related methods (e.g., for a receiver) are provided. A receiver is provided that includes a tunable sample provider configured to provide samples of an input signal using tunable sample timing, a feedback path configured to provide a feedback signal to the tunable sample provider based on a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the tunable sample provider, and a replacement value provider configured to provide replacement sample timing information that replaces the sample timing information provided by the feedback path when the input signal does not satisfy predetermined requirements for feedback-based sample timing adjustment, wherein the replacement value provider is configured to provide the replacement sample timing information taking into account timing error information or a quantity derived from the timing error information over a longer period of time than a period of time taken into account by the loop filter for providing the sample timing information.

Exemplary embodiments of this disclosure relate to methods, apparatus, devices, and computer-readable storage media for communication. In some embodiments, a first protective frame to be transmitted in a slot within a first round belonging to a first block may be generated based on a block-based time structure or a hyperblock-based time structure, wherein the block-based time structure or the hyperblock-based time structure comprises a plurality of blocks, each block comprising a plurality of rounds, and each round comprising a plurality of slots, and the first protective frame is protected by a first nonce comprising identification information, a round index, and a block index associated with the first protective frame, wherein the round index is the index of the first round, and the block index is the index of the first block. In this way, security operations can be performed and the security of the communication can be ensured.

This document discloses an oscillator calibration structure and method. A short-range data link receiver includes: an edge detector configured to generate pulses on the edges of a data input; a first clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; a second clock data recovery path coupled to the output of the edge detector for recovering clock and data from the output of the edge detector; and a controller configured to alternate between the first and second clock data recovery paths to use one path to recover clock and data while calibrating the other path. The controller can switch paths whenever calibration of one path is complete. This can include starting calibration of the next path immediately after switching paths. Alternatively, power consumption can be reduced by delaying calibration of the next path after switching paths.

A clock and data recovery circuit includes a voltage-controlled oscillator (VCO), a frequency detector, and a control circuit. The VCO generates a clock signal based on a voltage signal. The frequency detector detects whether the frequency of the clock signal needs to be increased based on multiple sampling results of the input data signal and generates a first rising control signal accordingly. The control circuit is coupled to the VCO and the frequency detector and adjusts the voltage signal based on the first rising control signal. After detecting that the frequency of the clock signal is locked, the clock and data recovery circuit operates in a data recovery mode, and the frequency detector detects whether the frequency of the clock signal needs to be increased in the data recovery mode.

The present application discloses a data phase recovery method, system, device and storage medium for burst code stream, which includes: when it is detected that a data burst transmission occurs in the target counterpart device and the data pause signal is in an invalid state, increasing the data transmission bandwidth until the CDR completes data locking within a preset time specified by the transmission protocol, and when it is detected that the CDR completes data locking, decreasing the increased data transmission bandwidth. In the embodiment of the present application, by combining fast locking and slow tracking, the data transmission bandwidth is increased only within a preset time specified by the protocol, and the bandwidth is not continuously increased, so that the link stability is not significantly affected, and the locking time requirement is met while the link stability is met.

An apparatus and method for a receiver configured to perform timing recovery decoupling feedforward equalizer (FFE) adaptation. The receiver apparatus may include an analog front-end (AFE) device coupled to a time-interleaving (TI) interface. The TI interface is coupled in a timing recovery feedback loop to an FFE equalizer, a digital signal processor (DSP), a delay-timing loop (DTL) device, and a clock device, with the clock device feeding back to the TI interface. The DSP has an additional path to the FFE equalizer, which in turn has an additional path to the DTL device. The DTL loop is equipped with an interleaving-specific enable / disable vector Q[1:N] that can enable / disable the contribution of specific time-interleaving errors to the timing recovery loop, allowing the FFE adaptation process to be decoupled from the timing recovery loop.

Systems and methods for synchronizing with and decoding radio frequency signals are provided. In one aspect, a radio receiver includes an antenna configured to receive a radio frequency signal and digital signal processing circuitry configured to receive the radio frequency signal from the antenna and perform a first synchronization algorithm and a second synchronization algorithm on the radio frequency signal in parallel. The digital signal processing circuitry is further configured to determine which of the first synchronization algorithm and the second synchronization algorithm completes first and begin playback on the radio frequency signal based on synchronization with the radio frequency signal based on the determination of which of the first synchronization algorithm and the second synchronization algorithm completed first.

A phase determining method and an apparatus are provided, which are applied to the field of communication technologies, for example, applied to a UWB-based WPAN system, for example, an 802.15.4a protocol, an 802.15.4z protocol, or an 802.15.4ab protocol in 802.15 series protocols, and also applied to a sensing system. The method includes: A transmit end generates a first frame, and then sends the first frame. In this way, a receive end may receive the first frame, and determine phase information based on the first frame. The first frame may include a first CTS, the first CTS includes at least two segment groups, a time interval between adjacent segments in each segment group is a first time interval, and a time interval between adjacent segment groups is a second time interval. Coverage of the first frame is effectively improved.

A method of reducing impact of variation in latency in data transport between clock domains of a physical layer transceiver having physical coding sublayer circuitry with a first clock in a first clock domain and physical medium attachment circuitry with a second clock in a second clock domain, includes determining, during an initial training of a link, a transmit latency value in a transmit direction from the first clock domain to the second clock domain, determining, during the initial training of the link, separately from determining the transmit latency value, a receive latency value in a receive direction from the second clock domain to the first clock domain, and using the transmit latency value and the receive latency value to account for latency in transfer of data between the first clock domain and the second clock domain following the initial training until a subsequent training.

Example embodiments of the present disclosure relate to methods, devices, apparatuses and a computer readable storage medium for communication. In some embodiments, a first secured frame to be transmitted in a slot in a first round belonging to a first block based on a block-based time structure or a hyper block-based time structure may be generated, where the block-based time structure or the hyper block-based time structure comprises a plurality of blocks, each block of the plurality of blocks comprises a plurality of rounds, each round of the plurality of rounds comprises a plurality of slots, the first secured frame is secured by a first nonce being constructed based on identifying information associated with the first secured frame, a round index and a block index, the round index is an index of the first round, and the block index is an index of the first block. As such, the security operation may be performed and the communication can be guaranteed to be secured.

A device and method for a receiver configured to perform timing recovery decoupled feed-forward equalizer (FFE) adaptation. The receiver device can include an analog front-end (AFE) device, which is coupled to a time-interleaved (TI) interface. The TI interface is coupled in a timing recovery feedback loop to FFE equalizers, a digital signal processor (DSP), a delay timing loop (DTL) device, and a clock device, which feeds back to the TI interface. The DSP has an additional pathway to the FFE equalizers, which has an additional pathway to the DTL device. The DTL loop is equipped with an interleave specific enable / disable vector Q[1:N] that can turn on / off the contribution of the specific time interleave errors to the timing recovery loop, which allows the FFE adaptation process to be decoupled from the timing recovery loop.

A phase determining method and an apparatus are provided, which are applied to the field of communication technologies, for example, applied to a UWB-based WPAN system, for example, an 802.15.4a protocol, an 802.15.4z protocol, or an 802.15.4ab protocol in 802.15 series protocols, and also applied to a sensing system. The method includes: A transmit end generates a first frame, and then sends the first frame. In this way, a receive end may receive the first frame, and determine phase information based on the first frame. The first frame may include a first CTS, the first CTS includes at least two segment groups, a time interval between adjacent segments in each segment group is a first time interval, and a time interval between adjacent segment groups is a second time interval. Coverage of the first frame is effectively improved.

The invention discloses a network system of a long-distance Ethernet and a related control method. In a physical layer circuit (PHY) of a network module, an ultra-long line transmit-receive specification is designed. In a network system, when both network modules support the ultra-long line transmit-receive specification, the ultra-long line transmit-receive specification can be selectively used for data exchange after an auto-negotiation process. In this embodiment, a unique hardware architecture is designed in physical layer circuitry (PHY) of a network module. When the two network modules of the network system both comprise the unique hardware architecture, the ultra-long line transceiving specification can be selectively used for data exchange after the auto-negotiation process.

The disclosure relates to a physical layer transceiver that reduces variations in packet latency. A method of reducing the effects of latency variations in data transfer between clock domains of a physical layer transceiver, the physical layer transceiver comprising physical coding sub-layer circuitry having a first clock in a first clock domain and physical media connection circuitry having a second clock in a second clock domain, comprising the steps of determining a transmission delay value in a transmission direction from a first clock domain to a second clock domain during an initial training period of a link; determining a receiving delay value in a receiving direction from the second clock domain to the first clock domain separately from the determined transmission delay value during the initial training period of the link; and using the transmission delay value and the reception delay value to calculate a delay in data transfer between the first clock domain and the second clock domain after the initial training until before the subsequent training.

Provided is a transmitter adopting correlated signaling. The transmitter includes serializers and a phase interpolator configured to select a reference phase of a clock as any one of 0°, 90°, 180°, and 270° using a first code, fine-tune the selected reference phase by adding a phase selected using a second code thereto, and generate differential clocks using the fine-tuned reference phase, in which the phase selected using the second code is any one of 0°to 90°, and the differential clocks are used as synchronization clocks of each of the serializers.

Embodiments of this application disclose a phase detection method, a phase detection circuit, and a clock recovery apparatus. The method includes: receiving a first signal, and deciding a (2M-1) level of the first signal to obtain a decision result, where the first signal is a (2M-1)-level signal, and M is a positive integer; obtaining a response amplitude parameter of a transmission channel; extracting clock phase information in the first signal based on the first signal, the decision result, and the response amplitude parameter; and determining output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods. According to the foregoing method, a stable phase detection gain can be achieved when a clock phase is tuned to a pulse response edge.

A clock and data recovery circuit is disclosed. The clock and data recovery circuit can include a clock recovery unit configured to output a recovered clock signal by operating a first time-to-digital conversion circuit or a second time-to-digital conversion circuit according to a phase difference between the recovered clock signal and a clock of an input signal, and a data recovery unit configured to sample data from the input signal and output recovered data.

In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.

Proposed is an apparatus for a digital clock and data recovery. The apparatus includes a frequency detector for detecting a high frequency (FH) signal, a low frequency (FL) signal and ultra-high frequency (FUH) signal by determining the relationship between an input data rate and a clock frequency, and generating a continuous frequency up (CFUP) signal and a continuous frequency down (CFDN) signal based on the FH, FL and FUH signals; and a digital loop filter (DLF) for controlling to adjust a clock frequency in a coarse adjustment stage using the CFUP and CFDN signals and to adjust a clock frequency in a fine adjustment stage using the FH and FL signals.

A network system for long reach Ethernet and an associated control method are provided. A long reach transceiving specification is additionally designed in the physical layer circuit of the network module in the network system. When two network modules in the network system support this long reach transceiving specification, the data transaction between the two network modules can be selectively implemented according to this long reach transceiving specification in the self-negotiation process. Furthermore, the physical layer circuit in the network module is equipped with a special hardware architecture. In case that both of the two network modules in the network system include the special hardware architecture, the data transaction between the two network modules can be selectively implemented according to this long reach transceiving specification in the self-negotiation process.