752results about "Channel dividing arrangements" patented technology

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

In a chip-to-chip communication system and apparatus, a set of physical signals to be conveyed over a communication bus is provided, and mapped to a codeword of a vector signaling code using the physical signals and a state information, wherein a codeword is representable as a vector of plurality of real-valued components, and wherein a vector signaling code is a set of codewords in which the components sum to zero and for which there is at least one component and at least three codewords having different values in that component; and wherein the state information is a plurality of information present in continuous or discrete form which may have been obtained from previous codewords transmitted over the communication bus.

A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver. The transmitter logic circuit may consist of a bank of multiplexers configured to transmit a selected one of two input signals to be transmitted through a lane. Similarly, the receiver logic circuit may comprises a bank of multiplexers configured to transmit a selected one of two input signals received from a lane. The unique lane identifiers symbols are preferably insensitive to binary inversion and are preferably 10-bit symbols compatible with an 8B/10B encoding scheme.

A method and a system for compensating for a permutation of L pairs of cable such that the compensation is localized in a trellis decoder of a receiver. The L pairs of cable correspond to L dimensions of a trellis code associated with the trellis decoder. The trellis code includes a plurality of code-subsets. The permutation of the L pairs of cable is determined. A plurality of sets of swap indicators based on the permutation of the L pairs of cable is generated. Each of the sets of swap indicators corresponds to one of the code-subsets. The code-subsets are remapped based on the corresponding sets of swap indicators.

A communication system that includes a supervisory node (e.g., a headend) and one or more remote nodes (e.g., cable modems). Packets are transmitted between the supervisory node and the one or more remote nodes via RF channels. A plurality of the RF channels are bonded, such that packets may be transmitted via any one or more of the RF channels that are bonded. Bonding may include higher-layer bonding and/or lower-layer bonding. In higher-layer bonding, the communication system further includes a forwarder and a plurality of edge modulators. Each edge modulator is connected to a different RF channel or group of RF channels. The forwarder determines to which edge modulator one or more packets or flows are to be transmitted. In lower-layer bonding, a packet is split into pieces. The pieces are assigned to respective RF channels that are associated with an edge modulator for transmission to a remote node.

A method and apparatus for wireless communication may provide a multi-link PDCP sublayer (710) in a radio network controller (702) capable of allocating PDCP PDUs among a plurality of RLC entities (712) for use in a multi -point HSDPA network. Some aspects of the disclosure address issues relating to out-of-order delivery of the PDCP PDUs to a UE (610), such as unnecessary retransmissions. That is, the disclosed multi-link PDCP (710) may be capable of distinguishing between sequence number gaps that are caused by physical layer transmission failures and those caused merely by skew.

A node configured to support multi-service with Flexible Ethernet (FlexE) includes circuitry configured to receive a client signal, wherein the client signal is different from a FlexE client; and circuitry configured to map the client signal into a FlexE shim. A method, implemented in a node, for supporting multi-service with Flexible Ethernet (FlexE) includes receiving a client signal, wherein the client signal is different from a FlexE client; and mapping the client signal into a FlexE shim.

A method for sending data from a transmit site to a receive site which includes dividing a transmit data stream having a first bit rate into multiple data streams with each of the multiple data streams having a bit rate which is lower than the first bit rate, transmitting each of the multiple data streams over a plurality of RF channels and recombining the multiple data streams at the receive site to provide a receive data stream having a bit rate equal to the first bit rate.

A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the of the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.

Apparatus and method for providing controlled Quality of Service over Ethernet-like links. Prioritised frames are allocated to transmission queues responsive to their priorities. Each queue has an associated subsidiary Ethernet MAC which transmits frames from its queue subject to a scheduler which selects from the set of MAC's according to a pre-determined algorithm. The multiple logical paths between corresponding pairs of transmitter and receiver subsidiary MAC's are preferably multiplexed over a single physical channel. If congestion occurs at the receiver, then Ethernet PAUSE frames may be sent back to the transmitter, directed to specific subsidiary MAC's-typically those with lower priority-to suspend transmission from the corresponding queue for a time period indicated in the PAUSE frame. In this way back pressure flow control may be applied selectively to so that large amounts of low priority traffic do not cause unnecessary delays to higher priority traffic.

A method for transmitting data using data packets includes dividing a data portion of the data packet into two or more data segments, each having a corresponding check portion. The data packet may also be communicated over two or more logical communication channels. The order of data portions in one communication channel may differ from the order of data portions in a second communication channel. Identical or different check portions may be assigned to respective data portions.

A physical layer device provides for synchronization of clocks in a communication network. A place holder for an alignment marker is inserted into a frame to be transmitted. Once the placeholder alignment marker is inserted into the frame, no additional data is added to the frame. Transmission of the frame including the placeholder alignment marker may also be delayed to allow data processing in subsequent blocks within a transmit block to complete prior to further processing of the frame including the placeholder alignment marker (e.g., timestamping, MACSec, etc.) to improve timing accuracy with a multi lane distribution environment.

A phase interpolator circuitry is composed of a delay line, and a phase blender circuit. The delay line delays a first input clock signal to develop a delayed clock signal. The phase blender circuit includes a first inverter receiving the delayed clock signal, and a second inverter receiving a second input clock signal phased away from the first input clock signal. The outputs of the first and second inverters are commonly coupled together. The phase interpolator circuitry additionally includes at least one of constant current sources: first one connected between a power terminal of the first inverter and a power supply, second one connected between a ground terminal of the first inverter and ground, third one connected between a power terminal of the second inverter and a power supply, and fourth one connected between a ground terminal of the second inverter and ground.

A high-speed communication interface manages a parallel bus having N bus lines. N+1 communication lines are established. A maintenance operation is performed on one of the N+1 communication lines, while N of the N+1 communication lines is available for data from the N line bus. The communication line on which the maintenance operation is performed, is changed after the operation is complete, so that all of the N+1 communication lines are periodically maintained, without interfering with communications on N of the N+1 communication lines.