121results about "Channel dividing arrangements" patented technology

The invention provides a 200GE service data transmission method based on 224G high-speed SerDes, a chip and a communication system, and the method comprises the steps that a PCS sending module carries out PCS sending processing on obtained upstream data to obtain first PCS data; the PCS sending module sends first PCS data to the PMA sending module through the rate increasing module according to the first PCS clock rate and the first PCS data bit width; the rate increasing module determines first clock information according to the first PMA data bit width, the first PMA clock rate, the first PCS clock rate, the first PCS data bit width and the set bandwidth so as to increase the first PCS clock rate; the PCS sending module sends first PCS data according to the first PMA data bit width and the improved first PCS clock rate; the PMA sending module processes the first PCS data and sends the first serial data. The method can be applied to the fields of internet access and related services, the alignment mark insertion process is avoided so as to improve the sending rate of the PCS layer, and the PMA state frame is introduced so as to accelerate link convergence and improve link stability.

A wireless communication protocol which operates with multi-link devices (MLDs) having simultaneous transmit and receive (STR) link pairs to allow transmitting a long MU PPDU by an originator on a first link, which is acknowledged (Ack) by a recipient on a second link. The Ack on the second link may be on a single resource unit (RU) which may be shared by multiple stations. The Ack may be received during the MP PPDU on the first link, making it a quick Ack. In many cases this allows the originator to perform a retransmission within the same PPDU, thus especially benefitting real-time traffic which is latency sensitive.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

Systems and methods are disclosed for phase calibration between clock and data lanes at a data link receiver. In calibration mode, matching signals are transmitted over the clock and data lanes, and a phase offset is measured at the receiver. A phase shifter in one signal path is adjusted to a first phase to obtain a desired phase offset. For operation mode, the phase shifter is set based on the first phase. Embodiments measure phase offset using an XOR gate and use a phase interpolator as the phase shifter. Embodiments with multiple data lanes apply coarse calibration to a shared clock lane relative to a first data lane, and similar fine calibration to other data lanes. Calibration provides optimum signal-to-noise ratio or timing margin, enabling high transmission speeds at relatively low power. Variations are disclosed.

A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.

Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti-aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.

Frequency error tracking and lane monitoring techniques for multi-lane optical transceivers are provided. In one aspect, a method includes capturing phase and frequency information recovered by clock-and-data recovery circuits from data traveling along a plurality of lanes of an optical transceiver, with one of the lanes being a master lane; determining a frequency error based on the phase and frequency information of the master lane; outputting, by a tunable oscillator, a reference clock based on the frequency error; and controlling the optical transceiver based on i) a transmitter clock signal generated by a transmitter phase-locked loop (PLL) using the reference clock signal, and ii) a receiver clock signal generated by a receiver PLL using the reference clock signal.

A communication interface at a first end of a communication link includes a plurality of communication lanes. The communication interface includes logic to cooperate with another communication interface at a second end of the communication link to send data through the communication lanes to the second end. The logic is to store a communication lane state of a wake-up communication lane and, when detecting that the communication lane state of the wake-up communication lane changes to a first determined state, the logic is to stop sending data through the wake-up communication lane, change a sleep communication lane to a new wake-up communication lane, and notify the communication interface at the second end. The communication interface provides seamless and asymmetric data communication between the first and second ends of the communication link even in the event of a lane failure.

Disclosed are an encoding method, a decoding method, and related devices designed to independently encode each of z second data streams without performing operations such as de-skewing and reordering, thereby reducing operational complexity and latency. The encoding method includes: obtaining m first data streams through m input channels, where m is a positive integer; processing the m first data streams to obtain z second data streams, where z is a positive integer; independently encoding each of the z second data streams to obtain z third data streams; and multiplexing the z third data streams to obtain n fourth data streams, where n is a positive integer.

An apparatus (100) for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit (130) receiving an input signal from a signal path mixed with interference from a clock path. The apparatus (100) includes a phase interpolator circuit (120) implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit (140) to sample the input signal and the interference in every cycle. The apparatus (100) also includes an analog-to-digital converter (150) configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

The application provides a 200GE service data transmission method, a chip and a communication system based on a 224G high-speed SerDes, and the method comprises the following steps: a PCS sending module performs PCS sending processing on upstream data obtained, to obtain first PCS data; the PCS sending module sends the first PCS data to a PMA sending module according to a first PCS clock rate and a first PCS data bit width; a rate improvement module determines first clock information according to a first PMA data bit width, a first PMA clock rate, the first PCS clock rate, the first PCS data bit width and a set bandwidth, to improve the first PCS clock rate; the PCS sending module sends the first PCS data according to the first PMA data bit width and the improved first PCS clock rate; and the PMA sending module processes the first PCS data and sends first serial data. The application can be applied to the field of internet access and related services, avoids the alignment mark insertion process to improve the sending rate of the PCS layer, and accelerates link convergence and improves link stability by introducing a PMA state frame.

Embodiments herein describe on-demand packetization where data (115) that is too large to be converted directly into data words (DWs) (130) for a chip-to-chip (C2C) interface (140) are packetized instead. When identifying a protocol word (115) that is larger than the DW (130) of the C2C interface (140), a protocol layer (120a) can perform packetization where a plurality of protocol words (115) are packetized and sent as a transfer. In one embodiment, the protocol layer (120a) removes some or all of the control data or signals in the protocol words (120a) so that the protocol words no longer exceed the size of the DW (130). These shortened protocol words (115) can then be mapped to DWs (130) and transmitted as separate packets on the C2C (140). The protocol layer (120a) can then collect the portion of the control data that was removed from the protocol words (115) and transmit this data as a separate packet on the C2C interface (140).

A system includes a transmitter device and a receive device coupled to a link having data lanes. The receiver device includes training logic. Each of the plurality of data lanes is to receive, from the transmitter device, an incoming data stream having the same pattern repeated over the plurality of clock cycles, and the training logic is to shift the incoming data stream one unit interval (UI) at a time until a shifted data pattern matches an expected data pattern on each data lane. Each of the plurality of data lanes is to receive, from the transmitter device, a count value at every clock cycle, and the training logic is to shift one or more burst lengths (BLs) until each data lane receives a same count value, thereby synchronizing the data lanes to a common frame boundary.

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

An encoding method includes: obtaining m lanes of first data streams through m input lanes, where m is a positive integer; processing the m lanes of first data streams to obtain z lanes of second data streams, where z is a positive integer; separately performing encoding processing on each of the z lanes of second data streams to obtain z lanes of third data streams; and performing multiplex processing on the z lanes of third data streams to obtain n lanes of fourth data streams, where n is a positive integer.

Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti¬ aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.

Systems and methods for reducing a number of comparators used during an alignment marker (AM) search are presented. A method includes enabling communication between a physical coding sublayer (PCS) having a PCS transmit side and a PCS receive side with a physical medium attachment (PMA) sublayer, at a first end, using multiple PCS lanes that receives data blocks from the multiple PCS lanes, wherein a PCS lane includes an alignment marker (AM) on the PCS transmit side and performs an AM search using a first AM search stage circuit, wherein, in the first AM search stage circuit, all of the multiple PCS lanes are consecutively searched with read components on the PCS receive side until an AM is detected in all of the multiple PCS lanes.

Systems including a first circuit and a second circuit, with a multi-data lane link between the first circuit and the second circuit. The first circuit and the second circuit are configured to determine a delay setting of a clock signal forwarded from the first circuit to the second circuit by utilizing a first distinct subset of the data lanes to communicate commands redundantly encoded in multiple unit intervals of the data lanes and by utilizing a second distinct subset of the data lanes to communicate results of the commands.

An encoding method, a decoding method and related apparatus are disclosed for separately performing an encoding process on each of the second data streams of z lanes without performing operations such as deskewing and reordering, which reduces operational complexity and delay. The encoding method includes the steps of obtaining a first data stream of m lanes through m input lanes, where m is a positive integer, processing the first data stream of m lanes to obtain a second data stream of z lanes, where z is a positive integer, separately performing an encoding process on each of the second data streams of z lanes to obtain a third data stream of z lanes, and performing a multiplexing process on the third data stream of z lanes to obtain a fourth data stream of n lanes, where n is a positive integer.

There is provided a reception device including a data signal receiver circuit, a clock signal receiver circuit, and a discrimination circuit. The data signal receiver circuit receives a data signal through a data signal line, and receives a data blanking signal through the data signal line in a blanking period of the data signal. The clock signal receiver circuit receives a clock signal and a clock blanking signal through a clock signal line, the clock blanking signal outputted in synchronization with the blanking period of the data signal. The discrimination circuit discriminates communication modes on a basis of one or both of a signal value of the data blanking signal and a signal value of the clock blanking signal.

A wireless communication protocol that operates on a multilink device (MLD) with simultaneous transmit / receive (STR) link pairs and allows an originator to transmit a long MU PPDU on the first link and a receiver to acknowledge (Ack) on the second link. The Ack on the second link can reside on a single resource unit (RU) that can be shared by multiple stations. The Ack can be received during an MP PPDU on the first link, which is a quick Ack. In many cases, this allows the originator to perform a retransmission within the same PPDU, which benefits latency-sensitive real-time traffic in particular.

A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter (S502), receiving an UNBOND set by a receiver (S504), waking up a second transmitter by a LASM when the receiver receives the UNBOND set (S506), transmitting a training sequence by the second transmitter (S508), transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence (S510), determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block (S512), stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block (S514), and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter (S516).

Systems, methods, apparatuses, and computer program products for reducing data port downtime are provided. An example network interface device of the present disclosure includes a first data port and a second data port. The network interface device performs a first link training process associated with the first data port coupled to a first communication link to determine a first communication parameter set for the first communication link. The network interface device then deactivates the first data port and performs a second link training process associated the second data port coupled to a second communication link to determine a second communication parameter set. Based on a network usage parameter set associated with a data plane of the network interface device, the network interface device determines whether to activate the first data port concurrently with the second data port.

A signaling link retimer injects flow-rate compensation transmissions into a synthesized symbol stream in coordination with flow-rate compensation transmissions detected within a received symbol stream, enabling the retimer to switch seamlessly between forwarding the received symbol stream and outputting the synthesized symbol stream.

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

This application discloses a link monitoring method and apparatus, which belongs to the field of data transmission technology. The method includes: receiving outer code encoded data; performing inner code encoding on the outer code encoded data and outputting inner code encoded data; performing outer code decoding on the outer code encoded data; and determining the link quality for transmitting the outer code encoded data based on the status of performing outer code decoding on the outer code encoded data. This application can effectively monitor the link quality.

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.

To provide a method and an apparatus for clock recovery of communication via a multi-wire, multi-phase interface.SOLUTION: The method includes generating a combinational signal that includes transition pulses. Each transition pulse is generated in response to a transition in a differential signal that represents a difference in the signaling state of a pair of wires in a three-wire bus. The method also provides a logic circuit with the combinational signal. The logic circuit provides a clock signal as its output. Here, a pulse in the combinational signal causes the clock signal to be driven to a first state. The method further receives a reset signal derived from the clock signal by the logic circuit delaying the transition to the first state and passing the transition from the first state without any additional delay. The clock signal is driven from the first state after passing the transition of the clock signal to the first state.SELECTED DRAWING: Figure 20

Disclosed are a multi-lane synchronization method and apparatus. The method includes: forming N data frames, frame headers of the N data frames including an identical frame header sequence, N being greater than or equal to 1 and less than or equal to the number of lanes M, and M being an integer not less than 2; and sending the N data frames via N lanes, wherein different data frames are sent via different lanes, and the frame header sequence is configured to perform frame synchronization between a receiving end and a sending end or to check frame synchronization. Also disclosed are a synchronization system and a computer storage medium.