11results about "Channel dividing arrangements" patented technology

Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti-aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.

Alignment detection circuitry is disclosed that include a buffer configured to output a data stream of multiplexed groups of symbols from multiple data lanes and a set of correlators configured to determine physical link skew from one data lane of the multiple data lanes, wherein the physical link skew from the one data lane is known to equal the physical link skew on each data lane, assuming each data lane is transmitted over the same physical link. The alignment detection circuitry may also include anti¬ aliasing circuitry configured to extract a unique marker of the alignment marker to detect common marker aliasing by comparing the extracted unique marker to a known unique marker. Anti-aliasing circuitry may also be configured to use common marker detection status of adjacent data lanes of the multiple data lanes to detect common marker aliasing determined by a detection delay between the adjacent data lanes.

A method for link transition in a USB device includes transmitting a plurality of first RS-FEC blocks by a first transmitter (S502), receiving an UNBOND set by a receiver (S504), waking up a second transmitter by a LASM when the receiver receives the UNBOND set (S506), transmitting a training sequence by the second transmitter (S508), transmitting a specific pattern sequence by the second transmitter after finishing transmitting the training sequence (S510), determining whether a current RS-FEC block to be transmitted by the first transmitter is a DESKEW block (S512), stopping transmitting the specific pattern sequence if the current RS-FEC block is determined to be the DESKEW block (S514), and transmitting a plurality of second RS-FEC blocks by the first transmitter and the second transmitter (S516).

An apparatus for canceling clock-to-signal interference in a multi-lane SerDes comprising an analog front-end circuit receiving an input signal from a signal path mixed with interference from a clock path. The apparatus includes a phase interpolator circuit implemented in the clock path to generate multiple phases of a clock signal and to provide a timing rotated by the phases for a track-and-hold circuit to sample the input signal and the interference in every cycle. The apparatus also includes an analog-to-digital converter configured to digitize the input signal and the interference to provide an ADC output and a digital-interference-cancellation circuit configured to demultiplex the ADC output and detect a baseline offset associated with the interference sampled at one of the phases in each demultiplexed path using a digital loop to calibrate the baseline offset.

An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

To provide a deskewing method for a physical layer interface on a multi-chip module.SOLUTION: A circuit connected to a plurality of communication lanes is configured to: train each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window 1505; in response to determining that all of the lanes have an incorrect symbol alignment 1515 / none, symbol-rotate each lane by a single step 1520; in response to determining that some but not all of the lanes have a correct symbol alignment 1515 / some, symbol-rotate lanes which have an incorrect symbol alignment by a single step 1525; when the end of the timing window has been reached 1530 / yes, symbol-rotate lanes which have a correct symbol alignment and adjust a phase of a corresponding global clock to compensate for wrong symbol rotations 1535.SELECTED DRAWING: Figure 15

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

Aspects relate to mechanisms for detecting a voltage level (414) on a data communication interface (404) between a slave device (402) and a host device. Based on the detected voltage level (414), the slave device (402) may respond to the host device on the data communication interface (404) at the detected voltage level. In some examples, the slave device (402) may include a circuit configured to toggle between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to the detected voltage level on the data communication interface (404).

A network transceiver device is provided, including at least two variable gain amplifiers (VGAs), and at least two sets of analog digital converters (ADCs), each set including ADCs coupled to an output of one of the VGAs, the sets being arranged in VGA-specific channels. The device includes a plurality of feed-forward equalizers (FFEs), each FFE being coupled to receive an output of one of the ADCs in one of the VGA-specific channels. Each FFE is configured to adaptively equalize the output received from the ADCs utilizing a first equalization coefficient subset with coefficient values that are common to all FFEs, and a second equalization coefficient subset that is channel specific and that has a first set of coefficient values for a first VGA-specific channel and a second set of coefficient values for a second VGA-specific channel, the sets of coefficient values being computed independently.