32 results about "8b/10b encoding" patented technology

A multi-lane link that automatically detects if the lanes in the link have been reordered and corrects the order of the lanes. In one embodiment, the link includes a transmitter and a receiver. The receiver is configured to receive a plurality of lanes and includes a receiver logic circuit configured to receive signals from each of the plurality of lanes. Lane misordering is corrected during a training sequence in which a first training sequence and a second training sequence are bilaterally transmitted between the transmitter and receiver. The receiver monitors the training sequence for symbols that are unique to each lane and if an unexpected symbol is detected in the lane, the receiver logic circuit will correct the order of the lanes. The link further comprises a transmitter logic circuit configured to transmit signals to the lanes. The transmitter logic circuit is configured to reorder the sequence of the signals transmitted to the lanes if the transmitter does not detect a response from the receiver. The transmitter logic circuit may consist of a bank of multiplexers configured to transmit a selected one of two input signals to be transmitted through a lane. Similarly, the receiver logic circuit may comprises a bank of multiplexers configured to transmit a selected one of two input signals received from a lane. The unique lane identifiers symbols are preferably insensitive to binary inversion and are preferably 10-bit symbols compatible with an 8B/10B encoding scheme.

Two types of codings are integrated, instead of performing each coding independently. The two codings may be integrated by interleaving one or more acts of one coding method (e.g. data coding) between two or more acts of the other coding method (e.g. line coding). In some embodiments, partitioning of a block of data (e.g. a byte) for line coding (e.g. DC balance coding) is done prior to data coding (e.g. error correction coding). In such embodiments, the remaining acts of line coding may be performed after the data coding is completed. In one particular embodiment, an 8 bit byte is not directly used in error correction coding and instead, the 8 bit byte is initially partitioned into two sub-blocks (of 3 bits and 5 bits) as required by 8B/10B encoding (which is an example of line coding). After partitioning, the 8B/10B encoding is not continued, and instead Reed Solomon coding (which is an example of data coding) is then performed (to completion) on the individual sub-blocks (of 3 bits and 5 bits). The error correction coded sub-blocks (of 3 bits and 5 bits) are then used for the remainder of 8B/10B encoding.

A bus interface for transfer of SONET/SDH data that supports a plurality of SONET/SDH flows. The invention supports two line coding schemes: 8B/10B encoding of STS-12, and SONET scrambled coding for STS-12, STS-48, and STS-51. The invention additionally supports two modes of line testing: entire links can be tested by inserting and checking PRBS sequences, and the SPE payload of the largest concatenated STS-Nc which the link can carry (STS-12c, STS-48c, STS-51c) can be individually tested by inserting and checking PRBS sequences.

The invention discloses a fault simulation device of a fiber channel avionics environment (FC-AE)-1533 device, which relates to the fault simulation device. In order to simulate a fault of the FC-AE-1533 device so as to detect the fault of the FC-AE-1533 device, a Qsys system is built inside a programmable logic device. An NIOSII processor in the Qsys system is used for transmitting a control command to an optical fibre interface module; a PCIe module is used for receiving the fault injected from a fault simulation host computer and carrying out data interaction with the simulation host computer, and the optical fibre interface module is used for carrying out 8B/10B encoding and transmitting on the data, transmitting the injected fault, and carrying out decoding and CRC (cyclic redundancy check) on the received data. The fault simulation device of the FC-AE-1533 device disclosed by the invention can be widely applied to an avionic device, a fighter plane, a civil airplane, naval vessels and other occasions with the device meeting the FC-AE-1533 protocol, and can carry out the work such as maintaining, testing, fault overhauling and the like on the product.

The invention discloses a design method of a field bus optical fiber communication interface. The method includes: operations interfaces provided to a data link layer are two asynchronous FIFOs, and the two asynchronous FIFOs are a transmitting FIFO and a receiving FIFO; the number of 0 and 1 in the data of the transmitting FIFO is balanced after the data is subjected to 8b/10b encoding, and the high-speed serial data stream, after parallel-serial conversion, of the encoded 10bit parallel data is transmitted through an optical transceiver to complete a data transmitting function; the serial data oversampling module of a receiving part samples the received serial data and performs data recovery, the recovered data is transmitted to a word alignment and data monitoring module to obtain aligned 10bit data, a 8b/10b decoding module is used to recover the 10bit data into 8bit data, and the data is written to the asynchronous receiving FIFO through a receiving control module to complete a data receiving function.

The invention relates to an FC-EG gateway and a communication conversion method between an optical fiber channel and the Ethernet. The FC-EG gateway comprises an Ethernet universal interface module, an FC universal interface module and a protocol conversion module. The Ethernet universal interface module is used for packaging and analyzing an Ethernet frame header and realizing the conversion of a physical layer and a data link layer; the FC universal interface module is used for performing photovoltaic conversion, electro-optical conversion, 8B/10B encoding and decoding, and packaging and analyzing of a universal frame header; and the protocol conversion module is used for converting an IPFC sequence and an IP message. The invention further discloses a communication conversion method between the optical fiber channel and the Ethernet by utilizing the FC-EG gateway. By means of the design of the FC-EG gateway, heterogeneous network IP fusion communication based on the Ethernet and the optical fiber channel is realized, so that the IP message in the ordinary Ethernet can access the FC network through the FC-EG gateway.

The invention discloses a selected output device of a packaging multiplexing code stream, which comprises an encoding/decoding unit and a processing unit, wherein the encoding/decoding unit is connected with the processing unit and is used for conducting 8b/10b decoding on input asynchronous serial code streams, resolving out a plurality of paths of packaging multiplexing code streams and conducting abnormality test on 16 bytes of package header information in 188 bytes of the packaging multiplexing code streams; multiplexing frames analyzed by the processing unit are received and packaged into a packaging multiplexing code stream with 188 bytes for 8b/10b encoding, then the encoded stream is sent to an asynchronous serial output interface, or the path of the packaging multiplexing code stream with the optimal quality is selected for being directly sent to the asynchronous serial output interface; and the processing unit is connected with the encoding/decoding unit and used for gradingfor analysis of all paths of multiplexing frames and quality of service. The invention also discloses a selected output method of packaging multiplexing code stream. The invention realizes the selected output of multiple paths of PMS code streams, and reduces the possibility of interruption of service of backward-stage equipment.

A system and method of transmitting client data encoded according to an 8B/10B encoding between a client side and an optical communication network side, including inserting padding signals in an amount corresponding to a rate difference between a clock on the client side and a clock in the optical transmission device and controlling a clock to be used as a reference in transmitting the client data to synchronize with a clock having been used as a reference in transmitting the client data on the basis of a ratio of padding signals having been inserted in the client data.

An optical transmitter of a subscriber optical interface and an optical receiver of a laser transceiver node can be designed to a frequency of data that is formatted according to a predetermined network protocol, that is encoded with a predetermined coding scheme, and that is transmitted according to a predetermined data transmit timing scheme. The frequency of data is an occupied frequency of a protocol when the data comprises a maximum number of like bits permitted by the protocol. An optical transmitter and optical receiver can be designed to a lowest occupied frequency of data that is encoded with 8B/10B encoding, and that is propagated upstream according to time division multiple access (TDMA). In this way, upstream optical communications can be maximized for speed.

The invention discloses a new 8b/10b encoding implementation method. The contents provided by the invention is to simply a 8b/10b encoding table through the discovered rule to provide a new 8b/10b encoding implementation scheme according to the simplified encoding table. The implementation process of the scheme provided by the invention comprises: inputting 8 bit code words, K codes, polar indication, performing 4b/6b and 3b/4b encoding and low-four-bit statistics, selecting 4b/6b and 3b/4b encoding results, selecting polarity, and outputting a 10bit encoding result and the polar indication. The 4b/6bn encoding is implemented by simplifying 5b/6b encoding by using the rule 1 in the invention; and code word classification in the rule 2 is realized by the low-four-bit statistics; and in the selecting 4b/6b and 3b/4b encoding results and selecting polarity, and bitwise processing is carried out on the 4b/6b and 3b/4b encoding results according to the rule 2. Compared with the traditional blocked implementation scheme of 5b/6b encoding and 3b/4b encoding, the scheme in the invention not only simplifies the implementation scale of the circuit, but also reduces the delay from input to output to a certain extent, and reinforce the efficiency and instantaneity of encoding.

The invention relates to a high-speed 8B/10B encoding device which is characterized by comprising a special signal determining module, a 5B/6B lookup table, a 5B/6B operating sign, a 3B/4B lookup table, a 3B/4B operating character, a special character coder and an output producing module. According to the high-speed 8B/10B encoding device, a basic lookup table can be constructed and operations of lookup table results can be previously ensured so as to quickly achieve a high-speed coder on the base that a designer needs not to deep understand an 8B/10B encoding principle.

During decoding and encoding, the starting disparity of a current block is computed by using a disparity at some previous reference point and disparity characteristics of bytes from the reference point to a current block boundary. The characteristics of the bytes are whether the bytes are unbalanced coded vectors and whether the number of unbalanced vectors is even or odd. Alternately, the characteristics of the bytes are whether the bytes are balanced and how many balanced coded vectors exist. New classifications are created for encoding and decoding 3B/4B and 5B/6B transmission codes. Separate functions are created that address specifically disparity aspects. A dispartiy violation at the front of a byte is detected during decoding by comparing a required front-end disparity of the byte with the actual running disparity by assuming the actual running disparity is equivalent to an exit disparity of the next preceding byte that is disparity dependent.

The invention relates to a television signal transmitter combining wired television transmission and network television transmission. The television signal transmitter comprises a digital voice signal acquisition module, a digital video signal acquisition module, an additional data acquisition module, a packing and multiplexing module, a 8B/10B encoding module, a synchronous character insertion module, a serial-parallel conversion module, an asynchronous serial interface (ASI) processing module, an IP (Internet Protocol) packing module, a UDP (User Datagram Protocol) packing module and a conversion control module, wherein the packing and multiplexing module is connected with the digital voice signal acquisition module, the digital video signal acquisition module and the additional data acquisition module to be respectively used for receiving compressed voice data, compressed video data and encoded additional data, packing and multiplexing the data and processing the packed and multiplexed data under the control of the conversion control module so as to obtain wired television signals or network television signals. Through the invention, the functions of the transmitter can be expanded, and wired television signal transmission and network television signal transmission are combined.

Disclosed herein is a signal transmitting device including a multiplexing section configured to generate a B/R ch by alternately multiplexing image signals read from B pixels and R pixels among image signals read and input in units of a predetermined number of samples in each of the first line and the second line from said image pickup element in an active region corresponding to a C ch in HD-SDI together with start code of one of SAV and EAV, and generate a G ch by multiplexing, in order, image signals read from G pixels in an active region corresponding to a Y ch in HD-SDI together with said start code; and an 8B/10B encoder configured to output serial digital data converted by 8B/10B-encoding the active regions on the B/R ch and the G ch having data structures corresponding to said HD-SDI and an auxiliary data region including SAV, EAV, LN, and CRCC.

Existing message fields and/or message parameters are configured to facilitate the packet and message synchronization and decoding tasks that conventionally rely upon a known bit sequence in each packet, thereby eliminating the need for a predefined message preamble in each packet. In example embodiments, the unique identifier of each transmitter is structured to facilitate determination of bit polarity and the start of each packet; packet sequence numbers use an unconventional counting sequence to assure synchronizing bit transitions; and so on. Other techniques, such as the use of run-length limited (RLL) message encoding, or 8b/10b encoding, to assure within-packet bit transitions, are also used to enhance clock synchronization and proper header location determination.

The invention discloses a device and a method for interconverting 8B/10B codes and 64B/66B codes. The system comprises an 8-to-64 module and a 64-to-8 module, for the 8-to-64 module, the data receivedby 8 channels is decoded to obtain 8 groups of 8-bit data, the 8 groups of 8-bit data is packaged into a group of 64-bit data, 64B/6B encoding is performed on the 64-bit data, and high-speed transmission is performed to realize conversion from 8B/10B codes to 64B/66B codes; for the 64-to-8 module, data received from a sending end is decoded and restored into 8-bit data of 8 groups of corresponding channels, 8B/10B encoding is carried out, then transmission is carried out, and 64B/66B codes are converted into 8B/10B codes. According to the invention, the use amount of optical fibers and the laying cost of the optical fibers are greatly reduced, the 1.25 Gbps rate of PON port data transmission can be improved to 10Gbps rate through 64B/6B codes, and the long-distance transmission speed is greatly improved.