30results about How to "Small circuit" patented technology

An apparatus and method for acquiring an image of a patterned object such as a fingerprint including a light refracting device, a focusing lens, a light source, and a biometric circuit for detecting the presence of a patterned object such as a fingerprint at the light refracting device. Incident light from the light source is projected through a light receiving surface of the light refracting device and is directly reflected off an imaging surface. The resulting image is projected through the focusing lens. The focusing lens has a diameter which is larger than the projection of the patterned object through the light refracting device.

A transformer 21 includes charging secondary winding lines 24 that can charge batteries 11 composing a corresponding cell block, and a discharging secondary winding line 26 that can discharge the corresponding cell block. Each of the charging secondary winding lines 24 is connected to corresponding one of the batteries 11 through corresponding one of secondary-side rectification output circuits 25 and corresponding one of output control switches 22. The discharging secondary winding line 26 is connected to a block discharging circuit through a block discharging switch 28. A switching control circuit 23 controls the block discharging switch 28. The switching control circuit 23 controls the output control switches 22 so that the electrical properties of the batteries 11 in the cell block are equalized. In addition, the switching control circuits 23 control the block discharging switches 28 so that the electrical properties of the batteries among the cell blocks are equalized.

Two types of codings are integrated, instead of performing each coding independently. The two codings may be integrated by interleaving one or more acts of one coding method (e.g. data coding) between two or more acts of the other coding method (e.g. line coding). In some embodiments, partitioning of a block of data (e.g. a byte) for line coding (e.g. DC balance coding) is done prior to data coding (e.g. error correction coding). In such embodiments, the remaining acts of line coding may be performed after the data coding is completed. In one particular embodiment, an 8 bit byte is not directly used in error correction coding and instead, the 8 bit byte is initially partitioned into two sub-blocks (of 3 bits and 5 bits) as required by 8B/10B encoding (which is an example of line coding). After partitioning, the 8B/10B encoding is not continued, and instead Reed Solomon coding (which is an example of data coding) is then performed (to completion) on the individual sub-blocks (of 3 bits and 5 bits). The error correction coded sub-blocks (of 3 bits and 5 bits) are then used for the remainder of 8B/10B encoding.

A cache memory 2 includes error bits corresponding to each line of data. An error detecting circuit uses these error bits 12, 14, 16, 18 to detect if a soft error has occurred within the data of a cache line. If such an error has occurred, then the line may be refilled from the main memory or some other action taken, such as a write back or generation of a soft error abort signal.

A packet network interface apparatus includes a media access control (MAC) module for constructing a packet for transmission over a packet network and a physical coding sublayer (PCS) module for encoding the packet for transmission over a physical interface. An inter packet gap module located between the MAC module and the PCS module directly transfers data to the PCS module while maintaining a certain inter packet gap by deleting or inserting idle characters. The inter packet gap module has at least one memory module for temporary storage of packet data. The modules preferably operate in a common time domain.

A method and apparatus is provided for passing an N bit wide data stream between two physical devices at high speed while maintaining the coherency of the data streams during the transfer. The N bit wide data stream is transmitted in N parallel data streams on N of N+1 differential data lines. A predetermined serial sync detect pattern is transferred on the remaining differential data line, which is designated as the sync line. A sub interval clock phase is then determined for the sync line that will successfully extract the transmitted sync detect pattern during each half cycle of the clock. This sub interval clock phase compensates for differing delays in the data streams across the physical interface. All of the N+1 differential data lines are in turn designated as the sync line to determine a sub interval clock phase for each of the respective differential data lines. Data is then extracted from the N data streams by sampling at the sub interval clock phase determined for each particular data line. The number of clock cycles that pass between reception of the sync detect pattern on the sync line and reception of the sync detect pattern on the next data line designated as the sync line is counted. The counted number of clock cycles is then compared to a predetermined number of clock cycles that pass between transmission of the sync detect pattern on the respective lines to determine if any data skew of multiple clock cycles is present between the respective lines. Any detected data skew is corrected. Thus, the present invention provides an improved method and apparatus for transmitting continuous parallel data streams while the bits in the data streams maintain their relative positions when received.

To perform a product-sum operation by adding third data to a product of first data and second data, a floating point multiplier first multiplies the first data by the second data, and a bit string representing a fixed-point part in the multiplication result is divided into a portion representing more significant digits in the fixed-point part and a portion representing less significant digits in the fixed-point part. Then, a floating point adder first adds less significant multiplication result data having a bit string representing the less significant digits as a fixed-point part to the third data, and then adds the addition result to more significant multiplication result data having a bit string representing the more significant digits as a fixed-point part. A rounding process is performed on the two addition results to obtain a result of the product-sum operation.

The present invention is directed at circuit for controlling a voltage applied to an output voltage terminal from a first voltage level supplied by an input voltage terminal comprising a first switch and a second switch connected in series between said input voltage terminal and a common terminal; a transformer, having a primary side and a second side, connected with said first switch on the primary side and to said output terminalon the secondary side; wherein when said first switch is closed and said second switch open, said first voltage level is supplied to said output voltage terminal; and wherein when said first switch is open and said second switch is closed, a second voltage level is supplied to said output voltage terminal.

The present invention relates to receiver equipment with AC-coupled receiver circuits and AC coupling filters. A switch connected between a first stage and a second stage among the receiver circuits is adapted to switch from a high coupling corner frequency, for rapid settling of a signal during preparation of data reception, to a low corner frequency, for low signal distortion during data reception. The receiver circuits are adapted to use known properties in the signal to perform the switch at a time when the short term DC-components of the signal are as low as possible.