12 results about "Floating point multiplier" patented technology

The invention discloses mixed precision multiply-add operation hardware, which comprises an input processing unit used for obtaining standard symbols, standard indexes and standard mantissas according to a pre-configured input format and unpacked input multiply-add operation factors, and obtaining input and output special value detection results; the floating point multiplier-adder is used for calculating an operation result after the operand multiplies the scaling factor and the offset is accumulated according to the symbol, the exponent and the mantissa of each multiplication-addition operation factor; and the output processing unit is used for obtaining a target format result according to a pre-configured output format, a rounding type and a normalization and rounding operation result, packaging the target format result according to a detection result and outputting the target format result, and by multiplexing a data path of the floating-point multiplier-adder, the chip area is saved, format conversion is integrated, a data stream is simplified, and the data processing efficiency is improved. The requirements for automatic reconstruction of the multiply-add operation unit according to input and output formats and quantization and inverse quantization of floating points and integers are met, and the reuse rate of computing resources is increased.

The invention discloses a high-energy-efficiency logarithm floating point multiplier based on truncation error compensation. The system comprises a compensation parameter modeling unit and a floating point multiplier module. The compensation parameter modeling unit obtains an optimal compensation value k through linear fitting and parameter optimization, and realizes regional self-adaptive compensation in combination with block modeling so as to reduce truncation errors; the floating point multiplier module comprises a special value detection module, a symbol exclusive or module, an exponential addition module and a mantissa truncation compensation module. In a logarithm domain, multiplication is replaced by addition, and compensation logic is introduced to correct errors. The multiplier supports various floating point precisions and configurable truncation bit widths, provides three representative structures to give consideration to both the precision and the energy efficiency, and is suitable for high-energy-efficiency calculation scenes such as neural networks and image processing.

An apparatus includes a floating-point gradient register; an integer register; a memory bank; and an array of processing units. Each of the units includes a plurality of binary shifters having an integer input configured to obtain corresponding bits of a 4-bit integer multiplicand, and a shift-specifying input configured to obtain corresponding bits in an exponent field of a 4-bit floating point multiplier. The multiplier is specified in a mantissaless four-bit floating point format including a sign bit, three exponent bits, and no mantissa bits. An adder tree has a plurality of inputs coupled to outputs of the plurality of shifters, and a rounder has an input coupled to an output of the adder tree. The integer inputs are connected to the integer register; the shift-specifying inputs are connected to the floating-point gradient register; and outputs of the rounders are coupled to the memory bank.

The invention relates to the field of floating-point multiplication, and particularly discloses a floating-point multiplier based on an FPGA, a calculation method and equipment, and the floating-point multiplier comprises a symbol calculation module which is used for determining the symbol of a target output floating-point number through an exclusive-OR gate and the symbol bits of a first input floating-point number and a second input floating-point number; the index addition module is used for adding the indexes of the first input floating-point number and the second input floating-point number and subtracting the deviation value of the corresponding format to obtain the index output of the target output floating-point number; the binary multiplier module is used for carrying out multiplication operation by using a Karatsuba algorithm and a Urdhva-Tiryagbhyam algorithm based on the mantissa bit widths of the first input floating-point number and the second input floating-point number so as to obtain a mantissa product of the target output floating-point number; and the result normalization module is used for performing normalization operation based on the mantissa product. The calculation delay can be reduced, and the percentage increase of the hardware area is also reduced.

The invention relates to a floating-point number multiplier, a computing chip and a floating-point number multiplication operation method, and belongs to the technical field of computers. According to the floating-point number multiplier, floating-point multiplication of a target floating-point number type is performed on input data by utilizing multiplication mode indication, the floating-point number type is specified as the floating-point number type of floating-point numbers in the input data, the floating-point numbers in the input data are divided into data groups by preprocessing the input data, and the floating-point numbers in the input data are divided into the data groups based on a target multiplication mode. According to the invention, the floating point data in the same data set is subjected to floating point number type floating point number multiplication operation, so that the floating point number multiplier can perform floating point number multiplication operation of various floating point number types by specifying different multiplication modes for input data of different floating point number types; therefore, the operation requirements of floating-point number multiplication of various floating-point number types can be met.

The invention provides a floating-point number multiplier, a near memory computing circuit, a high-bandwidth magnetic computing chip system and electronic equipment, and relates to the technical field of circuits, and the floating-point number multiplier comprises a compression circuit and a partial product generation circuit; the floating-point number multiplier is used for realizing mantissa multiplication of a known floating-point number of a multiplier; the partial product generation circuit comprises: a one-out-of-four selector; the compression circuit comprises a compressor and a summator. The one-out-of-four selector is used for generating a partial product of a known multiplier and a multiplicand after NR4SD + coding; the compressor is used for carrying out parallel compression on the partial product output by the one-out-of-four selector; and the adder is used for accumulating the parallel compression results output by the compressor and outputting an accumulation result to finish mantissa multiplication of the known multiplier and the multiplicand. The storage efficiency can be improved, and the area and power consumption of a hardware circuit are reduced.

The invention provides an approximate floating-point multiplier based on a Chebyshev polynomial, and the multiplier comprises two logarithm conversion modules which achieve logarithm function operation based on the Chebyshev polynomial, and convert an input single-precision floating-point mantissa into a logarithm approximate value with 2 as a base number; the adder is used for carrying out additive operation on the two logarithm approximate values; the exponential conversion module is used for realizing exponential function operation based on a Chebyshev polynomial and converting data output by the adder into an exponential approximate value taking 2 as a base number; and an exponent approximate value which is output by the exponent conversion module and takes 2 as a base number is a multiplication result of two single-precision floating point mantissas.

The present disclosure provides a floating point multiplier-adder, a processor and an electronic device. The floating point multiplier-adder includes a control module, a receiving module, a splitting module, an exponent operation module, a multiplication module, a scaling module and an addition module. The receiving module receives all of the first, second and third operands or only the first and third operands for an operation. The splitting module splits the operands received by the receiving module into a sign bit, an exponent and a mantissa, respectively. The addition module performs a first addition process on a scaling result of the mantissa and a multiplication result when performing a multiply-add operation, or performs a second addition process on the scaling result of the mantissa and a first mantissa of the first operand when performing an addition operation. The control module controls the splitting module, the exponent operation module, the addition module and the multiplication array module according to the type of the operation. The floating point multiplier-adder can reduce the power loss when the floating point multiplier-adder performs an addition operation.

An integrated circuit includes a digital signal processing circuit. The digital signal processing circuit includes fixed point multiplier circuits, floating point multiplier circuits, and adder circuits. The digital signal processing circuit is configurable to implement a reduction of floating point multiplication operations based on floating point inputs to the digital signal processing circuit using the fixed point multiplier circuits, the floating point multiplier circuits, and the adder circuits.

The application discloses a switchable precision floating-point multiplier-adder, which comprises a four-stage pipeline, a first-stage pipeline, a second-stage pipeline, a third-stage pipeline and a fourth-stage pipeline; the first-stage pipeline comprises a distribution processing module, a multiplier array module, an adder array adding module and an exponent comparison module; the second-stage pipeline comprises an exponent difference module, an alignment shift module, an addition tree module and a compression module; the third-stage pipeline comprises a leading zero prediction module, a leading zero coding module, a sign prediction module and an advance calculation module; and the fourth-stage pipeline comprises a sum and rejection module and an exponent normalization module. The floating-point multiplier-adder combines double-precision multiplication and addition to complete double-precision floating-point operation in the form of A+BxC, and the combination can greatly reuse the components in the multiplier-adder compared with a simple multiplier-adder combined with an adder. The application can be widely applied in the field of hardware operation devices.

The invention discloses an approximate floating point multiply-accumulate circuit and method, and belongs to the field of computer system structures and the technical field of digital circuit design, and the circuit comprises an approximate floating point multiplier precision arbitration module which receives a preprocessed floating point number and outputs a first precision control signal; the approximate floating point multiplication module is used for outputting an approximate floating point multiplication result by adopting an approximate addition scheme of different mantissa multiplication according to the first precision control signal; the approximate floating point adder precision arbitration module is used for receiving an approximate floating point multiplication result and a last partial sum result and outputting a second precision control signal; and the approximate floating point addition module is used for outputting a partial sum result by adopting an approximate addition scheme of different mantissa addition according to the second precision control signal. The calculation process is dynamically adjusted according to the characteristics of the input data, and when the difference of the input data is large, the circuit adopts accurate calculation to ensure the accuracy of the calculation result; when the input data difference is small, the circuit is switched to an approximate calculation mode to simplify the operation process.

A process for a floating point multiplier-accumulator (MAC) is operative on N pairs of floating point values using N MAC processes operating concurrently, each MAC process operating on a pair of values comprising an input value and a coefficient value. Each MAC process simultaneously generates: an integer form fraction at a first bitwidth and a second bitwidth greater than the first bitwidth, a sign bit, and an exponent difference computed by subtracting an exponent sum from a maximum exponent sum of all exponent sums. The integer form fractions of the first bitwidths are provided to an adder tree using the first bitwidth, and if the sum has an excess percentage of leading 0s, then the second bitwidth is used by an adder tree using the second bitwidth to form a great precision integer form fraction. The sign, integer form fraction, and maximum exponent are provided to an normalizer which generates a floating point result.