37 results about "Floating point multiplier" patented technology

The invention provides an FPGA-based sparse matrix vector multiplication processor. The processor comprises a preprocessing controller module, an operation module and a storage controller module, wherein the preprocessing controller module is used for performing scheduling and hazard detection and enabling a storage unit to keep continuous data flow for an operation unit array; the operation unitarray is composed of a plurality of operation units; single-precision floating-point sparse matrix vector multiplication operation is realized through single-precision floating-point multiplier and adder; and the storage controller module is used for controlling reading and writing of data in an off-chip DRAM. The beneficial effects are that the processor can expand the storage bandwidth and the operation resources, and the operation efficiency and universality of the processor are effectively improved.

The invention discloses a mask-based hybrid floating-point multiplication low-power-consumption control method . The method comprises the following steps: hardware automatically determines a hybrid floating point multiplication operation type, fills high bits of mantissa of a standard floating point multiplier and a multiplicand with all zero, and enables the floating point multiplier and the multiplicand to be the same as the input bit width of a multiplex fixed-point hardware multiplier; and for floating point multiplication operation, a partial product is obtained from the filled floating point multiplier and multiplicand according to a preset multiplication encoding rule and a symbol extension rule, an invalid mantissa is moved to a high order, and the invalid mantissa is controlled not to participate in partial product compression summation operation by adopting a mask so as to save logic power consumption. The invention further discloses a hybrid floating point multiplication low-power-consumption control device based on the mask. The method supports multiplexing of fixed-point multiplication hardware to realize low-power-consumption control of floating-point multiplication,automatic detection of floating-point multiplication operation by the hardware and control of high-order expansion bit coding based on masks, and has the advantages of low hardware overhead, easinessin logic implementation, simplicity in power consumption control and the like.