37 results about "Floating point multiplier" patented technology

A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.

The invention discloses a design of a full pipeline of a single precision floating point multiplication-add fused unit, which realizes multiplication-add operation in the form of A+B x C. the multiplication-add operation is realized in the following five pipelines: in the first stage pipeline, exponential difference is calculated and a part of the multiplication is completed; in the second stage pipeline, A and B x C are aligned according to the exponential difference, effective subtraction and complement are performed, the rest multiplication is completed, simultaneously, the exponent is divided into six states, and the calculation method of normalized shift amount in different states are different; in the third stage pipeline, the number of leading zero is pre-estimated, simultaneously the sign of the final result is synchronously pre-estimated, and finally first stage normalized shift is performed; in the fourth stage pipeline, second normalized shift is performed first, and then addition and a part of half adjust are performed; in the last stage pipeline, addition and half adjust are completed, exponential terms are amended, and third stage normalized shift is completed in the spacing of the half adjust. The invention has the advantages that high performance and high precision are realized in the condition of low hardware cost.

The invention discloses a water floating point multiply-accumulate method based on FPGA. The method comprises the following steps: firstly inputting a number M to undergo multiply-accumulate calculation, secondly, sequentially inputting M 32-bit binary floating point numbers A and B which are required to be calculated into floating-point multiplier to undergo multiplication till the operation of M data is accomplished, and simultaneously and continuously inputting the product result of the floating-point multiplier and the addition result of a first floating-point adder to the first floating-point adder to accomplish a part of summation operation to obtain a summation result, and thirdly, inputting data of the last N stage pipeline in the summation result obtained in step two into a second floating-point adder to be calculated to obtain the result of the whole multiply-accumulate process. The method has the advantages that the principle is simple, the universality is good, the operating speed can be improved, and the like.

A floating point multiplier includes a data path in which a plurality of partial products are calculated and then reduced to a first partial product and a second partial product. Shift amount determining circuitry 100 analyses the exponents of the input operands A and B as well as counting the leading zeros in the fractional portions of these operands to determine an amount of left shift or right shift to be applied by shifting circuitry 200, 202 within the multiplier data path. This shift amount is applied so as to align the partial products so that when they are added they will produce the result C without requiring this to be further shifted. Furthermore, shifting the partial products to the correct alignment in this way in advance of adding these partial products permits injection rounding combined with the adding of the partial products to be employed for cases including subnormal values.

The invention discloses an approximate floating-point multiplier for a neural network processor and a floating-point multiplication. When the approximate floating-point multiplier executes fractional part multiplying operation on an operand, part bits are intercepted from all high bits of a fractional part of the operand according to designated precision, and 1 is supplemented to the front and the back of the intercepted part bits to obtain two new fractional parts; multiplying operation is performed on the two new fractional parts to obtain an approximate fractional part of a product; and zero is supplemented to a low bit of the normalized approximate fractional part so that the bits of the approximate fractional part are consistent with the bits of the fractional part of the operand, and therefore the fractional part of the product is obtained. According to the approximate floating-point multiplier, an approximate calculation mode is adopted, different bits of the fractional part are intercepted according to a precision demand for corresponding multiplying operation, energy loss of multiplying operation is lowered, multiplying operation speed is increased, and therefore the performance of a neural network processing system is more efficient.

To perform a product-sum operation by adding third data to a product of first data and second data, a floating point multiplier first multiplies the first data by the second data, and a bit string representing a fixed-point part in the multiplication result is divided into a portion representing more significant digits in the fixed-point part and a portion representing less significant digits in the fixed-point part. Then, a floating point adder first adds less significant multiplication result data having a bit string representing the less significant digits as a fixed-point part to the third data, and then adds the addition result to more significant multiplication result data having a bit string representing the more significant digits as a fixed-point part. A rounding process is performed on the two addition results to obtain a result of the product-sum operation.

In a denormal support mode, the normalization circuit of a floating-point adder is used to normalize or denormalized the output of a floating-point multiplier. Each floating-point multiply instruction is speculatively converted to a multiply-add instruction, with the addend forced to zero. This preserves the value of the product, while normalizing or denormalizing the product using the floating-point adder's normalization circuit. When the operands to the multiply operation are available, they are inspected. If the operands will not generate an unnormal intermediate product or a denormal final product, the add operation is suppressed, such as by operand-forwarding. Additionally, each non-fused floating-point multiply-add instruction is replaced with a multiply-add instruction having a zero addend, and a floating-point add instruction having the addend of the original multiply-add instruction is inserted into the instruction stream. Upon inspection of the operands, if an unnormal intermediate result or a denormal final result will not occur, the addend may be restored to the multiply-add instruction and the add instruction converted to a NOP.

The invention discloses a 64-bit fixed and floating point multiplier unit supporting complex operation and subword parallelism. The multiplier unit is formed by combining four 32-bit multiplier units, wherein each 32-bit multiplier unit contains a 'carry' string used as output and an 'And' string used as output; the four 32-bit multiplier units contain four 'carry' strings and four 'And' strings; and the four 'carry' strings and the four 'And' strings are compressed by a 8-2 compressor to obtain a new 'carry' string and a new 'And' string for summation, so that the sum is used as the output of the multiplier unit. The 64-bit fixed and floating point multiplier unit reduces the time delay of key paths and the expense of operation resources.

The invention discloses a fixed-point and floating-point operation part with a shared multiplier structure in a GPDSP (General-Purpose Digital Signal Processor). The fixed-point and floating-point operation part comprises a floating-point multiplier-adder unit, a fixed-point multiplier-adder unit and a 64-bit fixed-point multiplier, wherein the floating-point multiplier-adder unit is used for supporting double-precision floating-point operation and double/single-precision floating point multiplication, multiplication-addition, multiplication-subtraction and complex multiplication operations of an SIMD structure; the fixed-point multiplier-adder unit is used for supporting 64-bit signed or unsigned fixed-point multiplication operation and double 32-bit signed or unsigned fixed-point multiplication operation of the SIMD structure; and the 64-bit fixed-point multiplier performs operation by regarding floating-point mantissa multiplication as unsigned fixed-point multiplication by multiplexing the structure of the same multiplier. The fixed-point and floating-point operation part has the advantages of capabilities of increasing the hardware utilization rate and reducing the chip area, and the like.

A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations.

The invention provides an FPGA-based sparse matrix vector multiplication processor. The processor comprises a preprocessing controller module, an operation module and a storage controller module, wherein the preprocessing controller module is used for performing scheduling and hazard detection and enabling a storage unit to keep continuous data flow for an operation unit array; the operation unitarray is composed of a plurality of operation units; single-precision floating-point sparse matrix vector multiplication operation is realized through single-precision floating-point multiplier and adder; and the storage controller module is used for controlling reading and writing of data in an off-chip DRAM. The beneficial effects are that the processor can expand the storage bandwidth and the operation resources, and the operation efficiency and universality of the processor are effectively improved.

A processor includes an integer multiplier configured to execute an integer multiply instruction to multiply significand bits of at least one floating point operand of a floating point multiply operation. The processor also includes a floating point multiplier configured to execute a special purpose floating point multiply accumulate instruction with respect to an intermediate result of the floating point multiply operation and the at least one floating point operand to generate a final floating point multiplication result.

The invention belongs to the field of digital signal processing, and discloses a reconfigurable integer-floating point multiplier which comprises an enabling control module, an integer-floating point preprocessing module, a pre-operation module, a reconfigurable multiplication module and an order matching module. The enabling control module generates a first control signal and a second control signal; the integer-floating point preprocessing module obtains first floating point type data and second floating point type data to obtain a first expansion mantissa and a second expansion mantissa; the front operation module obtains a sign bit of the floating point result and a temporary order code of the floating point result; the reconfigurable multiplication module obtains a temporary mantissa of an integer result or a floating point result; the order matching module obtains the mantissa and the order code of the floating point result. According to the method, floating point multiplication operation can be achieved, integer multiplication operation can be achieved under the condition that extra resources are not increased, the requirements of a current artificial intelligence chip can be fully met, data operation modes can be flexibly selected when different requirements are met, and the method has the better resource utilization rate, functionality and universality.

The invention discloses a mask-based hybrid floating-point multiplication low-power-consumption control method . The method comprises the following steps: hardware automatically determines a hybrid floating point multiplication operation type, fills high bits of mantissa of a standard floating point multiplier and a multiplicand with all zero, and enables the floating point multiplier and the multiplicand to be the same as the input bit width of a multiplex fixed-point hardware multiplier; and for floating point multiplication operation, a partial product is obtained from the filled floating point multiplier and multiplicand according to a preset multiplication encoding rule and a symbol extension rule, an invalid mantissa is moved to a high order, and the invalid mantissa is controlled not to participate in partial product compression summation operation by adopting a mask so as to save logic power consumption. The invention further discloses a hybrid floating point multiplication low-power-consumption control device based on the mask. The method supports multiplexing of fixed-point multiplication hardware to realize low-power-consumption control of floating-point multiplication,automatic detection of floating-point multiplication operation by the hardware and control of high-order expansion bit coding based on masks, and has the advantages of low hardware overhead, easinessin logic implementation, simplicity in power consumption control and the like.

A method for providing a floating point product consistent with the present invention includes multiplying a subprecise operand and a non-subprecise operand using a plurality of intermediate stages. The method further includes correcting an error introduced by the subprecise operand by performing an operation in conjunction with a one of the plurality of intermediate stages utilizing a compensating summand.

The invention discloses a floating-point multiply-add device, which realizes floating-point multiply-add operation in a form of A * B + C. The floating-point multiply-add device adopts a three-stage pipeline mode to realize the floating-point multiply-add operation, completes floating-point multiplication in a first pipeline beat, completes addition in a second pipeline beat and completes rounding operation and exception judgment in a third pipeline beat, and outputs a final result. The floating-point multiply-add device has the advantages that single-double-precision floating-point number multiply-add operation is achieved, and a three-level assembly line framework of non-normalized numbers is supported.