Multiplication rounding implementation method and device

An implementation method and a rounding technology, which are applied in the direction of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems affecting the performance of floating-point processing units and low calculation efficiency, and achieve the goal of improving performance and improving execution efficiency Effect

Inactive Publication Date: 2011-04-06
HISILICON TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the prior art, if an overflow is caused by the rounding operation, another rounding operation is required, that is, the one bit shifted to the right due to the overflow is rounded, which leads to low calculation efficiency and affects the floating point processing unit performance

Method used

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  • Multiplication rounding implementation method and device
  • Multiplication rounding implementation method and device
  • Multiplication rounding implementation method and device

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Embodiment 1

[0033] figure 1 It is a flow chart of the implementation method of multiplication and rounding provided by Embodiment 1 of the present invention. The method of this embodiment specifically includes the following steps:

[0034] Step 110. Obtain the carry result and sum result of the carry-reserved form of the floating-point number respectively. As mentioned above, the floating-point number is divided into high bit, L bit, R bit and sticky bit, the L bit is the lowest bit of the reserved part, and the high bit is the reserved part For the remaining part except the L position, the R position is the highest position of the truncated part, and the sticky position is the remaining part of the truncated part except the R position;

[0035] Step 120, add the high bit and L bit of the carry result and the sum result respectively using a half adder, and add the R bit using a full adder to obtain the secondary carry result and the secondary sum result, and simultaneously obtain the high...

Embodiment 2

[0045] figure 2 It is a flowchart of a method for implementing multiplicative rounding provided by Embodiment 2 of the present invention. This embodiment is specifically a method for rounding floating-point numbers according to the round-to-nearest mode. Rounding to the nearest can be achieved by rounding to the nearest upper limit (Round to Nearest Up, RNU for short) and then correcting the L bit. For the correction of the L bit, according to the inventor's research in the process of implementing the present invention, it is found that rounding to the nearest can be done by adding 1 to the R bit of the rounded result, and when the sticky bits of the rounded result are all 0, the rounded The L position of the result is 0 to get. For the two cases of overflow and non-overflow, when there is no overflow, 1 should be added to the R bit of the rounded result; when overflow, 1 should be added to the L bit, that is, the upper bit of the R bit, which is equivalent to the R bit Add...

Embodiment 3

[0065] Figure 4 It is a flow chart for judging a tie situation in the implementation method of multiplication and rounding provided by Embodiment 3 of the present invention. This embodiment is based on Embodiment 2 and further considers the tie situation in the round-to-nearest mode. The so-called tie situation means that the value represented by the truncated part in the result to be rounded is the average value of the upper limit and the lower limit of the numerical value of the equivalent length. At this time, the result to be rounded is in the middle of the two nearest values. If binary 110.1000 is rounded to an integer, 1000 is equal to one-half of (0+1111). The IEEE754 standard specifies rounding to the nearest even number in this case.

[0066] Since the rounding to the nearest provided by Embodiment 2 is realized by rounding to the nearest upper limit, when a tie occurs, it is only necessary to set the L position of the rounding result obtained by rounding to the ne...

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Abstract

The invention discloses a multiplication rounding implementation method and a device. The method comprises the following steps: respectively obtaining carry result and sum result in the floating point number carry save form; adopting a half-adder to respectively add the high bit and the L bit of the carry result and the sum result, adopting a full adder to add the R bit to obtain secondary carry result and secondary sum result, and simultaneously obtaining high bit overflow value after high bit adding; obtaining carry value and sum value of the L bit in the current rounding mode; taking the sum value of the L bit as the L bit of rounding result, taking the sum of the high bit of the secondary carry result and the high bit of the secondary sum result as the high bit of the rounding result when the carry value of the L bit is identified to be 0, and taking the sum of the high bit of the secondary carry result and the high bit of the secondary sum result plus 1 as the high bit of the rounding result when the carry value of the L bit is identified to be 1. The method and the device can improve the execution efficiency of the rounding operation of a floating-point multiplier and improve the performances of a floating-point processing unit.

Description

technical field [0001] Embodiments of the present invention relate to floating-point computing technology, and in particular to a method and device for implementing multiplication and rounding. Background technique [0002] The floating-point processing unit of a modern microprocessor generally includes a floating-point multiplier compliant with the Institute of Electrical and Electronics Engineers (IEEE) 754 standard. Since more than 30% of the floating-point operations are floating-point multiplication operations, the floating-point multiplier is the key to determine the performance of the floating-point processing unit. [0003] Floating-point multiplication usually includes the steps of decoding, generating partial products, compressing partial products, generating results, and rounding the results in a prescribed mode. After the partial product compression, the floating-point multiplication will get the result of the carry save form (carry save), that is, two strings o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/57
Inventor 周昔平
Owner HISILICON TECH
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