149 results about "U-bit" patented technology

A method, of an aspect, includes challenging a set of Physically Unclonable Function (PUF) cells, of an integrated circuit device, and receiving a set of PUF bits from the PUF cells in response. A PUF key is generated based on the set of PUF bits. An encryption of the PUF key with an embedded key is output from the integrated circuit device. The integrated circuit device receives an encryption of a fuse key with the PUF key. Fuses of the integrated circuit device are programmed with at least one of the fuse key and the received encryption of the fuse key with the PUF key. Other methods, apparatus, and systems are also disclosed.

Methods and systems for producing an encoded information signal having attenuated low frequency spectral components and a substantially constant average energy. An M bit code word is produced for each N bits of an information signal according to the following conditions: (a) each code word includes an equal number of logic zero bits and logic one bits; (b) each code word includes no more than two consecutive identical bits; and (c) M is greater than N. For example, M equals eight and N equals four. Such an encoded information signal is especially useful for generating a magnetic field signal usable for locating an underground object. This is in part because information sidebands of the magnetic field signal to have desired spectral characteristics that are useful in environments that often include harmonically derived interference signals at regular 50 Hz (±0.1 Hz) or 60 Hz (±0.1 Hz) intervals caused by power lines.

The present invention relates to the encoding and decoding respectively of serial data, using block codes. Encoding of a serial bit stream of input data in groups of N bits, so-called words (O), to serial output data in groups of 2N bits, so-called code words (KO), is preferably carried out by a logic circuit in a manner such that N of the 2N bits in the code words (KO) are comprised of the N bits input data, unchanged or inverted, and remaining bits in the code words (KO) are determined so that, seen statistically, the code words (KO) will include approximately as many zeros as ones, such that each code word (KO) will be unique for each word (O), and such that at least one of the code words (KO) will remain unique even in bit stream shifting processes. Decoding includes further encoding in a similar logic circuit and comparison of the incoming code words with the code words encoded in the logic circuit, in a predetermined manner.

A network device includes a media access control (MAC) device that transmits a first data stream at a first data rate that includes symbols having M bits. A translator converts the first data stream to a second data stream at a second data rate. The translator includes a data appender that appends N bits to the symbols in the first data stream to generate second symbols having M+N bits. A data duplicator duplicates the second symbols X times to produce the second data stream at the second data rate.

A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2^S entries, the current stride table is compressed to store only 2^D entries. Ideally, the number of valid entries in the current stride table is between 2^D−1 and 2^D for maximum compression. Storage requirements are reduced.

Disclosed is a method of modular multiplication of two L-bit numbers (X, Y), the result defined from XY+mM, where M is the modulo, of L bits, and m is a number of L bits found and is divisible by 2^L. L/k iterations are performed, an iteration i involving XY_i+m_iM+R, Y_i, m_i being k-bit digits of rank i of Y, m from least significant bits, and R the previous iteration result. In each iteration, a first sub-loop of k/p iterations calculates a partial result of XY_i+m_iM+R on k least significant bits of X, M, R, following decomposition of X, m_i into p-bit digits. Starting each sub-loop iteration, the p bits of the current digit of m_i are simultaneously produced. A second sub-loop calculates and sums the remaining partial results of XY_i+m_iM+R using m_i from the first sub-loop.

There is provided a method for enabling a user equipment to transmit feedback information. The method includes generating feedback data representing the feedback information, the feedback data expressed by a binary number having N bits, where N is an integer, the N bits comprising 2 levels, the feedback information represented by one of the 2 levels, wherein different types of the feedback information are assigned to different levels and transmitting the feedback data. Overheads incurred by transmission of feedback information can be reduced.

A method and apparatus for generating pseudo-random numbers. The method includes defining a first set of R bits and defining a second set of S bits different from the first set of R bits. The method also includes updating the second set of S bits using a predetermined process that operates on the first set of R bits and the second set of S bits to form an updated set of S bits. The method also includes updating the first set of R bits using another predetermined process. The apparatus may include a linear feedback shift register and a second register. The linear feedback shift register is configured to store R bits. The second register is configured to store S bits. Each bit of the S bits is updated using a function that operates on one or more of the R bits from the linear feedback shift register and one or more of the S bits.

In order to provide a method or the like for storing floating point numbers to make it easier to manage the floating point numbers using a fixed point processor, when a real number x is represented by a*(2{circumflex over ( )}n) where a mantissa is a and an exponent is n, the mantissa is stored as a fixed point number in the upper U bits of N-bit field (N>=(U+L)) and the exponent is stored as an integer in the lower L bits. For the multiplication of two real numbers represented in such a format, these two real numbers are multiplied as fixed point numbers so as to make only the upper significant bits of the multiplication result a mantissa, while these two real numbers are added as integers so as to make only the lower significant bits of the addition result an exponent. As a result, the multiplication result can be obtained in a floating point format.

The invention can effectively reduces the occupation on redundancy bandwidth, avoid the generation of flag bit sequence of segments and lower the load of CPU. In the invention, reading the k bits of next group to the shift register from serial HDLC data stream; if the valid data only have C bits, C<K, then the front K-C bits in flag bit sequence are filled into the remaining space of shift register; sending the data in the shift register, and recording C; when needing to send next HDLC frame, the rear K-C+A bits in flag bit sequence are filled into the shift register, and then reading the valid data of the next HDLC frame from the serial HDLC data stream; wherein, A represents the bit numbers in flag bit sequence.

A highly-efficient hybrid class-S modulator circuit for a polar modulator includes a class-S path having a digital pulse-width modulator (PWM) generator, which receives the K most significant bits (MSBs) of N-bit digital input words to generate a discrete set of PWM signals. The discrete set of PWM signals drives a buck converter, to provide a modulated power supply voltage signal having a plurality of quantized voltage levels. An error generated by using only K of the N bits of each N-bit word is reduced by dithering the input drive and converting the error to an AC signal. Dithering is performed by feeding the N−K least significant bits (LSBs) of each N-bit input word to an input of a digital oscillator, while feeding the K most significant bits (MSBs) of each word to the PWM generator. The digital oscillator converts the N−K LSBs of each input word into an oscillating single LSB. An oscillating error signal appearing at the output of the modulator is fed to the inverting input of an op-amp connected in parallel with the class-S path. At the same time, the desired output voltage, which is represented by the full N bits of the N-bit input words, is coupled to the non-inverting input of the op-amp. The op-amp responds to the input signals by sourcing or sinking current into or out of the modulator output terminal, thereby removing the error attributable to using only K of the N bits at the PWM generator.

A data encoding system for a data stream comprises an interleaving module that receives the data stream as N bit data blocks and that reverses positions of at least two of the N bits of selected ones of the data blocks. A generating module generates P error checking bits for each of the N bit data blocks. An insertion module receives the P error checking bits from the generating module and inserts the P error checking bits into the corresponding data block received from the interleaving module.

Methods of encoding and decoding, as well as an encoding system and a digital communications system are provided for encoding data words into code words and decoding code words into data words. The data words are encoded according to a run-length-limited (RLL) code of “k” constraint, the encoding producing u-bit non-zero code words. The “k” constraint can be increased to a higher value by extending the u-bit non-zero code words to generate q-bit non-zero code words.

The invention discloses a secure and efficient block chain customization login method and security reinforcing system. The method logs in a block chain network and comprises the following steps: selecting N bits from M bits of a character string of an original key according to a basic protocol to take as a simple login key to return to a client for logging in, performing encryption on the rest (M-N) bits of the character string to obtain an encrypted key value, then storing an encrypted result of the key to a data server, performing decryption on the encrypted key value in use to obtain the (M-N) bits of the character string, and forming the complete M bits of the character string by inputting the N bits of the character string for mutual confirmation. According to the secure and efficient block chain client login method and security reinforcing system disclosed by the invention, when the client logs in, the digits are few and are easy to be remembered, thereby being convenient for customization; and meanwhile, the character string is encrypted and stored in segments, so the security capability is high; and thus, the problems that the existing block chain private key is lost and stolen easily are solved well.