150 results about "U-bit" patented technology

N data bits are stored in ┌N / M┐ cells by programming each cell with up to M of the bits according to a valid, nonserial bit ordering that satisfies one of the following criteria: Either the number of threshold voltage comparisons needed to read all M bits sequentially is at most 1 more than the smallest such number, or the largest number of threshold voltage comparisons needed to read any bit is minimized, or the smallest number of threshold voltage comparisons needed to read any bit is minimized, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit statically is at most 1 more than the smallest such difference, or the difference between the largest and smallest number of threshold voltage comparisons needed to read any bit dynamically is minimized.

A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate / mask and add operation in a three input arithmetic unit.

A method and apparatus for generating pseudo-random numbers. The method includes defining a first set of R bits and defining a second set of S bits different from the first set of R bits. The method also includes updating the second set of S bits using a predetermined process that operates on the first set of R bits and the second set of S bits to form an updated set of S bits. The method also includes updating the first set of R bits using another predetermined process. The apparatus may include a linear feedback shift register and a second register. The linear feedback shift register is configured to store R bits. The second register is configured to store S bits. Each bit of the S bits is updated using a function that operates on one or more of the R bits from the linear feedback shift register and one or more of the S bits.

Whenever N data bits are stored in a cell of a memory that programs each of its cells to represent any one of 2N different patterns of N>1 bits as a respective one of 2N ordered cell states, the N data bits are mapped to a transformed pattern of N bits according to a transformation that maps the pattern of the lowest state (typically all 1's) to a different pattern, and the cell is programmed to represent the transformed pattern. The transformation may invert all, some or only one of the bits of each pattern. Whenever the cells of the memory are read, the transformation is inverted.

A mask circuit (2) masks a bit sequence of K bits by a predetermined bit pattern. An EXOR circuit (3) EXORs the masked bit sequence. An inverter (9) controls inversion / non-inversion of values of bits of a bit sequence which includes a bit value indicating the EXOR result in a result obtained by shifting the bit sequence of K bits held in a shift register (1), in accordance with a designated bit value in a pattern table (14). A bit sequence as the control result is output as a random number expressed by K bits.

A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N / M sections, each constellation word being associated with one of the N / M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.

A mask circuit (2) masks a bit sequence of K bits by a predetermined bit pattern. An EXOR circuit (3) EXORs the masked bit sequence. An inverter (9) controls inversion / non-inversion of values of bits of a bit sequence which includes a bit value indicating the EXOR result in a result obtained by shifting the bit sequence of K bits held in a shift register (1), in accordance with a designated bit value in a pattern table (14). A bit sequence as the control result is output as a random number expressed by K bits.