71 results about "Linear feedback shift register" patented technology

The invention discloses a hyperspectral band selection and extraction system and method based on an FPGA (Field Programmable Gate Array), and mainly solves the problems of high complexity, poor real-time performance, low compressed sensing band selection efficiency and more occupied resources of the existing band selection algorithm. According to the implementation scheme, the method comprises the following steps of: generating data storage and an address by using a three-layer nested counter, generating a storage address of a hyperspectral image, reading an external original hyperspectral image according to the address, and storing the external original hyperspectral image into an RAM (Random Access Memory) for caching; setting an n-order linear feedback shift register, feeding back a polynomial and a seed value, generating a sparse random binary matrix, and linearly outputting a 0-1 random number to a subsequent operation module; and carrying out operation on the input original hyperspectral data and the sparse random binary by adopting a judgment accumulation mode to obtain selected hyperspectral data. According to the method, the number of wavebands needing to select dimension reduction can be flexibly adjusted, internal resource consumption is reasonably reduced, the timeliness of waveband selection in a satellite-borne scene is improved, and the method can be used for efficient spectral information processing of satellite-borne, airborne and other resource-limited platforms.

The invention belongs to the technical field of integrated circuit hardware security, and discloses a double-dynamic key encryption circuit and method for dynamically changing dynamic keys after interpretation, and the circuit comprises an external dynamic key module, an internal dynamic key module and a circuit original logic module. And the external dynamic key module generates a dynamic key signal through the linear feedback shift register unit, and the internal dynamic key module generates a D / T selection signal according to a parity check result of the dynamic key signal to dynamically change the type of a trigger in the state machine. The state machine is divided into a group A and a group B, key updating is triggered at an entrance state through a state detection unit, and it is ensured that the key is still dynamically changed after being interpreted. Through a double-dynamic key mechanism and state machine jump confusion, probe detection and bypass attacks are effectively resisted, and the safety of the circuit is remarkably improved. And when the initial key is wrong, circuit jump is abnormal, so that IP protection is realized. The method has the advantages of high attack resistance, dynamic key change, high security and the like.

The invention relates to the technical field of pseudo-random binary sequence design, in particular to a parallel PRBS generation method and system for testing a multi-protocol high-speed serial transceiver, and the method comprises the steps: setting demand parameters of a pseudo-random binary sequence for testing the multi-protocol high-speed serial transceiver, and enabling the demand parameters to comprise an order, a bit number and a feedback polynomial; constructing a generator matrix for describing state transition of the linear feedback shift register according to the feedback polynomial; according to the bit number of the pseudo-random binary sequence, generating a mapping matrix of the pseudo-random binary sequence through the exponentiation of the generated matrix; based on the mapping matrix and the current beat linear feedback shift register state, outputting a pseudo-random binary sequence meeting the requirement parameters for testing the multi-protocol high-speed serial transceiver. According to the method, parallel generation of any PRBS can be supported, the PRBS parallel implementation logic configuration is simple, the hardware implementation complexity is low, the PRBS output throughput rate is high, and the design requirements of multi-protocol high-speed SerDes can be met.

The invention discloses a high-precision arbitrary carrier generation method based on an FPGA (Field Programmable Gate Array) and an intermediate-frequency DAC (Digital-to-Analog Converter), which comprises the following steps of: when a system needs to execute arbitrary carrier generation, firstly, configuring a carrier frequency needing to be generated through instruction input, and calculating to obtain an equivalent carrier frequency by using an equivalent carrier conversion module based on a Nyquist sampling theorem and an equivalent carrier conversion formula; the phase calibration unit formulates a phase value of each channel, and then performs dynamic phase compensation based on a linear feedback shift register to generate a dynamically compensated phase control word; and finally, the multi-channel waveform generation module generates an equivalent carrier based on the multi-channel parallel DDS. According to the high-precision arbitrary carrier generation method based on the FPGA and the intermediate-frequency DAC, the limitation of the working clock frequency of an existing FPGA device is broken through through cooperative work of the carrier conversion module and the multi-channel waveform generation module, and high-flexibility arbitrary carrier generation is achieved.

The invention discloses data randomization equipment, a data randomization method and a solid state disk, belongs to the field of data randomization, and aims to solve the problem that linear feedback shift registers are low in cost and the randomness of obtained random interference can be improved through cascaded linear feedback shift registers. Therefore, a scrambling module in the data randomization equipment comprises a plurality of cascaded linear feedback shift registers, and the cascaded linear feedback shift registers can output M-bit random interference through each bit output channel according to an input seed of data to be written and a clock signal of a data transmission bus; the random interference is generated through the multi-stage cascaded linear feedback shift registers, so that the randomness of the generated random interference can be greatly improved, the data randomization effect is improved, and the implementation cost is relatively low.

The application discloses a general lightweight hash processing method and system and a storage medium. A linear feedback shift register (LFSR) is selected, and a register state conversion function is used to perform state conversion on the linear feedback shift register (LFSR). The output of the linear feedback shift register (LFSR) is used to initialize the internal state of a hash algorithm in combination with an initialization algorithm. Data for which a hash value needs to be calculated is input, and an update algorithm is used to update the initialized internal state. The data for which the hash value needs to be calculated is filled data. A determination algorithm is used to post-process the updated internal state to generate a final hash value. The application solves the speed and security problems of existing hash processing, is simple to implement, can flexibly adjust the length and starting point, is beneficial to parallel and rapid calculation, has small required storage space, and can dynamically append a hash word to eliminate collision when a hash collision occurs, thereby improving security.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

The invention relates to a linear and probabilistic logarithm counter. In one aspect, a dual scale counter circuit is provided, the dual scale counter circuit comprising: a counter logic unit to store a current counter value; a range determination logic to determine an operating range of the dual scale counter circuit based on the current counter value and a predetermined threshold; and a counter delta logic unit. The counter delta logic is to linearly increase the current counter value for delta events in response to the dual scale counter circuit operating within a linear range, and probabilistically increase the current counter value for delta events in response to the dual scale counter circuit operating within a probability range. The dual-scale counter circuit further includes a linear feedback shift register to generate a random binary bit sequence, a counter delta logic to generate a random binary bit sequence when the dual-scale counter circuit operates within a probability range, and a linear feedback shift register to generate a random binary bit sequence. It is determined whether to increase a current counter value for an incremental event based on the random bin sequence.

The application provides a linear feedback shift register and a construction method, device and equipment and a medium, which can be applied to the technical field of registers. The construction method comprises the following steps: determining information of shift chains required by all to-be-supported algorithms, the to-be-supported algorithms being algorithms required to be supported by the linear feedback shift register; and constructing the linear feedback shift register according to the information of the required shift chains. Compared with a static construction method, the construction method provided by the application is more flexible and can implement multiple algorithms. Compared with a dynamic construction method, the linear feedback shift register obtained by the method provided by the application requires less configuration information, so that the cost is smaller.

The invention discloses a memory with a test function and a test method, the memory comprises a plurality of columns of memory modules and a test circuit, the test circuit at least utilizes n + 1 columns of adjacent target memory modules, n is greater than or equal to 1, at least one row of first memory units and three rows of second memory units are multiplexed in each column of target memory modules, and a NOR gate is arranged in each column of target memory modules. Each NOR gate and the first storage unit and the second storage unit which are multiplexed in the target storage module in the same column form a local XOR module; when the test circuit is used in the test process, the first n columns of local XOR modules in the first direction are used as D triggers in a linear feedback shift register or a multi-input signature register when the test circuit is used for testing. And when the input end of the evaluation circuit in the memory is not provided with a trigger, a linear feedback shift register does not need to be added, so that the hardware overhead is reduced.

The invention relates to a fault detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring an analog voltage signal; the analog voltage signal is generated by performing corresponding XOR operation on the linear feedback shift register module; amplifying and coupling the analog voltage signal, and injecting the amplified and coupled analog voltage signal into a reactor to be tested; acquiring a response voltage signal and a response current signal of the to-be-tested reactor to the analog voltage signal; extracting multi-domain features from the response voltage signal and the response current signal, and coding based on the multi-domain features to obtain a feature fingerprint image; and inputting the feature fingerprint image into a fault identification model to obtain a fault identification result. By adopting the method, the fault type can be identified in time.

The application discloses a kind of cross-scale visual ultra-precision motion measurement device and method, the device includes image sensor, aperture diaphragm, imaging lens group, coaxial light source, beam splitter, positioning platform, encoding plate and DSP and ARM integrated signal processing system.In the method, by selecting the number of linear feedback shift register and period large λ and carrying out periodic coding, after DSP and ARM signal processing system pre-processing operation to image, static random access memory is driven to carry out image caching;Two-dimensional Fourier transform is executed to cached image, and relevant linear phase processing is carried out;According to the phase data obtained by linear phase processing, the corresponding binary sequence on local image is identified;The identified local binary sequence is looked up to the binary sequence of encoding plate and positioned, and according to the phase constant of periodic phase measurement, fine positioning is carried out.

The invention relates to a method for starting a silicon resonance accelerometer based on a pseudo-random number principle, and the method comprises the steps: analyzing the oscillation starting condition of a resonance beam based on a mechanical model of the resonance beam in the silicon resonance accelerometer, and enabling the resonance beam to start oscillation when the frequency of an input signal is close to the resonance peak frequency of the resonance beam; a linear feedback shift register is adopted in a digital circuit to generate pseudo-random number sequence simulation white noise, and the white noise comprises resonance peak frequency; and exciting the resonant beam based on the pseudo-random number sequence, when the amplitude of the silicon resonant accelerometer reaches a preset amplitude, indicating that the resonant beam starts oscillation, and at the moment, switching to use a sinusoidal signal of the phase-locked loop to maintain oscillation of the resonant beam so as to realize self-adaptive starting of the silicon resonant accelerometer. According to the method, resonance beams with different resonance frequencies can be excited to start oscillation, the complexity of the starting process of the silicon resonance accelerometer digital circuit is reduced, the self-adaptive starting capability is improved, and the method has very high engineering application value.

A test and measurement instrument has one or more channels to receive data from a device under test through a test fixture, the data being transmitted by the DUT in accordance with the Universal Serial Bus protocol 3.x, and one or more processors to: acquire a state of a linear feedback shift register (LFSR), extract a known portion of the LFSR as an LFSR value; shift the LFSR value a predetermined number of times to produce a new value of the LFSR, compare the new value of the LFSR to a value of incoming data to determine if the incoming data comprises a potential control code, repeat to acquire a predetermined number of potential control codes, compare them to known control code values to determine if they are valid, and if so, lock a seed used to descramble the remaining incoming data.

The present disclosure provides a computer-implemented method for authenticating devices using an encryption system (30). The method includes receiving an input word (31), obfuscating the input word (31) using a shift register encryption key (51) to obtain a shift register polynomial (41), and obfuscating the input word (31) using a generator encryption key (52) to obtain a generator polynomial (42). The method further includes shifting the shift register polynomial (41) through a Linear Feedback Shift Register (LFSR) (40) for at least one cycle using the generator polynomial (42) to obtain an output polynomial (43), obfuscating the output polynomial (43) using an output encryption key (53) to obtain an output codeword (32), and outputting the output codeword (32) for device authentication.

Cyclic redundancy check (CRC) algorithms are utilized in digital communication and storage systems for error detection. CRC encoding and decoding may be implemented using linear feedback shift registers (LFSRs). To achieve high throughput, a parallel LFSR may be implemented by registers using feedback matrix and pre-processing matrix multiplication. In conventional architectures, a feedback matrix may be decided by look-ahead computations of an FSR, and the corresponding matrix multiplication may contribute to a significant portion of the overall complexity of the LFSR. The methods described herein are provide for searching over a wide range of powers of a companion matrix describing the parallel LFSR in order to minimize the logic gate count required for the feedback matrix multiplication.

One aspect provides a dual-scale counter circuit that includes a counter logic unit for storing the current counter value, a range determination logic unit for determining the operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold, and a counter increment logic unit. The counter increment logic unit is used to linearly increment the current counter value for an increment event in response to the dual-scale counter circuit operating in a linear range, and to probabilistically increment the current counter value for the increment event in response to the dual-scale counter circuit operating in a probabilistic range.The dual-scale counter circuit also includes a linear feedback shift register for generating a random binary bit sequence, on the basis of which the counter increment logic unit is to determine whether the current counter value should be increased for the increment event when the dual-scale counter circuit is operating in the probabilistic range.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

The invention provides an arithmetic square root approximate calculation device and method based on maximum negative correlation, and belongs to the field of integrated circuit design. The circuit comprises a linear feedback shift register, a comparator, a square root calculation unit, a positive correlation median generation unit, a half-value scaling unit, a division unit and a delay unit. According to the arithmetic square root circuit approximate calculation device based on the maximum negative correlation, the minimum obtained mean square error (MSE) can reach 0.0031, and good precision is achieved.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

The invention discloses a method for accurately calculating a signal code rate. The method comprises the following steps of: constructing a signal receiving model under a multi-path channel; generating a pseudo-random signal sequence by using a linear feedback shift register, fitting a signal receiving model corresponding to each channel path by using the pseudo-random signal sequence, optimizing an attenuation coefficient and delay of the signal receiving model by using a genetic variation algorithm, and outputting an optimal signal receiving model; fourier transform is utilized to obtain a frequency spectrum of the output signal, and the frequency spectrum is detected to obtain a candidate value of a code rate; and filtering a received signal output by the optimal signal receiving model by adopting an adaptive filter, and correcting a candidate value to obtain an accurate code rate. According to the method, the influence of multipath propagation on signals is considered, and calculation errors caused by neglecting the multipath effect are avoided. And in combination with adaptive filtering, the code rate can be corrected and accurately calculated, and the accuracy of code rate calculation is remarkably improved.

The invention discloses a quality evaluation method and device for a cable for a television serial data interface, and relates to the technical field of communication data processing, a pseudo-random binary sequence and an ill-conditioned code are generated through a linear feedback shift register, and the pseudo-random binary sequence and the ill-conditioned code are converted into serial data through a serializer after being selected by a gating switch. The amplitude of serial data is adjusted through the adjustable attenuator, the serial data is input into a target cable for transmission, and the transmitted signal is processed by the rate adaptive equalizer and analyzed into parallel data by the deserializer. A pseudo-random code checker and a ill-conditioned code checker are adopted for error rate analysis, HD-SDI is gradually upgraded to 3G-SDI and UHD-SDI, and whether the cable meets the corresponding rate requirement or not is judged through dual detection logic. The method comprises the following steps: recording error code initial attenuation values at different rates, constructing a model based on an attenuation formula, calculating beta and gamma to judge the theoretical feasibility of 3G-SDI and UHD-SDI, actually measuring if the theoretical feasibility is feasible, calculating the maximum transmission distance if the theoretical feasibility is not feasible, and finally generating evaluation information containing the applicable rate and the like.

The application provides a key generation method, a register address scrambling method, a descrambling method and a chip. The key generation comprises generating a periodic pseudo-random sequence by using a linear feedback shift register, and generating an index value based on an original address; a sub-sequence is intercepted from the pseudo-random sequence according to the index value, and the bit width of the sub-sequence is the same as that of the original address; and a key is generated according to the sub-sequence and a static seed. The application utilizes a dynamic index mechanism, that is, the low bits of the original address are used as a variable index, to solve the problem of static mode address leakage. In addition, the application also realizes address consistency, that is, the static seed is used to ensure scrambling consistency of chips of the same type, and also realizes low resource consumption. The linear feedback shift register (PRBS) algorithm and the lightweight XOR operation are used, and compared with other complex encryption and hardware-level encryption, low delay and low consumption are brought, and the method is more suitable for register-level access.

The application discloses a kind of cable quality evaluation method and device for television serial data interface, it is related to communication data processing technical field, the present application generates pseudo-random binary sequence and ill-conditioned code by linear feedback shift register, after being selected by gating switch, it is converted into serial data by serializer.The amplitude of serial data is adjusted by adjustable attenuator, input target cable transmission, after transmission, signal is processed by rate adaptive equalizer, and is parsed into parallel data by deserializer.Pseudo-random code and ill-conditioned code checker are used for error rate analysis, from HD-SDI gradually upgrade to 3G-SDI, UHD-SDI, whether cable meets corresponding rate requirement is judged by double detection logic.Record the initial attenuation value of error rate under different rates, construct model based on attenuation formula, calculate β and γ to judge the theoretical feasibility of 3G-SDI, UHD-SDI, if feasible, then measured, if not feasible, then calculate the maximum transmission distance, finally generate evaluation information containing applicable rate etc..

Methods, systems, and devices for operational modes of a memory register are described. For example, a memory system may operate a register as a shift register, a multiple-input shift register (MISR) circuit, and a linear-feedback shift register (LFSR) circuit based on inputs provided to the register via respective multiplexers. In some instances, the register may operate as a shift register and a seed may be loaded to the associated flip-flops. The register may switch operational modes and may operate as a MISR circuit to test a data path between the associated memory system and a host system in the write direction. The register may also switch operational modes and may operate as a LFSR circuit to test the data path in the read direction. The register may operate in the respective modes based on inputs provided.

The present invention relates to a chirped digital signal generation method based on a linear feedback shift register. First, according to a target configuration signal, the start and end frequency control words and the signal change rate control word of each effective period of the chirp signal are configured. Then, for each period in a single cycle, the frequency control word FCW and the phase control word PCW are successively accumulated with time steps, and the phase control word PCW is synchronously superimposed in combination with the phase jitter pseudo-random value of the linear feedback shift register. Finally, a table lookup and a complement operation are performed to obtain amplitude signals output successively to form a period signal. The single-cycle target chirped digital signal is efficiently formed from the period signals. At the same time, a corresponding system is designed. The design scheme provides higher spectrum performance and realizes the generation of complex multi-segment linear frequency modulation signals without significantly increasing hardware resources, thereby enhancing the flexible configuration capability of the direct frequency synthesizer.

Provided in the present disclosure are a test circuit, a test method and a chip stack structure. The test circuit is applied to a logic chip, and comprises a first register module, which is electrically connected to a first path and a first through silicon via of the logic chip, wherein when a first test enable signal is at a first level, the first register module is configured as a linear feedback shift register, and receives a first test signal at a first speed by means of the first path; and when the first test enable signal is at a second level, the first register module is configured as an ordinary shift register, and serially outputs values in the first register module on the basis of a serial test protocol, so as to obtain a first test result signal. The present disclosure at least facilitates a speed test of a logic chip before stacking, thereby saving on test costs.

Electronic devices, circuitry, and methods are provided to efficiently generate a dither signal. An electronic device may include an output device, such as a speaker, to output a media signal, such as an audio signal, based on dithered media data, such as dithered audio data. The electronic device may include dithering circuitry to generate a dither signal, based on a first pseudorandom signal from a first linear feedback shift register and a second pseudorandom signal from a second linear feedback shift register, to add to the media signal to generate the dithered media signal.

The invention discloses a grain depot grain condition data encryption transmission system, which comprises a power conversion circuit matched with a circuit, a microprocessor processing circuit and a Lora communication transceiver circuit, and is characterized in that the microprocessor processing circuit and the Lora communication transceiver circuit are electrically connected with the power conversion circuit; the power conversion circuit comprises a power conversion chip U1. According to the method, data transmission of the grain condition of the grain depot is completed in real time, necessary measures are taken, a linear feedback shift register is adopted to generate a repeatable pseudo-random binary sequence, the sequence encrypts and decrypts communication data in real time, and a unified data encryption transmission method is adopted by both communication receiving and transmitting parties, so that the data transmission security is ensured.

A wireless peripheral device operatively coupled to a wireless dongle of an information handling system includes a microcontroller to receive a polling packet from the operatively coupled wireless dongle, via a wireless peripheral device radio, identifying a selected number of encrypted data packets for a data packet frame. The microcontroller executes code instructions of a wireless input / output protocol authenticated encryption agent with bi-lateral linear-feedback shift register (LFSR) input stream to generate an initial key or a later dynamic key. With the initial key or dynamic key, the encryption system uses a shifting state machine output from each of a first and second LFSR in an encryption algorithm to generate a data packet encryption output value. The data packet is encrypted via an XOR operator with the data packet encryption output value, and each generated data packet encryption output value is subsequently the dynamic key for encryption of subsequent data packets.