121 results about "Linear feedback shift register" patented technology

A wireless peripheral device operatively coupled to a wireless dongle of an information handling system includes a microcontroller to receive a polling packet from the operatively coupled wireless dongle, via a wireless peripheral device radio, identifying a selected number of encrypted data packets for a data packet frame. The microcontroller executes code instructions of a wireless input / output protocol authenticated encryption agent with bi-lateral linear-feedback shift register (LFSR) input stream to generate an initial key or a later dynamic key. With the initial key or dynamic key, the encryption system uses a shifting state machine output from each of a first and second LFSR in an encryption algorithm to generate a data packet encryption output value. The data packet is encrypted via an XOR operator with the data packet encryption output value, and each generated data packet encryption output value is subsequently the dynamic key for encryption of subsequent data packets.

The invention discloses a hyperspectral band selection and extraction system and method based on an FPGA (Field Programmable Gate Array), and mainly solves the problems of high complexity, poor real-time performance, low compressed sensing band selection efficiency and more occupied resources of the existing band selection algorithm. According to the implementation scheme, the method comprises the following steps of: generating data storage and an address by using a three-layer nested counter, generating a storage address of a hyperspectral image, reading an external original hyperspectral image according to the address, and storing the external original hyperspectral image into an RAM (Random Access Memory) for caching; setting an n-order linear feedback shift register, feeding back a polynomial and a seed value, generating a sparse random binary matrix, and linearly outputting a 0-1 random number to a subsequent operation module; and carrying out operation on the input original hyperspectral data and the sparse random binary by adopting a judgment accumulation mode to obtain selected hyperspectral data. According to the method, the number of wavebands needing to select dimension reduction can be flexibly adjusted, internal resource consumption is reasonably reduced, the timeliness of waveband selection in a satellite-borne scene is improved, and the method can be used for efficient spectral information processing of satellite-borne, airborne and other resource-limited platforms.

The invention relates to a controllable scaling convolution processing device and a controllable scaling convolution processing method based on random calculation, which share a pseudo random number sequence generated by a random number source in a random number generation module, so that only one linear feedback shift register is used in one round of convolution calculation, the hardware cost and the calculation overhead are greatly reduced, and the processing efficiency is improved. And meanwhile, the random number generation module performs operations such as shifting and interchanging on the pseudo-random number sequence through shuffling operation, so that the correlation between data is effectively weakened, and the precision error caused by the correlation in random calculation is greatly reduced. In the convolution calculation module, a JK trigger is used for replacing a binary divider to generate a control signal of a multiplexer in convolution calculation, and a large number of AND gates or exclusive-OR gates are not needed, so that the complexity of a convolution calculation architecture is greatly simplified, and the hardware cost, the area occupation and the power consumption are further reduced; and finally, the data processing module completes conversion and recovery of binary numbers.

The invention belongs to the technical field of integrated circuit hardware security, and discloses a double-dynamic key encryption circuit and method for dynamically changing dynamic keys after interpretation, and the circuit comprises an external dynamic key module, an internal dynamic key module and a circuit original logic module. And the external dynamic key module generates a dynamic key signal through the linear feedback shift register unit, and the internal dynamic key module generates a D / T selection signal according to a parity check result of the dynamic key signal to dynamically change the type of a trigger in the state machine. The state machine is divided into a group A and a group B, key updating is triggered at an entrance state through a state detection unit, and it is ensured that the key is still dynamically changed after being interpreted. Through a double-dynamic key mechanism and state machine jump confusion, probe detection and bypass attacks are effectively resisted, and the safety of the circuit is remarkably improved. And when the initial key is wrong, circuit jump is abnormal, so that IP protection is realized. The method has the advantages of high attack resistance, dynamic key change, high security and the like.

An Advanced Encryption Standard (AES) cryptographic system and a method of performing Advanced Encryption Standard (AES) cryptography. The method comprises the steps of performing multiplicative inversion for SubBytes transformation using two forward-reverse linear-feedback shift registers, LFSRs, pairs; and using different respective initialization seeds for the pairs of forward-reverse LFSRs.

The invention discloses an integrated circuit scan chain diagnosis method and system based on an artificial neural network, and the method comprises the steps: firstly, injecting two random faults, namely, buck at-0 and buck at-1, into each scan trigger in an integrated circuit scan chain, and generating a random number through a linear feedback shift register to obtain a random period of the fault; then executing automatic test vector generation to obtain a pattern report containing fault information and a corresponding simulation log; and finally, obtaining an integer fault vector and a label vector through the pattern report and the simulation log, inputting the integer fault vector and the label vector into an artificial neural network for training and verification, and predicting through the trained artificial neural network to obtain a fault position in the integrated circuit scan chain. According to the method, random period faults are generated, abnormal data are eliminated, the artificial neural network model is used, the risk of man-made misjudgment and missing detection is effectively reduced, and accurate prediction is achieved.

The invention relates to the technical field of pseudo-random binary sequence design, in particular to a parallel PRBS generation method and system for testing a multi-protocol high-speed serial transceiver, and the method comprises the steps: setting demand parameters of a pseudo-random binary sequence for testing the multi-protocol high-speed serial transceiver, and enabling the demand parameters to comprise an order, a bit number and a feedback polynomial; constructing a generator matrix for describing state transition of the linear feedback shift register according to the feedback polynomial; according to the bit number of the pseudo-random binary sequence, generating a mapping matrix of the pseudo-random binary sequence through the exponentiation of the generated matrix; based on the mapping matrix and the current beat linear feedback shift register state, outputting a pseudo-random binary sequence meeting the requirement parameters for testing the multi-protocol high-speed serial transceiver. According to the method, parallel generation of any PRBS can be supported, the PRBS parallel implementation logic configuration is simple, the hardware implementation complexity is low, the PRBS output throughput rate is high, and the design requirements of multi-protocol high-speed SerDes can be met.

The invention discloses a high-precision arbitrary carrier generation method based on an FPGA (Field Programmable Gate Array) and an intermediate-frequency DAC (Digital-to-Analog Converter), which comprises the following steps of: when a system needs to execute arbitrary carrier generation, firstly, configuring a carrier frequency needing to be generated through instruction input, and calculating to obtain an equivalent carrier frequency by using an equivalent carrier conversion module based on a Nyquist sampling theorem and an equivalent carrier conversion formula; the phase calibration unit formulates a phase value of each channel, and then performs dynamic phase compensation based on a linear feedback shift register to generate a dynamically compensated phase control word; and finally, the multi-channel waveform generation module generates an equivalent carrier based on the multi-channel parallel DDS. According to the high-precision arbitrary carrier generation method based on the FPGA and the intermediate-frequency DAC, the limitation of the working clock frequency of an existing FPGA device is broken through through cooperative work of the carrier conversion module and the multi-channel waveform generation module, and high-flexibility arbitrary carrier generation is achieved.

The invention discloses data randomization equipment, a data randomization method and a solid state disk, belongs to the field of data randomization, and aims to solve the problem that linear feedback shift registers are low in cost and the randomness of obtained random interference can be improved through cascaded linear feedback shift registers. Therefore, a scrambling module in the data randomization equipment comprises a plurality of cascaded linear feedback shift registers, and the cascaded linear feedback shift registers can output M-bit random interference through each bit output channel according to an input seed of data to be written and a clock signal of a data transmission bus; the random interference is generated through the multi-stage cascaded linear feedback shift registers, so that the randomness of the generated random interference can be greatly improved, the data randomization effect is improved, and the implementation cost is relatively low.

The application discloses a general lightweight hash processing method and system and a storage medium. A linear feedback shift register (LFSR) is selected, and a register state conversion function is used to perform state conversion on the linear feedback shift register (LFSR). The output of the linear feedback shift register (LFSR) is used to initialize the internal state of a hash algorithm in combination with an initialization algorithm. Data for which a hash value needs to be calculated is input, and an update algorithm is used to update the initialized internal state. The data for which the hash value needs to be calculated is filled data. A determination algorithm is used to post-process the updated internal state to generate a final hash value. The application solves the speed and security problems of existing hash processing, is simple to implement, can flexibly adjust the length and starting point, is beneficial to parallel and rapid calculation, has small required storage space, and can dynamically append a hash word to eliminate collision when a hash collision occurs, thereby improving security.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

The invention relates to a linear and probabilistic logarithm counter. In one aspect, a dual scale counter circuit is provided, the dual scale counter circuit comprising: a counter logic unit to store a current counter value; a range determination logic to determine an operating range of the dual scale counter circuit based on the current counter value and a predetermined threshold; and a counter delta logic unit. The counter delta logic is to linearly increase the current counter value for delta events in response to the dual scale counter circuit operating within a linear range, and probabilistically increase the current counter value for delta events in response to the dual scale counter circuit operating within a probability range. The dual-scale counter circuit further includes a linear feedback shift register to generate a random binary bit sequence, a counter delta logic to generate a random binary bit sequence when the dual-scale counter circuit operates within a probability range, and a linear feedback shift register to generate a random binary bit sequence. It is determined whether to increase a current counter value for an incremental event based on the random bin sequence.

The application provides a linear feedback shift register and a construction method, device and equipment and a medium, which can be applied to the technical field of registers. The construction method comprises the following steps: determining information of shift chains required by all to-be-supported algorithms, the to-be-supported algorithms being algorithms required to be supported by the linear feedback shift register; and constructing the linear feedback shift register according to the information of the required shift chains. Compared with a static construction method, the construction method provided by the application is more flexible and can implement multiple algorithms. Compared with a dynamic construction method, the linear feedback shift register obtained by the method provided by the application requires less configuration information, so that the cost is smaller.

The invention discloses a memory with a test function and a test method, the memory comprises a plurality of columns of memory modules and a test circuit, the test circuit at least utilizes n + 1 columns of adjacent target memory modules, n is greater than or equal to 1, at least one row of first memory units and three rows of second memory units are multiplexed in each column of target memory modules, and a NOR gate is arranged in each column of target memory modules. Each NOR gate and the first storage unit and the second storage unit which are multiplexed in the target storage module in the same column form a local XOR module; when the test circuit is used in the test process, the first n columns of local XOR modules in the first direction are used as D triggers in a linear feedback shift register or a multi-input signature register when the test circuit is used for testing. And when the input end of the evaluation circuit in the memory is not provided with a trigger, a linear feedback shift register does not need to be added, so that the hardware overhead is reduced.

The invention relates to a fault detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring an analog voltage signal; the analog voltage signal is generated by performing corresponding XOR operation on the linear feedback shift register module; amplifying and coupling the analog voltage signal, and injecting the amplified and coupled analog voltage signal into a reactor to be tested; acquiring a response voltage signal and a response current signal of the to-be-tested reactor to the analog voltage signal; extracting multi-domain features from the response voltage signal and the response current signal, and coding based on the multi-domain features to obtain a feature fingerprint image; and inputting the feature fingerprint image into a fault identification model to obtain a fault identification result. By adopting the method, the fault type can be identified in time.

The application discloses a kind of cross-scale visual ultra-precision motion measurement device and method, the device includes image sensor, aperture diaphragm, imaging lens group, coaxial light source, beam splitter, positioning platform, encoding plate and DSP and ARM integrated signal processing system.In the method, by selecting the number of linear feedback shift register and period large λ and carrying out periodic coding, after DSP and ARM signal processing system pre-processing operation to image, static random access memory is driven to carry out image caching;Two-dimensional Fourier transform is executed to cached image, and relevant linear phase processing is carried out;According to the phase data obtained by linear phase processing, the corresponding binary sequence on local image is identified;The identified local binary sequence is looked up to the binary sequence of encoding plate and positioned, and according to the phase constant of periodic phase measurement, fine positioning is carried out.

The invention relates to the technical field of digital communication, in particular to an implementation method of an optical transport network pseudo-random sequence parallel scrambling descrambler, which comprises the following steps of: deducing a parallel scrambling code based on an original digital sequence signal of a scrambling code encoding label; designing a frame synchronization scrambler based on the parallel scrambling codes; a frame synchronization descrambling code device is designed based on the parallel scrambling codes, the method is based on a linear feedback shift register (LFSR) circuit, a parallel pseudorandom sequence generation method is achieved through a field programmable gate array (FPGA), the scrambling / descrambling code function of OTN system high-speed code stream (1.25 Gbps to 10 Gbps) data is simply and efficiently achieved through the method, the scrambling / descrambling code function is achieved, and the method is suitable for large-scale popularization and application. By performing modulo 2 operation on the OTUk code stream and the pseudo-random sequence, the frequency spectrum of the digital baseband signal of the OTN system is smooth so as to adapt to the transmission of the baseband system, the transmission performance of the OTN system is improved, and the problems of low efficiency and slow speed of the existing software calculation scrambling method are solved.

The invention discloses a clock signal frequency determination method and a chip, and the method comprises the steps: in response to a frequency detection instruction for a signal of a to-be-detected clock, controlling a linear feedback shift register to start counting the signal of the to-be-detected clock, and controlling an accumulation counter to start counting the signal of a reference clock; if it is determined that the counting end condition is met, the linear feedback shift register and the accumulation counter are controlled to stop counting, and the frequency of the signal of the to-be-tested clock is determined based on the first count value of the linear feedback shift register and the second count value of the accumulation counter. Therefore, the feedback logic circuit of the linear feedback shift register is simple in structure and has simple processing logic, and the processing speed of the counting signal is far higher than that of a common accumulation counter, so that the counting speed of the linear feedback shift register is relatively high; and the counting frequency can be higher than the frequency of the signal of the clock to be detected, so that the high-frequency clock signal can be effectively detected.

Disclosed are a general-purpose lightweight hash processing method, a general-purpose lightweight hash processing system and a storable medium. The method includes: selecting a linear feedback shift register, and performing state transition on the linear feedback shift register by using a register state transition function; initializing an internal state of a hash algorithm by using an output of the linear feedback shift register in combination with an initialize algorithm; inputting data of which a hash value needs to be calculated, and updating the initialized internal state by using an update algorithm, wherein the data of which the hash value needs to be calculated is the padded data; and processing the updated internal state by using a finalize algorithm to generate a final hash value. The problems of speed and security of existing hash processing are solved.

The present invention relates to a target acquisition method and system for a steerable light beam in an optical wireless communication or free space optical communication system, in which the duration during which the steerable light beam of a transmitter must illuminate a light detector at a receiver for acquisition can be minimized, and may allow a slow feedback channel from a receiver to a transmitter. This can be accomplished by transmitting a pseudorandom sequence having the attribute that knowledge of a small number of bits uniquely allows determination of the beam direction in which the steerable beam of the transmitter is received by the receiver. In one example, a linear feedback shift register sequence is a suitable and very efficient choice.

The invention relates to a method for starting a silicon resonance accelerometer based on a pseudo-random number principle, and the method comprises the steps: analyzing the oscillation starting condition of a resonance beam based on a mechanical model of the resonance beam in the silicon resonance accelerometer, and enabling the resonance beam to start oscillation when the frequency of an input signal is close to the resonance peak frequency of the resonance beam; a linear feedback shift register is adopted in a digital circuit to generate pseudo-random number sequence simulation white noise, and the white noise comprises resonance peak frequency; and exciting the resonant beam based on the pseudo-random number sequence, when the amplitude of the silicon resonant accelerometer reaches a preset amplitude, indicating that the resonant beam starts oscillation, and at the moment, switching to use a sinusoidal signal of the phase-locked loop to maintain oscillation of the resonant beam so as to realize self-adaptive starting of the silicon resonant accelerometer. According to the method, resonance beams with different resonance frequencies can be excited to start oscillation, the complexity of the starting process of the silicon resonance accelerometer digital circuit is reduced, the self-adaptive starting capability is improved, and the method has very high engineering application value.

A test and measurement instrument has one or more channels to receive data from a device under test through a test fixture, the data being transmitted by the DUT in accordance with the Universal Serial Bus protocol 3.x, and one or more processors to: acquire a state of a linear feedback shift register (LFSR), extract a known portion of the LFSR as an LFSR value; shift the LFSR value a predetermined number of times to produce a new value of the LFSR, compare the new value of the LFSR to a value of incoming data to determine if the incoming data comprises a potential control code, repeat to acquire a predetermined number of potential control codes, compare them to known control code values to determine if they are valid, and if so, lock a seed used to descramble the remaining incoming data.

The present disclosure provides a computer-implemented method for authenticating devices using an encryption system (30). The method includes receiving an input word (31), obfuscating the input word (31) using a shift register encryption key (51) to obtain a shift register polynomial (41), and obfuscating the input word (31) using a generator encryption key (52) to obtain a generator polynomial (42). The method further includes shifting the shift register polynomial (41) through a Linear Feedback Shift Register (LFSR) (40) for at least one cycle using the generator polynomial (42) to obtain an output polynomial (43), obfuscating the output polynomial (43) using an output encryption key (53) to obtain an output codeword (32), and outputting the output codeword (32) for device authentication.

Cyclic redundancy check (CRC) algorithms are utilized in digital communication and storage systems for error detection. CRC encoding and decoding may be implemented using linear feedback shift registers (LFSRs). To achieve high throughput, a parallel LFSR may be implemented by registers using feedback matrix and pre-processing matrix multiplication. In conventional architectures, a feedback matrix may be decided by look-ahead computations of an FSR, and the corresponding matrix multiplication may contribute to a significant portion of the overall complexity of the LFSR. The methods described herein are provide for searching over a wide range of powers of a companion matrix describing the parallel LFSR in order to minimize the logic gate count required for the feedback matrix multiplication.

One aspect provides a dual-scale counter circuit that includes a counter logic unit for storing the current counter value, a range determination logic unit for determining the operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold, and a counter increment logic unit. The counter increment logic unit is used to linearly increment the current counter value for an increment event in response to the dual-scale counter circuit operating in a linear range, and to probabilistically increment the current counter value for the increment event in response to the dual-scale counter circuit operating in a probabilistic range.The dual-scale counter circuit also includes a linear feedback shift register for generating a random binary bit sequence, on the basis of which the counter increment logic unit is to determine whether the current counter value should be increased for the increment event when the dual-scale counter circuit is operating in the probabilistic range.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

The invention provides an arithmetic square root approximate calculation device and method based on maximum negative correlation, and belongs to the field of integrated circuit design. The circuit comprises a linear feedback shift register, a comparator, a square root calculation unit, a positive correlation median generation unit, a half-value scaling unit, a division unit and a delay unit. According to the arithmetic square root circuit approximate calculation device based on the maximum negative correlation, the minimum obtained mean square error (MSE) can reach 0.0031, and good precision is achieved.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

Disclosed are a general-purpose lightweight hash processing method, a general-purpose lightweight hash processing system and a storable medium. The method includes: selecting a linear feedback shift register, and performing state transition on the linear feedback shift register by using a register state transition function; initializing an internal state of a hash algorithm by using an output of the linear feedback shift register in combination with an initialize algorithm; inputting data of which a hash value needs to be calculated, and updating the initialized internal state by using an update algorithm, wherein the data of which the hash value needs to be calculated is the padded data; and processing the updated internal state by using a finalize algorithm to generate a final hash value. The problems of speed and security of existing hash processing are solved.

The invention discloses a method for accurately calculating a signal code rate. The method comprises the following steps of: constructing a signal receiving model under a multi-path channel; generating a pseudo-random signal sequence by using a linear feedback shift register, fitting a signal receiving model corresponding to each channel path by using the pseudo-random signal sequence, optimizing an attenuation coefficient and delay of the signal receiving model by using a genetic variation algorithm, and outputting an optimal signal receiving model; fourier transform is utilized to obtain a frequency spectrum of the output signal, and the frequency spectrum is detected to obtain a candidate value of a code rate; and filtering a received signal output by the optimal signal receiving model by adopting an adaptive filter, and correcting a candidate value to obtain an accurate code rate. According to the method, the influence of multipath propagation on signals is considered, and calculation errors caused by neglecting the multipath effect are avoided. And in combination with adaptive filtering, the code rate can be corrected and accurately calculated, and the accuracy of code rate calculation is remarkably improved.