462 results about "Linear feedback shift register" patented technology

A data processing apparatus maps input symbols to be communicated onto a predetermined number of carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM carrier signals. The interleaver memory reads-out the data symbols on to the OFDM carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. In order to provide a 4 k mode for an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial (DVB-T) or DVB-Handheld (DVB-H) standards, a generator polynomial for the linear feedback shift register of Ri'[10]=Ri-1'[0]⊕Ri-1'[2] is provided with a permutation order which has been established by simulation analysis to optimise communication performance via typical radio channels.

A built-in self test (BIST) circuit comprising a linear feedback shift register is disclosed. The BIST circuit comprises a controller for controlling a self-testing operation of a memory chip embedded in an integrated circuit, an address generator for generating pseudo-random address patterns under control of the controller, a data generator for producing test data associated with data backgrounds of the address bits under the control of the controller, and a comparator for comparing the test data with memory data output from the memory chip to detect a defect, if any, of the memory chip. The pseudo-random random pattern comprises a single-random pseudo-random address pattern.

In a cryptography system, client and server terminals each generate a private key constituting a randomized compilation of dynamic system parameters. Public keys are then generated based on the private keys, exchanged between the terminals, and used to generate a shared secret. Key stream generators generate a randomized key stream at each terminal using the shared secret, based on self-generating primitive polynomials. Key length is user selected, and may be modified during an ongoing encryption session. The generator includes a plurality of linear feedback shift registers whose lengths are self-configuring based on the user-specified key length. The registers are interconnected so that their output, namely, the key stream, is non-linear and random. Data is converted to binary form and encrypted by XOR'ing the binary-format data with the key stream. The system may be used in both a static secure transfer mode and a dynamic secure real time transfer mode.

Techniques are provided for generating a hash value for searching for substrings in a data stream without reading more than one element (e.g. one byte) at a time. According to one technique, a before a next element is added to an old hash value, the old hash value is circularly shifted one or more bits. The first original element is shifted a number of bits and XOR'ed against the old hash value. The next element is added to the old hash value. In one embodiment, an entry value is retrieved for each element from an index table and the XOR and shift operations are performed on the entry values. According to another technique, each Linear Feedback Shift Register (LFSR) of a plurality of LFSRs read in one element at a time beginning at different offsets. Each LFSR uses the same state machine. The result of reading a number of elements into an LFSR is used as the hash value.

A system and method to generate memory test patterns for the calibration of a delay locked loop (DLL) using pseudo random bit sequences (PRBS) generated through a pair of liner feedback shift registers (LFSR). The generated patterns are implemented on the system data bus as test patterns that closely simulate run-time switching conditions on the system bus, so as to allow more accurate calibration of the DLL. Test data write/read operations may be performed while signals for the test patterns are present on various bit lines in the data bus so as to allow for accurate determination or adjustment of the value for the delay to be provided by the DLL to the strobe signals during memory data reading operations at run time. Memory chips may also be tested over an operating range of values using the generated test patterns.

A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. The linear feedback shift register has twelve register stages with a generator polynomial for the linear feedback shift register of R′_i[11]=R′_i-1[0]R′_i-1[1]R′_i-1[4]R′_i-1[6], and the permutation code forms, with an additional bit, a thirteen bit address. The permutation code is changed from one OFDM symbol to another, thereby providing an improvement in interleaving the data symbols for an 8K operating mode of an OFDM modulated system such as a Digital Video Broadcasting (DVB) standard such as DVB-Terrestrial2 (DVB-T2). This is because there is a reduced likelihood that successive data bits which are close in order in an input data stream are mapped onto the same sub-carrier of an OFDM symbol.

An apparatus and method for generating multiple scrambling codes in an asynchronous mobile communication system. In a scrambling code generating apparatus for generating a current scrambling code and a compressed mode scrambling code for compressed mode transmission in a base station device having a spreader for spreading an input data sequence with one of a plurality of OVSF codes and a scrambler for scrambling the spread data sequence with a primary scrambling code used as a default or one of a plurality of secondary scrambling codes according to the number of mobile stations in communication, a first feedback linear shift register generates an m-sequence from first predetermined initial bits, a second feedback linear shift register generates another m-sequence from second predetermined initial bits, a first adder generates the current scrambling code by adding the outputs of the first and second linear feedback shift registers, a second adder adds the output of the second linear feedback register and an m-sequence one bit delayed from the output of the first linear feedback register, and a third adder adds the output of the second linear feedback register and an m-sequence two bits delayed from the output of the first linear feedback register. Here, the compressed mode scrambling code is one of the outputs of the second and third adders and provided to the scrambler to scramble the spread data sequence.

The invention discloses an RFID lightweight class bidirectional authentication method based on a PUF. Information encryption and pseudo random number generation are carried out through a linear feedback shift register protected through a secret key seed, counterfeit attack can be resisted, a pseudo random number generator does not need to be additionally integrated, and complexity and cost of a label are reduced; in the communication process, all communication information is effectively utilized to carry out authentication, the problem of desynchronization attack of out-of-step information between a reader and the label can be effectively solved through falsification and other means, and security is higher. The method can be widely applied to the internet of things and information security authentication fields.