43 results about "Linear feedback shift register" patented technology

The application discloses a general lightweight hash processing method and system and a storage medium. A linear feedback shift register (LFSR) is selected, and a register state conversion function is used to perform state conversion on the linear feedback shift register (LFSR). The output of the linear feedback shift register (LFSR) is used to initialize the internal state of a hash algorithm in combination with an initialization algorithm. Data for which a hash value needs to be calculated is input, and an update algorithm is used to update the initialized internal state. The data for which the hash value needs to be calculated is filled data. A determination algorithm is used to post-process the updated internal state to generate a final hash value. The application solves the speed and security problems of existing hash processing, is simple to implement, can flexibly adjust the length and starting point, is beneficial to parallel and rapid calculation, has small required storage space, and can dynamically append a hash word to eliminate collision when a hash collision occurs, thereby improving security.

Linear feedback shift registers (LFSRs) are described that are used to generate bounded random numbers (e.g., the range of random numbers is narrower than the range of random numbers generated by a conventional LFSR having the same width). In one embodiment, a bounded LFSR for generating n-bit values includes an m-bit LFSR that ranges over 2 m m random numbers and an n-m-bit LFSR that ranges over 2 n‑m n-m-1-k random numbers. The bounded LFSR further includes logic for skipping over k values in a repeatable sequence of the n-m-bit LFSR, e.g., the logic can be configured during design of the bounded LFSR. The bounded LFSR provides bounded random numbers based on outputs of the m-bit LFSR and the n-m-bit LFSR. In one embodiment, the bounded random numbers generated by the bounded LFSR are used as random addresses in a row hammer mitigation system.

The invention relates to a linear and probabilistic logarithm counter. In one aspect, a dual scale counter circuit is provided, the dual scale counter circuit comprising: a counter logic unit to store a current counter value; a range determination logic to determine an operating range of the dual scale counter circuit based on the current counter value and a predetermined threshold; and a counter delta logic unit. The counter delta logic is to linearly increase the current counter value for delta events in response to the dual scale counter circuit operating within a linear range, and probabilistically increase the current counter value for delta events in response to the dual scale counter circuit operating within a probability range. The dual-scale counter circuit further includes a linear feedback shift register to generate a random binary bit sequence, a counter delta logic to generate a random binary bit sequence when the dual-scale counter circuit operates within a probability range, and a linear feedback shift register to generate a random binary bit sequence. It is determined whether to increase a current counter value for an incremental event based on the random bin sequence.

The application provides a linear feedback shift register and a construction method, device and equipment and a medium, which can be applied to the technical field of registers. The construction method comprises the following steps: determining information of shift chains required by all to-be-supported algorithms, the to-be-supported algorithms being algorithms required to be supported by the linear feedback shift register; and constructing the linear feedback shift register according to the information of the required shift chains. Compared with a static construction method, the construction method provided by the application is more flexible and can implement multiple algorithms. Compared with a dynamic construction method, the linear feedback shift register obtained by the method provided by the application requires less configuration information, so that the cost is smaller.

The invention relates to a fault detection method and device, computer equipment, a computer readable storage medium and a computer program product. The method comprises the following steps: acquiring an analog voltage signal; the analog voltage signal is generated by performing corresponding XOR operation on the linear feedback shift register module; amplifying and coupling the analog voltage signal, and injecting the amplified and coupled analog voltage signal into a reactor to be tested; acquiring a response voltage signal and a response current signal of the to-be-tested reactor to the analog voltage signal; extracting multi-domain features from the response voltage signal and the response current signal, and coding based on the multi-domain features to obtain a feature fingerprint image; and inputting the feature fingerprint image into a fault identification model to obtain a fault identification result. By adopting the method, the fault type can be identified in time.

The application discloses a kind of cross-scale visual ultra-precision motion measurement device and method, the device includes image sensor, aperture diaphragm, imaging lens group, coaxial light source, beam splitter, positioning platform, encoding plate and DSP and ARM integrated signal processing system.In the method, by selecting the number of linear feedback shift register and period large λ and carrying out periodic coding, after DSP and ARM signal processing system pre-processing operation to image, static random access memory is driven to carry out image caching;Two-dimensional Fourier transform is executed to cached image, and relevant linear phase processing is carried out;According to the phase data obtained by linear phase processing, the corresponding binary sequence on local image is identified;The identified local binary sequence is looked up to the binary sequence of encoding plate and positioned, and according to the phase constant of periodic phase measurement, fine positioning is carried out.

The invention relates to a method for starting a silicon resonance accelerometer based on a pseudo-random number principle, and the method comprises the steps: analyzing the oscillation starting condition of a resonance beam based on a mechanical model of the resonance beam in the silicon resonance accelerometer, and enabling the resonance beam to start oscillation when the frequency of an input signal is close to the resonance peak frequency of the resonance beam; a linear feedback shift register is adopted in a digital circuit to generate pseudo-random number sequence simulation white noise, and the white noise comprises resonance peak frequency; and exciting the resonant beam based on the pseudo-random number sequence, when the amplitude of the silicon resonant accelerometer reaches a preset amplitude, indicating that the resonant beam starts oscillation, and at the moment, switching to use a sinusoidal signal of the phase-locked loop to maintain oscillation of the resonant beam so as to realize self-adaptive starting of the silicon resonant accelerometer. According to the method, resonance beams with different resonance frequencies can be excited to start oscillation, the complexity of the starting process of the silicon resonance accelerometer digital circuit is reduced, the self-adaptive starting capability is improved, and the method has very high engineering application value.

The present disclosure provides a computer-implemented method for authenticating devices using an encryption system (30). The method includes receiving an input word (31), obfuscating the input word (31) using a shift register encryption key (51) to obtain a shift register polynomial (41), and obfuscating the input word (31) using a generator encryption key (52) to obtain a generator polynomial (42). The method further includes shifting the shift register polynomial (41) through a Linear Feedback Shift Register (LFSR) (40) for at least one cycle using the generator polynomial (42) to obtain an output polynomial (43), obfuscating the output polynomial (43) using an output encryption key (53) to obtain an output codeword (32), and outputting the output codeword (32) for device authentication.

Cyclic redundancy check (CRC) algorithms are utilized in digital communication and storage systems for error detection. CRC encoding and decoding may be implemented using linear feedback shift registers (LFSRs). To achieve high throughput, a parallel LFSR may be implemented by registers using feedback matrix and pre-processing matrix multiplication. In conventional architectures, a feedback matrix may be decided by look-ahead computations of an FSR, and the corresponding matrix multiplication may contribute to a significant portion of the overall complexity of the LFSR. The methods described herein are provide for searching over a wide range of powers of a companion matrix describing the parallel LFSR in order to minimize the logic gate count required for the feedback matrix multiplication.

One aspect provides a dual-scale counter circuit that includes a counter logic unit for storing the current counter value, a range determination logic unit for determining the operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold, and a counter increment logic unit. The counter increment logic unit is used to linearly increment the current counter value for an increment event in response to the dual-scale counter circuit operating in a linear range, and to probabilistically increment the current counter value for the increment event in response to the dual-scale counter circuit operating in a probabilistic range.The dual-scale counter circuit also includes a linear feedback shift register for generating a random binary bit sequence, on the basis of which the counter increment logic unit is to determine whether the current counter value should be increased for the increment event when the dual-scale counter circuit is operating in the probabilistic range.

The invention provides a self-anti-S box construction method and system based on m-sequence generation and logic optimization, and belongs to the technical field of cryptography and hardware security. The method comprises the following steps: firstly, constructing an n-level linear feedback shift register according to a set S box number n and a primitive polynomial, generating an m sequence in a non-all-zero initial state, and adding an all-zero state at the tail; a self-reverse S box lookup table is constructed through a symmetric mapping strategy, so that the ith element in the sequence and the element at the symmetric position form mapping, and the same S box is used for encryption and decryption. Thirdly, the lookup table serves as a Boolean function truth table, is simplified into a simplest expression through a logic minimization algorithm and is decomposed into a layered logic circuit; during actual processing, N data blocks are converted into a bit plane format from block type storage, then parallel operation is carried out through a hierarchical circuit, and finally a result is transposed back to block type storage. According to the method, the same S box hardware module can be reused in the encryption and decryption process, and hardware resources are remarkably saved.

The invention discloses a bit stream random number generator, a random multiplication circuit and a calculation method, and belongs to the technical field of integrated circuits. A reverse signal end of a highest-bit D trigger Ln of a linear feedback shift register is respectively connected with a NOR gate and a NAND gate, and output signal ends of n-1 low-bit triggers in the linear feedback shift register are respectively connected with a comparator; a sign bit xn of an n-bit binary number corresponding to the target numerical value is input into the NOR gate and the NAND gate respectively; bits corresponding to the amplitude bits of the n-bit binary number are input to the comparator; the comparator and the NOR gate are connected with the OR gate; the OR gate and the NAND gate are connected with the AND gate. In the application, the two bit stream random number generators can generate two bit streams with low correlation, so that the numerical value shown by the bit stream obtained by carrying out multiplication (namely XNOR operation) on the two bit streams is closer to the product result of two target numerical values.

The application provides a key generation method, a register address scrambling method, a descrambling method and a chip. The key generation comprises generating a periodic pseudo-random sequence by using a linear feedback shift register, and generating an index value based on an original address; a sub-sequence is intercepted from the pseudo-random sequence according to the index value, and the bit width of the sub-sequence is the same as that of the original address; and a key is generated according to the sub-sequence and a static seed. The application utilizes a dynamic index mechanism, that is, the low bits of the original address are used as a variable index, to solve the problem of static mode address leakage. In addition, the application also realizes address consistency, that is, the static seed is used to ensure scrambling consistency of chips of the same type, and also realizes low resource consumption. The linear feedback shift register (PRBS) algorithm and the lightweight XOR operation are used, and compared with other complex encryption and hardware-level encryption, low delay and low consumption are brought, and the method is more suitable for register-level access.

The application discloses a kind of cable quality evaluation method and device for television serial data interface, it is related to communication data processing technical field, the present application generates pseudo-random binary sequence and ill-conditioned code by linear feedback shift register, after being selected by gating switch, it is converted into serial data by serializer.The amplitude of serial data is adjusted by adjustable attenuator, input target cable transmission, after transmission, signal is processed by rate adaptive equalizer, and is parsed into parallel data by deserializer.Pseudo-random code and ill-conditioned code checker are used for error rate analysis, from HD-SDI gradually upgrade to 3G-SDI, UHD-SDI, whether cable meets corresponding rate requirement is judged by double detection logic.Record the initial attenuation value of error rate under different rates, construct model based on attenuation formula, calculate β and γ to judge the theoretical feasibility of 3G-SDI, UHD-SDI, if feasible, then measured, if not feasible, then calculate the maximum transmission distance, finally generate evaluation information containing applicable rate etc..

Provided in the present disclosure are a test circuit, a test method and a chip stack structure. The test circuit is applied to a logic chip, and comprises a first register module, which is electrically connected to a first path and a first through silicon via of the logic chip, wherein when a first test enable signal is at a first level, the first register module is configured as a linear feedback shift register, and receives a first test signal at a first speed by means of the first path; and when the first test enable signal is at a second level, the first register module is configured as an ordinary shift register, and serially outputs values in the first register module on the basis of a serial test protocol, so as to obtain a first test result signal. The present disclosure at least facilitates a speed test of a logic chip before stacking, thereby saving on test costs.

Electronic devices, circuitry, and methods are provided to efficiently generate a dither signal. An electronic device may include an output device, such as a speaker, to output a media signal, such as an audio signal, based on dithered media data, such as dithered audio data. The electronic device may include dithering circuitry to generate a dither signal, based on a first pseudorandom signal from a first linear feedback shift register and a second pseudorandom signal from a second linear feedback shift register, to add to the media signal to generate the dithered media signal.

A wireless peripheral device operatively coupled to a wireless dongle of an information handling system includes a microcontroller to receive a polling packet from the operatively coupled wireless dongle, via a wireless peripheral device radio, identifying a selected number of encrypted data packets for a data packet frame. The microcontroller executes code instructions of a wireless input / output protocol authenticated encryption agent with bi-lateral linear-feedback shift register (LFSR) input stream to generate an initial key or a later dynamic key. With the initial key or dynamic key, the encryption system uses a shifting state machine output from each of a first and second LFSR in an encryption algorithm to generate a data packet encryption output value. The data packet is encrypted via an XOR operator with the data packet encryption output value, and each generated data packet encryption output value is subsequently the dynamic key for encryption of subsequent data packets.

A data encryption method using linear-feedback shift registers (LFSRs) is disclosed. The method includes identifying one or more objects each of which comprises a sequence of object bits, and using each object to generate a plurality of logic blocks by: creating an LFSR seed comprising at least a portion of the object bits of the object, wherein the LFSR seed provides an initial state of an LFSR; implementing the LFSR to generate a plurality of LFSR outputs; and using the LFSR outputs to generate the logic blocks. The method also includes encrypting a plurality of data blocks in accordance with an encryption scheme that applies a screen and the LFSR-generated logic blocks. The encrypted data blocks may then be decrypted in accordance with a decryption scheme that applies an inverse screen and the same LFSR-generated logic blocks that were used in the encryption scheme.

The application relates to the technical field of data transmission, and discloses a cross-device data transmission method and device. In the cross-device data transmission, the working frequency of a first device performing a sending operation is higher than the highest working frequency of a second device, and the data interface bit width used by the first device for sending is smaller than the data interface bit width of the second device. The method is applied to the first device and comprises the following steps: dividing original data into at least two sub-data segments with equal bit widths; configuring a first linear feedback shift register with the same number of sub-data segments to form a first driving chain; wherein the initial state of each first linear feedback shift register in the first driving chain except the first stage is determined by the parallel data output by the adjacent previous-stage first linear feedback shift register in the current main clock cycle; performing a scrambling operation on the corresponding sub-data segment based on each first linear feedback shift register to obtain a scrambled sub-data segment, and sending the scrambled sub-data segment to the second device.

The utility model relates to the technical field of circuits, in particular to a general computing circuit and computing equipment for a liquid state machine and Isin annealing. Wherein the general calculation circuit comprises a processor, a selector, a linear feedback shift register, a weight memory, a membrane potential-local field calculation array, a membrane potential-local field memory, a comparator array, a neuron-spin state memory, a pulse counter, a dynamic multiply-accumulate array, an index calculation array and an output module; according to the general calculation circuit provided by the utility model, the same hardware circuit is shared to accelerate the processing of the liquid state machine and the Isin annealing task, so that not only can the identification, classification and prediction problems be quickly processed, but also the combinatorial optimization problem can be quickly solved.

The embodiment of the invention provides an unmanned aerial vehicle interference method and device based on the software radio technology, and the method comprises the steps: receiving a synchronization signal of a satellite navigation system, generating a reference clock signal based on the synchronization signal, receiving an air interface radio frequency signal, and carrying out the analysis of the radio frequency signal according to a pre-training deep learning model, the method comprises the following steps: obtaining unmanned aerial vehicle information, inputting the unmanned aerial vehicle information as a state space into a pre-trained Markov decision process model to obtain register optimization parameters output by a corresponding model, configuring a linear feedback shift register according to the parameters, and driving the configured linear feedback shift register according to a reference clock signal to obtain a pre-trained Markov decision process model. And determining a corresponding baseband noise signal, adjusting the amplitude of the baseband noise signal according to a preset confrontation mode, modulating the noise signal to a preset carrier signal to obtain an interference signal, performing time domain superposition on the interference signals for different unmanned aerial vehicle navigation systems, and then transmitting the interference signals to an air interface, so that the unmanned aerial vehicle defense security can be improved.

The application discloses a lightweight encryption method and device based on an ARX module. The method comprises the following steps: storing a master key in a linear feedback shift register (LFSR); taking four beats of LFSR precession as one round and generating a sub-key; generating 32 sub-keys in sequence to form a sub-key sequence; obtaining plaintext to be encrypted, and grouping the plaintext to be encrypted; performing 32 rounds of encryption on each group of plaintext based on the sub-key sequence; merging the encrypted ciphertext of each group of plaintext to obtain the overall encrypted ciphertext corresponding to the plaintext to be encrypted; and obtaining the overall encrypted ciphertext by a decryption party, grouping the overall encrypted ciphertext, and taking each group to include 128 bits; and performing a decryption operation on each group of ciphertext based on the sub-key sequence. The application can meet the high efficiency in the resource-limited scene, and can resist the security threats caused by differential analysis and linear analysis.

This invention relates to the field of queue management technology for Ethernet switching chips, specifically to a method for managing the probabilistic random drop of packets in a queue, applied to multi-service queue management in Ethernet switching chips. The method configures drop thresholds, sampling periods, prediction step sizes, congestion change rate thresholds, and target drop ratios for each service queue; calculates the congestion change rate and predicted queue length based on the real-time average queue length and its historical sequence, and determines the direction of threshold adjustment accordingly; determines the adjustment step value based on the deviation between the actual drop ratio and the target drop ratio, and updates the minimum and maximum drop thresholds. When packets are enqueued, a pseudo-random number is generated using a linear feedback shift register, and combined with the congestion change rate to generate a dynamic comparison threshold to complete the random drop judgment. This invention can improve queue congestion response speed and reduce hardware storage resource consumption.

The invention relates to a pipeline tight coupling hardware-in-loop verification method, device and equipment and a medium, and the method comprises the steps that an RTL coprocessor recognizes to-be-executed arithmetic logic according to an instruction type identifier, and executes corresponding operation based on a first source operand and a second source operand to generate an operation result, recording an actual execution cycle number corresponding to the instruction type identifier through a cycle counter, and marking as a time sequence violation if the total execution cycle number of the instruction type identifier reaches or exceeds a theoretical execution cycle in combination with a pseudo-random number generated by a 16-bit linear feedback shift register; the RTL coprocessor returns the operation result and the total execution cycle number to the RI SCV-VP virtual prototype, in the write-back stage, the operation result is written back to the target register according to the target register identification operation result, and an advent () function of the assembly line time sequence model is called to verify the returned total execution cycle number so as to update the total cycle number of the system. According to the method, the simulation speed is remarkably improved, and a large amount of hardware resource consumption is not additionally increased.

The invention discloses a lightweight encryption method and device based on an ARX module. Comprising the following steps: storing a master key in a linear feedback shift register (LFSR); four times of precession of the LFSR are recorded as one round, and a sub-key is generated; forming a sub-key sequence by 32 sub-keys generated in sequence; obtaining plaintexts to be encrypted, and grouping the plaintexts to be encrypted; performing 32 rounds of encryption on each group of plaintexts based on the sub-key sequence; combining the encrypted ciphertext of each group of plaintexts to obtain an overall encrypted ciphertext corresponding to the to-be-encrypted plaintexts; the decryption party obtains the overall encrypted ciphertext and groups the overall encrypted ciphertext, and each group comprises 128 bits; and performing decryption operation on each group of ciphertext based on the sub-key sequence. According to the method, high efficiency in a resource-limited scene can be met, and security threats caused by differential analysis and linear analysis can be resisted.

The invention discloses a configuration area analysis and fault thermal injection system for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array), and relates to online reliability evaluation of reconfigurable devices. The system is composed of a configuration area analysis unit and a configuration area fault thermal injection unit, wherein the configuration area analysis unit adaptively calibrates read-back delay through an ICAP interface, analyzes a device frame structure and establishes an effective frame address set; and the single event upset equivalent injection module randomly selects a target frame / bit based on a linear feedback shift register, realizes single event upset equivalent injection by using a configuration register through an ICAP interface, and completes result comparison and repair to form a closed-loop process of injection-detection-repair. The method has the advantages of being high in portability, accurate in positioning, high in injection throughput, capable of supporting batch automation and the like, and is suitable for aerospace, industrial control and other scenes with requirements for online reliability evaluation and reinforcement design.

One aspect provides a dual-scale counter circuit that includes a counter logic unit to store a current counter value, a range-determination logic unit to determine an operating range of the dual-scale counter circuit based on the current counter value and a predetermined threshold value, and a counter-increment logic unit. The counter-increment logic unit is to increment the current counter value linearly for an increment event in response to the dual-scale counter circuit operating in a linear range and increment the current counter value probabilistically for the increment event in response to the dual-scale counter circuit operating in a probabilistic range. The dual-scale counter circuit further includes a linear-feedback shift register to generate a random binary bit sequence, based on which the counter-increment logic unit is to determine whether to increase the current counter value for the increment event when the dual-scale counter circuit operates in the probabilistic range.

The invention provides a key generation method, a register address scrambling method, a register address descrambling method and a chip. The key generation comprises the following steps: generating a periodic pseudo-random sequence by adopting a linear feedback shift register, and generating an index value based on an original address; intercepting a subsequence from the pseudorandom sequence according to the index value, wherein the bit width of the subsequence is the same as that of the original address; and generating a key according to the sub-sequence and the static seed. According to the scheme, the problem of static mode address leakage is solved by using a dynamic index mechanism, namely taking a low bit of an original address as a variable index, in addition, encryption address consistency is also realized, namely, the scrambling consistency of chips of the same model is ensured by using a static seed, and low resource overhead is also realized. Compared with other complex encryption and hardware-level encryption, a linear feedback shift register (PRBS) algorithm and lightweight XOR operation are utilized, low delay and low consumption are brought, and the method is more suitable for register-level access.

The embodiment of the application provides a synchronization header expansion method and device for satellite positioning terminal uplink signals, and relates to the technical field of satellite positioning. The method comprises the following steps: obtaining a power amplifier pre-starting time, a code rate of a to-be-sent data segment, an initial phase code chip sequence, and a preset polynomial of a linear feedback shift register; determining a target total code chip quantity according to the power amplifier pre-starting time and the code rate; recursively obtaining a plurality of target code chips according to the preset polynomial of the linear feedback shift register and the initial phase code chip sequence, and recording each target code chip one by one until the number of recorded code chips reaches the target total code chip quantity, thereby obtaining a target code chip sequence; and modulating the target code chip sequence and a preset pseudo-synchronization header to obtain a synchronization header of the to-be-sent data segment. The synchronization header obtained by the method can avoid single-tone interference caused by a single carrier while starting the antenna power amplifier of an open power detection type antenna.

A data encryption method using linear-feedback shift registers (LFSRs) is disclosed. The method includes identifying one or more objects each of which comprises a sequence of object bits, and using each object to generate a plurality of logic blocks by: creating an LFSR seed comprising at least a portion of the object bits of the object, wherein the LFSR seed provides an initial state of an LFSR; implementing the LF SR to generate a plurality of LFSR outputs; and using the LFSR outputs to generate the logic blocks. The method also includes encrypting a plurality of data blocks in accordance with an encryption scheme that applies a screen and the LFSR-generated logic blocks. The encrypted data blocks may then be decrypted in accordance with a decryption scheme that applies an inverse screen and the same LFSR-generated logic blocks that were used in the encryption scheme.