The application provides a VLIW architecture compilation optimization method, device, equipment, medium and product, the method comprises: generating a VLIW instruction
package sequence, and repeating the VLIW instruction
package sequence at least three times to identify a repeated pattern;Based on the predetermined operation constraint and instruction constraint, the CP-SAT scheduler is used to preliminarily schedule the VLIW instruction
package sequence, obtain a preliminary scheduling result, freeze part of the preliminary scheduling result, and perform secondary scheduling for the register number constraint to obtain an optimized scheduling result;From the optimized scheduling result, the smallest repeating unit, the leading code and the trailing code are identified, and auxiliary control instructions are added to the key execution nodes of the smallest repeating unit to form an optimized loop mode;Combining multiple optimized loop
modes and
tensor control logic, a
tensor operation
instruction sequence is generated. Thus, the instruction
packaging problem in GEMM calculation under the light
feather architecture is effectively solved, and the efficiency of GEMM calculation is effectively improved.