134results about "Digital function generators" patented technology

The invention relates to a square wave generation method and system based on a DDS signal transmitter, and belongs to the technical field of digital electronic signal synthesis. The method comprises the following steps: calculating a digital analog signal sampling frequency based on a square wave output frequency set by a user, and obtaining a digital fundamental frequency phase signal according to a phase-locked loop precision range; mapping the digital fundamental frequency phase signal into a sinusoidal amplitude signal according to a digital phase accumulation mechanism to obtain a digital-analog conversion clock, binarizing the sinusoidal amplitude signal, and outputting a square wave output period; dividing a square wave output period into a low level region and a high level region according to the precision range of the phase-locked loop, reading a square wave output frequency set by a user through a random storage address, and outputting a non-offset phase-locked square wave; and constructing an error accumulation self-checking architecture to calculate a frequency control word, and when detecting that the frequency control word has a decimal discarding error, recalculating the frequency control word.

The invention relates to the technical field of signal generation, and discloses a signal generation system and method, and the system comprises a first signal generation module; the second signal generation module comprises an analog signal generation unit and a signal copying unit; the signal mixing module comprises an analog frequency mixing unit, a digital frequency mixing unit and a signal switching unit; the output end of the analog signal generation unit is connected with the input end of the analog frequency mixing unit; the first end of the signal copying unit is connected with the clock signal output end of the analog signal generating unit, the second end is connected with the mixing input end of the analog signal generating unit, and the third end is connected with the first end of the signal switching unit; the second end of the signal switching unit is connected with the output end of the analog frequency mixing unit, and the third end is connected with the input end of the digital frequency mixing unit. Therefore, a direct digital frequency synthesizer in the analog signal generation unit is calibrated when the clock signal is switched to, and spurious signals are eliminated based on a calibration result when the clock signal is switched to the analog local oscillator signal.

The utility model discloses a circuit system of a high-voltage signal generator. The circuit system comprises a DDS main control circuit, a filter circuit, an operational amplifier circuit, a level conversion circuit, a power supply circuit and a crystal oscillator circuit, the output end of the DDS main control circuit is sequentially connected with the filter circuit and the operational amplifier circuit; the operational amplifier circuit is connected with the power supply circuit and the peripheral port; the DDS main control circuit is also respectively connected with the power supply circuit and the crystal oscillator circuit; the level conversion circuit is connected with the crystal oscillator circuit, the DDS main control circuit and the external power supply circuit; the power supply circuit is connected with an external power supply circuit. According to the scheme, numerous application requirements of high-voltage and high-precision signals can be met.

A computer system is presented configured and operable as a library constructor for use in extracting one or more parameters of a patterned structure from real time measured data obtained on said structure. The system comprises: data input utility for receiving input data comprising preliminary measured data obtained from at least a part of a structure, and comprising data indicative of user-defined quality of measurement results (QOR); and a data processor.

The invention discloses a closed-loop adaptive generative adversarial network filter. A test and measurement system includes: a plurality of nodes, one or more nodes including sensors configured to receive signals; one or more generative adversarial network (GAN) models; one or more signal generators configured to generate and transmit signals; and one or more processors configured to execute the code to cause the one or more processors to receive a request for a signal having a signal profile from one of the plurality of nodes, transmit the signal profile and the request to one of the one or more GAN models, receive a matching signal profile that matches the signal profile, and transmit the matching signal profile to the one of the one or more GAN models. And transmit the matching signal profile to one of the one or more signal generators to generate and transmit a matching signal.

The application discloses a kind of pulse shaping method and system of nuclear signal, belong to signal processing technical field, for the problems of existing pulse signal width in prior art Widening, thereby increasing the accumulation event, and there is no better anti-noise effect to Gaussian white noise, the present application includes: the output signal of detector is acquired, and output signal is structured into digital function signal;The Z transform is carried out after the discrete of the digital function signal, and output Z transform signal is obtained;Definition input signal is exponential signal, and the Z transform is carried out to the exponential signal, and input Z transform signal is obtained;According to the input Z transform signal and the output Z transform signal, the transfer function of input signal pulse shaping is obtained;The inverse Z transform is carried out to the transfer function, and the pulse shaping signal of input signal is obtained, and its time domain expression.The purpose is: the pulse shaping signal obtained has better signal-to-noise ratio, and it is convenient to obtain amplitude.

This disclosure presents a method for constructing and parsing signal event descriptors for electromagnetic environment simulation. The construction method includes: acquiring an electromagnetic scene simulation description file; extracting at least one set of group-level control parameters and at least one set of service signal parameters constrained by the group-level control parameters from the electromagnetic scene simulation description file; performing quantization encoding conversion on the group-level control parameters and service signal parameters to obtain integer parameters recognizable by the signal generation hardware device; encapsulating the integer group-level control parameters and integer service signal parameters into group header frames and member frames, respectively; sequentially combining the group header frames and member frames with control constraints to the group header frames to generate signal event descriptor groups; and sequentially sending the signal event descriptor groups, frame by frame, to the signal generation hardware device. This method achieves standardized, structured construction, and ordered transmission of signal parameters through grouped encapsulation and integer quantization encoding.

The present application provides a waveform output method, device, hardware equipment and computer readable storage medium, the hardware equipment stores the waveform segment set sent by the software equipment, the waveform segment set includes at least one waveform segment, each waveform segment corresponds to a label respectively, and the method comprises the following steps: receiving the waveform combination mode sent by the software equipment, wherein the waveform combination mode is obtained by arranging the label of each waveform segment by the software equipment; receiving the instruction package sent by the software equipment, and outputting any waveform corresponding to the waveform combination mode based on the instruction package. The method only needs to obtain different waveform combination modes in the case of using the same waveform segment set, so as to realize the change of outputting any waveform. For the hardware equipment, only the output waveform combination mode with small update data amount sent by the software equipment needs to be received to change the output any waveform, so that the output efficiency of any waveform can be effectively improved.

A circuit for transmitting an n-bit phase value between circuits includes a system clock input, an n-bit phase value generator coupled to the system clock input that generates a phase value output and an edge output indicating that the phase output value is valid, a latched clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to a control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to an output of the variable phase delay circuit, a clock input coupled to a latched clock output of the variable output clock delay circuit, and a phase out output.

A graph processing core includes a plurality of processing pipelines and an interrupt controller unit. Each processing pipeline executes one or more threads and includes, for each thread, a register indicating a currently executing program counter vector and another register indicating an interrupt or exception handler vector. The interrupt controller unit may receive interrupt or exception notifications from the processing pipelines, determine a handler vector based on the notification and a set of registers of the interrupt controller unit, and transmit the handler vector to the processing pipeline that issued the interrupt or exception notification. Further, the issuing pipeline may receive the handler vector from the interrupt controller unit, write a value in the first register into the second register, write the handler vector into the first register, and invoke an interrupt or exception hander based on the value written into the first register.

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

The invention relates to a YOLO v3 post-processing hardware acceleration method based on a look-up table method, which comprises the following steps of: 1) establishing two look-up tables according to two operators of sigmoid and exp functions involved in a decoding calculation process; 2) analyzing the required storage space according to the quantization bits and the network structure; 3) distributing a corresponding BRAM storage block for the lookup table according to the required storage space; 4) calculating the data to be decoded, and putting a calculation result into a lookup table; 5) inputting to-be-decoded data, putting the to-be-decoded data into the cache unit, and arranging the to-be-decoded data; 6) reading data to be decoded, and searching corresponding calculation data from the lookup table; 7) inputting the calculation data into a parallel calculation unit to obtain decoding data; and 8) putting the decoded data back to the initial position in the cache unit. According to the method, the lookup table is established, the to-be-decoded data in YOLO v3 post-processing is subjected to decoding calculation, post-processing calculation is completed under the condition that few storage resources are used, the hardware scale is remarkably reduced, and the post-processing efficiency is improved.

This application discloses a precision capacitance sensing system, comprising a modulation signal source, a sensitive probe, a differential transformer bridge, a signal amplification link, an analog multiplier, and a low-pass filter circuit, all connected in sequence. It also includes a demodulation reference signal source, the output of which is connected to the second input of the analog multiplier. The demodulation reference signal source is used to generate a multi-frequency combination demodulation reference signal, which is composed of a fundamental frequency component and at least two harmonic components superimposed. This invention also discloses a precision capacitance sensing method. By employing a specially designed demodulation reference signal, this application ensures that the system output remains constant within a continuously varying range of the demodulation phase difference, thereby achieving complete insensitivity to phase difference fluctuations and effectively overcoming the performance bottleneck that has long constrained high-precision capacitance sensing.

The invention discloses a noise frequency modulation signal generation device, which is realized based on a field programmable gate array (FPGA), and adopts the following method steps: S1, in the FPGA, constructing an arbitrarily distributed random number generator to obtain random numbers conforming to distribution; s2, linearly mapping the obtained random number into a frequency modulation noise bandwidth by using a linear mapping method to obtain a random frequency conforming to Gaussian distribution; and S3, converting the obtained random frequency into frequency modulation noise by using a direct digital frequency synthesis technology. Complex linear algebraic operation is simplified into integer addition, subtraction and shifting, FPGA parallelism and special hardware resources are fully utilized, high speed, low resources and high statistical quality are considered, and a reliable hardware noise source is provided for scenes such as communication simulation and radar interference.

Systems and methods for providing an S-box. The methods comprise: implementing a plurality of layers on a field programmable gate array, wherein each of the layers comprises a substitution sublayer and a mixing sublayer. The substitution sublayer comprises a plurality of μ-boxes that are each configured to perform a different randomly chosen non-linear bijective mapping from GF(24) to GF(24). The mixing sublayer is configured to (i) compute a plurality of product terms each representing a product of an element of a maximum distance separable matrix M and an output from one of the plurality of μ-boxes, and (ii) compute a plurality of column vector elements each comprising a sum of respective ones of the plurality of product terms.

Computer-implemented technology mapping of a circuit design includes, for a node of a circuit design, generating a plurality of regular cuts and a plurality of super cuts. A regular cut subset that is a subset of the plurality of regular cuts having M highest priorities and a super cut subset that is a subset of the plurality of super cuts having N highest priorities are generated. Each super cut that is incompatible with a cascaded lookup-table (LUT) circuit structure is discarding from the super cut subset. A cut from a group of cuts including the regular cut subset and the super cut subset is selected to implement a portion of the circuit design including the node.

The invention discloses a thread defect detection instrument based on electromagnetic pulse eddy current, which belongs to the field of electromagnetic pulse eddy current nondestructive testing, and comprises a detection probe shell, an array detection coil, a DDS direct digital frequency synthesis circuit, a power amplification circuit, a signal conditioning circuit, a data acquisition circuit and a communication circuit, the detection probe shell is filled with electronic pouring sealant; the array detection coil is arranged in the detection probe shell, the DDS direct digital frequency synthesis circuit is electrically connected with the power amplification circuit, the power amplification circuit is electrically connected with an excitation coil of the array detection coil, a receiving coil of the array detection coil is electrically connected with the signal conditioning circuit, and the signal conditioning circuit is electrically connected with the data acquisition circuit. The data acquisition circuit is electrically connected with the communication circuit, and the communication circuit is used for establishing data interaction with an external upper computer. According to the invention, defects with different depths on the thread surface and the near surface can be detected, and different detection requirements can be met.

Approaches are disclosed for generating high voltage sinusoidal signals whose output voltage can be adjusted rapidly, without introducing high frequency artifacts on the output. When these approaches are used, stronger electric fields can be applied to the tumor for a higher percentage of time, which can increase the efficacy of TTFields therapy. In some embodiments, this is accomplished by preventing adjustments to a DC power source during times when the output of that DC power source is powering the output signal. In some embodiments, this is accomplished by synchronizing the operation of an AC voltage generator and an electronic switch that is connected to the output of the AC voltage generator.

To obtain SNRs needed for high MCSs.SOLUTION: This disclosure relates to performing a first encoding operation on data bits of a code block to shape the amplitudes of resultant symbols such that the amplitudes have a non-uniform distribution. In some aspects, the probabilities associated with the respective amplitudes generally increase with decreasing amplitude. For example, the non-uniform distribution of the amplitudes of the symbols may be approximately Gaussian. In some aspects, the first encoding operation is or includes a prefix encoding operation having an effective coding rate greater than 0.94 and less than 1. The first encoding operation is followed by a second encoding operation that also adds redundancy but does not alter data bits themselves. In some aspects, the second encoding operation is or includes a low-density parity-check (LDPC) encoding operation associated with a coding rate greater than 5 / 6.SELECTED DRAWING: Figure 12

The invention provides an FPGA-based programmable periodic pulse signal generation method and application thereof, and belongs to the technical field of electronic measurement. In order to solve the problems that the large dynamic range and the high resolution are difficult to consider at the same time and hardware resources are consumed synchronously by multiple channels in the prior art, according to the method, coarse delay is achieved through FPGA system clock counting, and next pulse parameters are calculated through accumulation of remaining decimal parts; picosecond-level fine delay is realized by constructing a three-level cascade architecture consisting of a lookup table, a coarse carry chain and a fine carry chain; and XOR synthesis waveforms after rising edges and falling edges are independently generated respectively. In addition, the inter-channel transmission delay difference is compensated by correcting the initial calculation parameters. According to the multi-channel pulse signal generation circuit, high-precision, low-jitter and strictly-aligned-phase multi-channel pulse signals can be generated only by utilizing pure logic resources of the FPGA.

This bidirectional logic element is provided with: a function / inverse function control unit; a forward input unit; a forward information transmission unit; a reverse input unit; a reverse information transmission unit; a bidirectional function operation unit that performs a forward logical operation and also performs a reverse operation; a forward function transfer unit; and an inverse function transfer unit. The arithmetic device and the arithmetic method use the bidirectional logic element.

This application provides an output amplifier circuit and an arbitrary waveform generator, belonging to the field of electronic circuit technology. The output amplifier circuit includes: a radio frequency amplifier circuit, including a first common-emitter amplifier sub-circuit and a second common-emitter amplifier sub-circuit, for amplifying high-frequency signals in the AC input signal from the input node; the second common-emitter amplifier sub-circuit includes a second transistor, the collector of which is connected to the output node through a current-sampling resistor; an output bias voltage circuit for superimposing an output bias voltage onto the output node; a static bias voltage circuit for providing a static bias voltage to the second transistor and outputting a reference voltage to the integrator circuit; a feedback amplifier circuit for outputting a feedback signal based on the static operating current of the second transistor; and an integrator circuit for outputting an integrated signal based on the reference voltage and the feedback signal. This output amplifier circuit can solve the problems of small output bias voltage range and performance degradation in ultra-high bandwidth AWGs.

This invention discloses a phase-amplitude conversion method and apparatus for a direct digital frequency synthesizer. The method includes the following steps: receiving an input phase word; performing trigone normalization on a subdivided phase field based on a trigone control field in the input phase word; using the first field of the normalized subdivided phase field as an index to look up a table, retrieving the initial sine and initial cosine values ​​corresponding to the index from a preset lookup table to obtain a coarse rotation result; generating a rotation code based on the second field of the normalized subdivided phase field; performing rotation correction on the coarse rotation result based on the rotation code to obtain a fine rotation result; and restoring the trigone control field to the final fine rotation result to obtain the final sine and cosine amplitude values. This invention can meet the high-precision requirements of phase-amplitude conversion while reducing storage requirements.

The invention relates to the technical field of electronic system time sequence control, in particular to a multi-system clock synchronization method based on a low-frequency calibration clock, which is characterized in that a main system adopts a high-stability clock source and simultaneously generates a high-frequency data clock and the low-frequency calibration clock of which the frequency is less than one thousandth of that of the data clock through a clock management unit; the characteristics of strong anti-interference and high transmission quality of the low-frequency clock are utilized, and the low-frequency clock is sent to each slave system through the optimized clock distribution network. Each slave system extracts a low-frequency calibration clock through a clock recovery circuit, a high-precision time interval measurement unit is adopted to measure the time difference between a local clock and the calibration clock, and the measurement precision and stability are improved through digital signal processing. And each slave system inputs the time difference as a control quantity into a digital regulation system, dynamically regulates the phase of a local clock, and judges a synchronous locking state through a locking state detection mechanism, thereby realizing high-precision, long-term and stable clock synchronization among multiple systems.

The invention discloses an FSK signal generator based on digital logic and an implementation method. The generator comprises a synchronization module, lookup tables LUT1 and LUT2, an accumulator ADDER and a trigger. The synchronous module processes a DATA / SELECT signal by using a high-frequency clock which is not lower than ten times of the highest output frequency, the LUT1 stores a frequency division coefficient, the LUT2 stores a pulse width ratio parameter and supports 1%-99% adjustment, the accumulator counts to a threshold according to the frequency division coefficient and is reset and triggered, and the trigger stably outputs an FSK (Frequency Shift Keying) signal. The implementation method comprises the following steps: the synchronization module processes a DATASELECT signal by using a high-frequency clock, the synchronized signal drives the LUT1 to output a frequency division coefficient, the accumulator counts to a threshold value, zero clearing is carried out to generate a trigger signal, the LUT2 controls level overturning by combining a parameter and the trigger signal, and the trigger latches and outputs a stable FSK (Frequency Shift Keying) signal. The method can be used for FPGA verification, burr and delay are avoided, the test cost and difficulty are reduced, and the application range is wide.

The application relates to a digital frequency synthesizer, a signal compensation method, an SOC chip and electronic equipment, and belongs to the integrated circuit field.The digital frequency synthesizer comprises a digital frequency synthesis unit, a phase compensation unit and a phase adjustment unit; the digital frequency synthesis unit is used for generating a first clock signal with a first specified duty cycle according to an externally input first digital phase enable binary code and a multi-path initial phase clock signal; the phase compensation unit is used for generating a target compensation clock signal with a corresponding phase width according to required phase accuracy; and the phase adjustment unit is used for generating an output clock signal with a second specified duty cycle according to the target compensation clock signal and the first clock signal. The first clock signal is compensated by generating the target compensation clock signal with the required phase width, so that a clock signal with an arbitrary duty cycle can be output, and the problem that the existing digital frequency synthesizer can only output a clock signal with a specific frequency is effectively improved.

The invention discloses a bit extraction-based zero arithmetic overhead address generation method and circuit. The method comprises the following steps of: detecting the position of a most significant bit of an input fixed-point integer to determine an interval index; directly extracting an intra-interval offset index from the input through a bit extraction operation; and splicing the interval index and the offset index bit to generate a storage address. The circuit comprises a most significant bit detection module, a bit extraction module and an address splicing module. According to the method, the mathematical characteristic of power interval division of 2 is utilized, the existing division operation is converted into simple bit extraction operation, and arithmetic operation in the address generation process is completely eliminated. Only a priority encoder, a multiplexer and bit splicing logic are needed, and no adder, multiplier or divider is included. Realization results on an FPGA show that the circuit only consumes 5-7 LUTs which are reduced by more than 90% compared with an existing method, and the circuit is particularly suitable for resource-limited embedded systems and processing application of high-throughput data streams.