365results about "Digital function generators" patented technology

The embodiment of the invention provides a broadband signal dynamic generation method and system based on multiple clock sources, and the method comprises the steps: monitoring a target frequency in real time through a field programmable gate array, and automatically switching to a corresponding target clock source based on a frequency band to which the target frequency belongs; correcting the phase difference corresponding to the new and old target clock sources through a phase compensation register when the target clock sources are switched, and loading a compensation value to a phase offset register of a direct digital frequency synthesis chip; a fundamental waveform of a broadband signal is generated based on a direct digital frequency synthesis chip, multiple harmonic components are superposed through a fractional accumulation method, and each harmonic amplitude is independently controlled through a look-up table method; an output signal of the power amplifier is collected through the analog-to-digital converter, error information of the actually measured waveform and the theoretical waveform is extracted, the phase offset register and the harmonic amplitude look-up table coefficient are dynamically corrected, and a target broadband signal is output. Unification of broadband coverage, high resolution and quick response is realized.

Embodiments described herein relate to computational multiplexing and applications thereof. The disclosed method and system for performing multiplexed diagnostic testing include providing a sample comprising nucleic acid units to a plurality of channels of a multichannel device; introducing a unique set of probes and reporter moieties into each of the channels; detecting a first indicator readout from a set of channels, wherein the first indicator readout is generated by interaction of a probe within the unique set with one of the nucleic acid units in the sample; generating a readout code for the sample based at least in part on the first indicator readout detected from the first set of channels; matching the generated readout code against a plurality of readout code entries of a lookup table; and generating a detection result of the multiplexed diagnostic testing for the sample based on the matched readout code.

The embodiments of the present disclosure provide a method for designing a high freedom parameterized frequency-modulated coded waveform, comprising: S1: obtaining a frequency-modulated coded vector; S2: selecting a coding model order to be utilized; S3: obtaining an parameterized instantaneous frequency function of a signal based on the frequency-modulated coded vector and the coding model order, integrating the parameterized instantaneous frequency function to obtain a phase of the signal, and generating the high freedom parameterized frequency-modulated coded waveform. Embodiments of the present disclosure provide a high freedom parameterized frequency-modulated coded waveform. The waveform has a continuous phase function, precise spectral control, and is configured to have a parameterized frequency-modulated waveform with high freedom.

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

The invention relates to transcendental function calculation, in particular to a resource reuse type transcendental function calculation device and method, and the device comprises a selector which receives input data, a data type and a control signal, and transmits the input data and the data type to a corresponding processing unit PE according to the control signal; the processing unit PE can process all types of transcendental functions and perform transcendental function calculation on input data according to data types; the result output unit is used for splicing the calculation results of the plurality of processing units PE in sequence to obtain output data; when all the processing units PE perform transcendental function calculation, the lookup table, the fixed-point multiplier, the floating-point multiplier and the floating-point adder are multiplexed; according to the technical scheme provided by the invention, the defect that the transcendental function is difficult to accurately calculate by using fewer hardware resources in the prior art can be effectively overcome.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention relates to the technical field of data processing, and discloses a digital feedback dynamic adjustment method and system for a neutron generator control signal, and the method comprises the steps: calling a reconfigurable waveform parameter set corresponding to a target neutron from a mapping relation according to the yield and beam spot characteristic demands of the target neutron; generating a basic high-frequency pulse sequence of the neutron tube, and performing pre-distortion filtering on the basic high-frequency pulse sequence to obtain a high-frequency pulse sequence of the neutron tube; collecting an anode current and a target voltage signal of the neutron tube applied with the high-frequency pulse sequence during operation, and converting the anode current and the target voltage signal into a digital feedback current; comparing the digital feedback flow with a reference waveform in the reconfigurable waveform parameter set in real time to obtain an error correction amount of the high-frequency pulse sequence; dynamically adjusting the high-frequency pulse sequence according to the error correction; applying the dynamically adjusted high-frequency pulse sequence to a corresponding electrode in a neutron tube through power; the neutron tube control signal processing efficiency can be improved.

The invention discloses an arbitrary waveform signal generation method and device, equipment, a medium and a product, and relates to the field of signal processing, and the method comprises the steps: obtaining a frequency control word, and obtaining target waveform sampling data of a target waveform type; obtaining an output phase value for the frequency control word through a phase accumulation method based on a preset data length; wherein the preset data length is the length of the target waveform sampling data, and the length of the output phase value is an integral multiple of the preset data length; obtaining a target waveform amplitude value through a waveform look-up table method according to the output phase value and the target waveform sampling data; and performing analog-to-digital conversion on the target waveform amplitude value to obtain a first waveform signal. According to the invention, the waveform signal of any output wave can be prevented from generating periodic jitter.

The invention relates to a square wave generation method and system based on a DDS signal transmitter, and belongs to the technical field of digital electronic signal synthesis. The method comprises the following steps: calculating a digital analog signal sampling frequency based on a square wave output frequency set by a user, and obtaining a digital fundamental frequency phase signal according to a phase-locked loop precision range; mapping the digital fundamental frequency phase signal into a sinusoidal amplitude signal according to a digital phase accumulation mechanism to obtain a digital-analog conversion clock, binarizing the sinusoidal amplitude signal, and outputting a square wave output period; dividing a square wave output period into a low level region and a high level region according to the precision range of the phase-locked loop, reading a square wave output frequency set by a user through a random storage address, and outputting a non-offset phase-locked square wave; and constructing an error accumulation self-checking architecture to calculate a frequency control word, and when detecting that the frequency control word has a decimal discarding error, recalculating the frequency control word.

The invention discloses a Depthwise volume storage internal calculation device and method based on dynamic table lookup accumulation, and the device comprises a lookup table memory, a multi-address concurrent lookup table cache module, a dynamic table lookup accumulation module, a data write-back module, a feature map memory, a data acquisition module and a cache switching control module. Based on the design of a multi-access concurrent lookup table cache module, parallel access to a plurality of pre-stored lookup table values in a single period is supported, and dynamic space alignment, multi-channel parallel lookup and accumulation operation of an input feature map and the lookup table values are realized in cooperation with a dynamic lookup accumulation module; according to the method, a lookup table pre-generation technology of receptive field decoupling is adopted, and exponential compression of lookup table storage overhead is realized by separating a convolution kernel space dimension mapping relation. According to the method, the multiplication and addition operation of the traditional convolution is converted into a dynamic table look-up accumulation process, a high-complexity multiplier of the traditional Depthwise convolution is avoided, the calculation efficiency is remarkably improved, and meanwhile, the hardware resource consumption and the power consumption are greatly reduced.

The invention relates to the technical field of underground pipeline detection, in particular to a Hertz signal digitization method and system for underground pipeline detection. A digital detection excitation signal with stable Hertz frequency is generated by adopting a phase accumulation mechanism of a DDS (direct digital synthesis) technology and digital interpolation translation; a controllable random jitter frequency division strategy is introduced to generate multiple groups of single-frequency-point voltage signals to reduce spectrum aliasing and background noise; a response signal is sampled and filtered through a high-precision ADC and a self-adaptive FIR low-pass filter; and carrying out detection analysis and alarm on the target underground pipeline in combination with the frequency band energy normalization analysis and feature vector construction of the wavelet sub-band. According to the invention, digital improvement can be carried out on a 512 Hz analog signal detected by a traditional underground pipeline, and the sensitivity, the anti-interference capability and the signal processing precision of underground pipeline detection are greatly improved.

Disclosed is a system-on-chip. The system-on-chip including at least one operation processing unit configured to process an instruction based on a driving voltage and a clock signal, a temperature management module configured to estimate a cooling coefficient and a heating coefficient associated with the at least one operation processing unit based on a temperature measured at the at least one operation processing unit, and determine an operating frequency of the clock signal to be sent to the at least one operation processing unit based on the cooling coefficient and the heating coefficient, and a dynamic voltage and frequency scaling (DVFS) module configured to output a control signal for adjusting the driving voltage and the clock signal based on the operating frequency.

The invention relates to the technical field of signal generation, and discloses a signal generation system and method, and the system comprises a first signal generation module; the second signal generation module comprises an analog signal generation unit and a signal copying unit; the signal mixing module comprises an analog frequency mixing unit, a digital frequency mixing unit and a signal switching unit; the output end of the analog signal generation unit is connected with the input end of the analog frequency mixing unit; the first end of the signal copying unit is connected with the clock signal output end of the analog signal generating unit, the second end is connected with the mixing input end of the analog signal generating unit, and the third end is connected with the first end of the signal switching unit; the second end of the signal switching unit is connected with the output end of the analog frequency mixing unit, and the third end is connected with the input end of the digital frequency mixing unit. Therefore, a direct digital frequency synthesizer in the analog signal generation unit is calibrated when the clock signal is switched to, and spurious signals are eliminated based on a calibration result when the clock signal is switched to the analog local oscillator signal.

The utility model relates to a signal generation device, an analog-digital hybrid test board card and a test machine, a read-write control module reads an original waveform from a storage device according to a received read request instruction, and returns the read original waveform to an arbitrary waveform generator; the arbitrary waveform generator receives the original waveform and outputs a reconstructed waveform matched with the frequency of a sampling clock of the digital-to-analog conversion device to the first communication module. And the second communication module is connected with the first communication module, and the reconstructed waveform is received by the second communication module and then is transmitted to the digital-to-analog conversion device. According to the technical scheme, the reconstructed waveform can be generated by resampling the original waveform, the external clock chip outputs the sampling clock with the fixed frequency to the digital-to-analog conversion device, digital-to-analog conversion can be completed, the external clock chip does not need to adjust the frequency of the sampling clock, the hardware requirement for the external clock chip and the digital-to-analog conversion device is low, and the design cost is reduced.

The embodiments of the present application relate to the technical field of chips. Provided are a data processing method and a data processing apparatus, which ameliorate the problem of the poor performance of a processor. The specific solution involves: a processor core acquiring input data of a target function by means of an input interface; on the basis of a first index and a second index, the processor core determining a polynomial coefficient corresponding to the input data; and on the basis of a data bit and the polynomial coefficient, the processor core performing polynomial calculation to obtain output data of the target function, and outputting the output data of the target function by means of an output interface. The embodiments of the preset application are used for a calculation process of a target function.

A compensation lookup table generator includes a maximum power voltage determiner, a rush power reduction amount operator, an allowable current increase amount operator and a lookup table modifier. The maximum power voltage determiner is configured to determine a maximum power voltage based on a first lookup table, a peak gain setting value and a power voltage curve. The rush power reduction amount operator is configured to operate a rush power reduction amount based on the maximum power voltage and a rush power limit. The allowable current increase amount operator is configured to operate an allowable current increase amount based on the maximum power voltage and the rush power reduction amount. The lookup table modifier is configured to generate a second lookup table by modifying the first lookup table based on the peak gain setting value and the allowable current increase amount.

To provide a VPU and associated components that are optimized to improve VPU performance and throughput.SOLUTION: A VPU includes a min / max collector, an automatic store predication function, a SIMD data path configuration allowing inter-lane sharing, a transposed load / store including a stride parameter function, a load including a permute and zero insertion function, a hardware, logic device, and memory layout function allowing two point and two by two point lookups, and per memory bank load caching ability. Decoupled accelerators are used to offload VPU processing tasks, and a hardware sequencer is included in a DMA system. The DMA and VPU execute a VPU configuration mode allowing the VPU and DMA to operate without a processing controller for executing dynamic region-based data movement operations.SELECTED DRAWING: Figure 9A

The invention discloses a high-precision arbitrary carrier generation method based on an FPGA (Field Programmable Gate Array) and an intermediate-frequency DAC (Digital-to-Analog Converter), which comprises the following steps of: when a system needs to execute arbitrary carrier generation, firstly, configuring a carrier frequency needing to be generated through instruction input, and calculating to obtain an equivalent carrier frequency by using an equivalent carrier conversion module based on a Nyquist sampling theorem and an equivalent carrier conversion formula; the phase calibration unit formulates a phase value of each channel, and then performs dynamic phase compensation based on a linear feedback shift register to generate a dynamically compensated phase control word; and finally, the multi-channel waveform generation module generates an equivalent carrier based on the multi-channel parallel DDS. According to the high-precision arbitrary carrier generation method based on the FPGA and the intermediate-frequency DAC, the limitation of the working clock frequency of an existing FPGA device is broken through through cooperative work of the carrier conversion module and the multi-channel waveform generation module, and high-flexibility arbitrary carrier generation is achieved.

The invention provides a high-precision low-jitter waveform generation method and device based on an FPGA, and relates to the technical field of signal processing. According to the phase accumulated value obtained through preprocessing, calculation is carried out according to a preset mathematical model, and a model output value is determined; performing phase comparison according to the phase accumulated value, and performing waveform selection in combination with a model output value to obtain an initial output waveform; according to the phase accumulated value, generating a sine wave through a preset CORDIC IP; according to the initial output waveform and the sine wave, waveform selection is carried out, and a secondary output waveform is determined; and performing digital-to-analog conversion according to the secondary output waveform and a preset reference clock signal, and outputting a final waveform. By combining the high-precision characteristic of DDS frequency control and the flexibility of edge interpolation, low-jitter pulse waves with adjustable parameters such as edge time, pulse width, duty ratio and degree of symmetry are generated; advantages of linear interpolation and nonlinear interpolation are integrated, and edge jitter of pulse signals is effectively reduced.

Compressing problems or models configured for execution in quantum computing systems is disclosed. An original problem, which may be represented as a string, for execution in a quantum computing system is classically compressed using classical computing systems. Unique variable names and unique coefficients stored in tables constructed from the original problem are associated with unique identifiers. The problem is then translated to a translated form, such as a translated string, using the tables. The translated string may also be generated after quantizing values in the at least one of the tables. The translated string, whether or not quantized, may be entropy encoded. The final result is a compressed version or string of the original string that can be transmitted and stored in a compressed form. The compressed problem may also be decompressed and submitted for execution in a quantum computing system.

The utility model discloses a circuit system of a high-voltage signal generator. The circuit system comprises a DDS main control circuit, a filter circuit, an operational amplifier circuit, a level conversion circuit, a power supply circuit and a crystal oscillator circuit, the output end of the DDS main control circuit is sequentially connected with the filter circuit and the operational amplifier circuit; the operational amplifier circuit is connected with the power supply circuit and the peripheral port; the DDS main control circuit is also respectively connected with the power supply circuit and the crystal oscillator circuit; the level conversion circuit is connected with the crystal oscillator circuit, the DDS main control circuit and the external power supply circuit; the power supply circuit is connected with an external power supply circuit. According to the scheme, numerous application requirements of high-voltage and high-precision signals can be met.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

A computer system is presented configured and operable as a library constructor for use in extracting one or more parameters of a patterned structure from real time measured data obtained on said structure. The system comprises: data input utility for receiving input data comprising preliminary measured data obtained from at least a part of a structure, and comprising data indicative of user-defined quality of measurement results (QOR); and a data processor.

Techniques are disclosed for a programmable processor architecture that enables data interpolation using an architecture that iteratively processes portions of a lookup table (LUT) according to a fused single instruction stream, multiple data stream (SIMD) instruction. The LUT may include segment entries corresponding to a result of evaluating a function using corresponding index values ​​representing an independent variable of the function. The index values ​​are used to map data sample values ​​in a data array configured to be interpolated to the segment entries.By using an iterative process of mapping data samples to valid segment entries contained in each LUT section, the architecture advantageously facilitates scaling to support larger LUTs and can thus be extended to enable linear interpolation on multiple dimensions.

The invention discloses a closed-loop adaptive generative adversarial network filter. A test and measurement system includes: a plurality of nodes, one or more nodes including sensors configured to receive signals; one or more generative adversarial network (GAN) models; one or more signal generators configured to generate and transmit signals; and one or more processors configured to execute the code to cause the one or more processors to receive a request for a signal having a signal profile from one of the plurality of nodes, transmit the signal profile and the request to one of the one or more GAN models, receive a matching signal profile that matches the signal profile, and transmit the matching signal profile to the one of the one or more GAN models. And transmit the matching signal profile to one of the one or more signal generators to generate and transmit a matching signal.

The present invention relates to the technical field of data classification, and specifically to a big data intelligent classification method and system. The method comprises: obtaining an access correlation coefficient of any two modules based on the number of visits and access time interval of each user to any two modules in software, combined with the software registration duration of each user and the number of software visits and access duration; obtaining the data content correlation of any two modules based on the data change relationship between any two modules; fusing the access correlation coefficient and the data content correlation to obtain the comprehensive correlation of any two modules; and classifying the data of each module in the software based on the comprehensive correlation of all two modules in the software, which can improve the accuracy and reliability of data classification, can accurately analyze the correlation between the various modules of the software, and is beneficial for software designers to analyze the collaborative performance between the various modules, thereby timely optimizing the functions of each module of the software and improving the user experience of the software.

A method and an apparatus are disclosed for a function approximation using a multi-level lookup table. The function approximation device and the method approximate function values for a function in multiple stages using a multi-level lookup table (LUT) in approximating nonlinear function values based on piecewise linear approximation or piecewise polynomial approximation. In the multi-level LUT, a segment length is set differently depending on the amount of change in the function in order to reduce approximation errors.

The application discloses a kind of pulse shaping method and system of nuclear signal, belong to signal processing technical field, for the problems of existing pulse signal width in prior art Widening, thereby increasing the accumulation event, and there is no better anti-noise effect to Gaussian white noise, the present application includes: the output signal of detector is acquired, and output signal is structured into digital function signal;The Z transform is carried out after the discrete of the digital function signal, and output Z transform signal is obtained;Definition input signal is exponential signal, and the Z transform is carried out to the exponential signal, and input Z transform signal is obtained;According to the input Z transform signal and the output Z transform signal, the transfer function of input signal pulse shaping is obtained;The inverse Z transform is carried out to the transfer function, and the pulse shaping signal of input signal is obtained, and its time domain expression.The purpose is: the pulse shaping signal obtained has better signal-to-noise ratio, and it is convenient to obtain amplitude.

This disclosure presents a method for constructing and parsing signal event descriptors for electromagnetic environment simulation. The construction method includes: acquiring an electromagnetic scene simulation description file; extracting at least one set of group-level control parameters and at least one set of service signal parameters constrained by the group-level control parameters from the electromagnetic scene simulation description file; performing quantization encoding conversion on the group-level control parameters and service signal parameters to obtain integer parameters recognizable by the signal generation hardware device; encapsulating the integer group-level control parameters and integer service signal parameters into group header frames and member frames, respectively; sequentially combining the group header frames and member frames with control constraints to the group header frames to generate signal event descriptor groups; and sequentially sending the signal event descriptor groups, frame by frame, to the signal generation hardware device. This method achieves standardized, structured construction, and ordered transmission of signal parameters through grouped encapsulation and integer quantization encoding.