250results about "Digital function generators" patented technology

The invention provides a dynamic residual amplification circuit based on charge sampling, and relates to the technical field of integrated circuits, the dynamic residual amplification circuit comprises an integrating circuit, a logic circuit, a charge pump and a zero-cross detection circuit, the integrating circuit is connected with the logic circuit and the zero-cross detection circuit, the integrating circuit converts a sampled input differential signal into a constant current, and the constant current is connected with the charge pump. The output node is continuously charged or discharged, so that the input differential signal is converted into a current integral quantity; the zero-cross detection circuit monitors the output voltage of the integrating circuit in real time, and when the output voltage is greater than or equal to the common mode voltage VCM, the moment when the output voltage is equal to the common mode voltage VCM is converted into a digital clock edge; the logic circuit is connected with the charge pump and outputs digital pulses to the charge pump according to the digital clock edge so as to control the reset time sequence of the whole dynamic residual amplification circuit; the charge pump is configured to output a residual voltage modulated by the digital pulse in response to the digital pulse. The application helps to improve the linearity of the residual signal.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

The invention relates to the technical field of data processing, and discloses a digital feedback dynamic adjustment method and system for a neutron generator control signal, and the method comprises the steps: calling a reconfigurable waveform parameter set corresponding to a target neutron from a mapping relation according to the yield and beam spot characteristic demands of the target neutron; generating a basic high-frequency pulse sequence of the neutron tube, and performing pre-distortion filtering on the basic high-frequency pulse sequence to obtain a high-frequency pulse sequence of the neutron tube; collecting an anode current and a target voltage signal of the neutron tube applied with the high-frequency pulse sequence during operation, and converting the anode current and the target voltage signal into a digital feedback current; comparing the digital feedback flow with a reference waveform in the reconfigurable waveform parameter set in real time to obtain an error correction amount of the high-frequency pulse sequence; dynamically adjusting the high-frequency pulse sequence according to the error correction; applying the dynamically adjusted high-frequency pulse sequence to a corresponding electrode in a neutron tube through power; the neutron tube control signal processing efficiency can be improved.

The invention relates to a square wave generation method and system based on a DDS signal transmitter, and belongs to the technical field of digital electronic signal synthesis. The method comprises the following steps: calculating a digital analog signal sampling frequency based on a square wave output frequency set by a user, and obtaining a digital fundamental frequency phase signal according to a phase-locked loop precision range; mapping the digital fundamental frequency phase signal into a sinusoidal amplitude signal according to a digital phase accumulation mechanism to obtain a digital-analog conversion clock, binarizing the sinusoidal amplitude signal, and outputting a square wave output period; dividing a square wave output period into a low level region and a high level region according to the precision range of the phase-locked loop, reading a square wave output frequency set by a user through a random storage address, and outputting a non-offset phase-locked square wave; and constructing an error accumulation self-checking architecture to calculate a frequency control word, and when detecting that the frequency control word has a decimal discarding error, recalculating the frequency control word.

The invention relates to the technical field of underground pipeline detection, in particular to a Hertz signal digitization method and system for underground pipeline detection. A digital detection excitation signal with stable Hertz frequency is generated by adopting a phase accumulation mechanism of a DDS (direct digital synthesis) technology and digital interpolation translation; a controllable random jitter frequency division strategy is introduced to generate multiple groups of single-frequency-point voltage signals to reduce spectrum aliasing and background noise; a response signal is sampled and filtered through a high-precision ADC and a self-adaptive FIR low-pass filter; and carrying out detection analysis and alarm on the target underground pipeline in combination with the frequency band energy normalization analysis and feature vector construction of the wavelet sub-band. According to the invention, digital improvement can be carried out on a 512 Hz analog signal detected by a traditional underground pipeline, and the sensitivity, the anti-interference capability and the signal processing precision of underground pipeline detection are greatly improved.

The invention relates to the technical field of signal generation, and discloses a signal generation system and method, and the system comprises a first signal generation module; the second signal generation module comprises an analog signal generation unit and a signal copying unit; the signal mixing module comprises an analog frequency mixing unit, a digital frequency mixing unit and a signal switching unit; the output end of the analog signal generation unit is connected with the input end of the analog frequency mixing unit; the first end of the signal copying unit is connected with the clock signal output end of the analog signal generating unit, the second end is connected with the mixing input end of the analog signal generating unit, and the third end is connected with the first end of the signal switching unit; the second end of the signal switching unit is connected with the output end of the analog frequency mixing unit, and the third end is connected with the input end of the digital frequency mixing unit. Therefore, a direct digital frequency synthesizer in the analog signal generation unit is calibrated when the clock signal is switched to, and spurious signals are eliminated based on a calibration result when the clock signal is switched to the analog local oscillator signal.

To provide a VPU and associated components that are optimized to improve VPU performance and throughput.SOLUTION: A VPU includes a min / max collector, an automatic store predication function, a SIMD data path configuration allowing inter-lane sharing, a transposed load / store including a stride parameter function, a load including a permute and zero insertion function, a hardware, logic device, and memory layout function allowing two point and two by two point lookups, and per memory bank load caching ability. Decoupled accelerators are used to offload VPU processing tasks, and a hardware sequencer is included in a DMA system. The DMA and VPU execute a VPU configuration mode allowing the VPU and DMA to operate without a processing controller for executing dynamic region-based data movement operations.SELECTED DRAWING: Figure 9A

The utility model discloses a circuit system of a high-voltage signal generator. The circuit system comprises a DDS main control circuit, a filter circuit, an operational amplifier circuit, a level conversion circuit, a power supply circuit and a crystal oscillator circuit, the output end of the DDS main control circuit is sequentially connected with the filter circuit and the operational amplifier circuit; the operational amplifier circuit is connected with the power supply circuit and the peripheral port; the DDS main control circuit is also respectively connected with the power supply circuit and the crystal oscillator circuit; the level conversion circuit is connected with the crystal oscillator circuit, the DDS main control circuit and the external power supply circuit; the power supply circuit is connected with an external power supply circuit. According to the scheme, numerous application requirements of high-voltage and high-precision signals can be met.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

A computer system is presented configured and operable as a library constructor for use in extracting one or more parameters of a patterned structure from real time measured data obtained on said structure. The system comprises: data input utility for receiving input data comprising preliminary measured data obtained from at least a part of a structure, and comprising data indicative of user-defined quality of measurement results (QOR); and a data processor.

The invention discloses a closed-loop adaptive generative adversarial network filter. A test and measurement system includes: a plurality of nodes, one or more nodes including sensors configured to receive signals; one or more generative adversarial network (GAN) models; one or more signal generators configured to generate and transmit signals; and one or more processors configured to execute the code to cause the one or more processors to receive a request for a signal having a signal profile from one of the plurality of nodes, transmit the signal profile and the request to one of the one or more GAN models, receive a matching signal profile that matches the signal profile, and transmit the matching signal profile to the one of the one or more GAN models. And transmit the matching signal profile to one of the one or more signal generators to generate and transmit a matching signal.

The present invention relates to the technical field of data classification, and specifically to a big data intelligent classification method and system. The method comprises: obtaining an access correlation coefficient of any two modules based on the number of visits and access time interval of each user to any two modules in software, combined with the software registration duration of each user and the number of software visits and access duration; obtaining the data content correlation of any two modules based on the data change relationship between any two modules; fusing the access correlation coefficient and the data content correlation to obtain the comprehensive correlation of any two modules; and classifying the data of each module in the software based on the comprehensive correlation of all two modules in the software, which can improve the accuracy and reliability of data classification, can accurately analyze the correlation between the various modules of the software, and is beneficial for software designers to analyze the collaborative performance between the various modules, thereby timely optimizing the functions of each module of the software and improving the user experience of the software.

The application discloses a kind of pulse shaping method and system of nuclear signal, belong to signal processing technical field, for the problems of existing pulse signal width in prior art Widening, thereby increasing the accumulation event, and there is no better anti-noise effect to Gaussian white noise, the present application includes: the output signal of detector is acquired, and output signal is structured into digital function signal;The Z transform is carried out after the discrete of the digital function signal, and output Z transform signal is obtained;Definition input signal is exponential signal, and the Z transform is carried out to the exponential signal, and input Z transform signal is obtained;According to the input Z transform signal and the output Z transform signal, the transfer function of input signal pulse shaping is obtained;The inverse Z transform is carried out to the transfer function, and the pulse shaping signal of input signal is obtained, and its time domain expression.The purpose is: the pulse shaping signal obtained has better signal-to-noise ratio, and it is convenient to obtain amplitude.

This disclosure presents a method for constructing and parsing signal event descriptors for electromagnetic environment simulation. The construction method includes: acquiring an electromagnetic scene simulation description file; extracting at least one set of group-level control parameters and at least one set of service signal parameters constrained by the group-level control parameters from the electromagnetic scene simulation description file; performing quantization encoding conversion on the group-level control parameters and service signal parameters to obtain integer parameters recognizable by the signal generation hardware device; encapsulating the integer group-level control parameters and integer service signal parameters into group header frames and member frames, respectively; sequentially combining the group header frames and member frames with control constraints to the group header frames to generate signal event descriptor groups; and sequentially sending the signal event descriptor groups, frame by frame, to the signal generation hardware device. This method achieves standardized, structured construction, and ordered transmission of signal parameters through grouped encapsulation and integer quantization encoding.

The present application provides a waveform output method, device, hardware equipment and computer readable storage medium, the hardware equipment stores the waveform segment set sent by the software equipment, the waveform segment set includes at least one waveform segment, each waveform segment corresponds to a label respectively, and the method comprises the following steps: receiving the waveform combination mode sent by the software equipment, wherein the waveform combination mode is obtained by arranging the label of each waveform segment by the software equipment; receiving the instruction package sent by the software equipment, and outputting any waveform corresponding to the waveform combination mode based on the instruction package. The method only needs to obtain different waveform combination modes in the case of using the same waveform segment set, so as to realize the change of outputting any waveform. For the hardware equipment, only the output waveform combination mode with small update data amount sent by the software equipment needs to be received to change the output any waveform, so that the output efficiency of any waveform can be effectively improved.

A computing platform may receive matrix multiplication information indicating a plurality of matrix dimension sets for matrix multiplication. For each matrix dimension set, the computing platform may: 1) identify one or more multiplication variations, indicating different possible orders of operation for executing the corresponding multiplication, 2) perform memoization to identify, for each order of operation, a corresponding number of operations to complete the corresponding multiplication, 3) identify, based on the numbers of operations, a most efficient order of operation, and 4) store, in a lookup table, a relationship between the given matrix dimension set and the most efficient order of operation. The computing platform may identify matrix dimensions for a model configuration request, and identify, using the lookup table, a corresponding order of operations. The computing platform may iteratively train the generative AI model based on the order of operations, and deploy the generative AI model.

A circuit for transmitting an n-bit phase value between circuits includes a system clock input, an n-bit phase value generator coupled to the system clock input that generates a phase value output and an edge output indicating that the phase output value is valid, a latched clock delay circuit having an input coupled to the system clock input, an input coupled to the edge output, a variable phase delay circuit coupled to the phase value output, a delay adder having a first input coupled to the phase value output, a second input coupled to a delay offset signal, and an output coupled to a control input of the variable phase delay circuit, and a phase flip-flop having a data input coupled to an output of the variable phase delay circuit, a clock input coupled to a latched clock output of the variable output clock delay circuit, and a phase out output.

Methods, systems, devices, and computer-readable media are described for performing neural network computations using a system configured to implement a neural network on hardware circuitry. The system includes a host receiving a batch of inputs to a neural network layer. Each input is stored in a memory location identified by an address. The system identifies one or more duplicate addresses in a list of addresses for the one or more inputs. For each duplicate address, the system generates a unique identifier that identifies the duplicate address in the list of addresses. The system (i) obtains a first input from a memory location identified by an address corresponding to the unique identifier; and (ii) generates an output of the layer from the obtained first input.

The invention provides a variable frequency digital power supply pulse width modulation controller and a modulation control method. The controller comprises a clock management module used for generating a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; the communication module is used for receiving a proportion parameter, an integral parameter, a differential parameter and a target value sent by the upper computer according to the first clock signal; the AD conversion module is used for acquiring voltage data from the buck circuit according to the second clock signal and converting the voltage data into digital waveform data; the PID control module is used for determining a control quantity based on an incremental PID compensation algorithm; the DDS generation module is used for generating digital waveform data with a specific duty ratio according to the fourth clock signal and the control quantity; and the DA conversion module is used for converting the digital waveform data with the specific duty ratio into an analog signal according to the third clock signal and sending the analog signal to the buck circuit. According to the technical scheme provided by the invention, the problem that the control accuracy is limited by the chip performance in the prior art is solved.

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a low temperature. The system also includes a second packaged device including a control circuit configured to operate at a low temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit includes a plurality of charge locking circuits configured to lock the charge of the first packaged device to the second packaged device. Wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

A graph processing core includes a plurality of processing pipelines and an interrupt controller unit. Each processing pipeline executes one or more threads and includes, for each thread, a register indicating a currently executing program counter vector and another register indicating an interrupt or exception handler vector. The interrupt controller unit may receive interrupt or exception notifications from the processing pipelines, determine a handler vector based on the notification and a set of registers of the interrupt controller unit, and transmit the handler vector to the processing pipeline that issued the interrupt or exception notification. Further, the issuing pipeline may receive the handler vector from the interrupt controller unit, write a value in the first register into the second register, write the handler vector into the first register, and invoke an interrupt or exception hander based on the value written into the first register.

Systems and methods related to charge locking circuits and control systems for qubits are provided. A system for controlling qubit gates includes a first packaging device including a quantum device, the quantum device including a plurality of qubit gates, wherein the quantum device is configured to operate at cryogenic temperatures. The system further includes a second packaging device including a control circuit configured to operate at cryogenic temperatures, wherein the first packaging device is coupled to the second packaging device, and wherein the control circuit includes a plurality of charge locking circuits, wherein each charge locking circuit of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect, such that each charge locking circuit of the plurality of charge locking circuits is configured to provide a voltage signal to the at least one qubit gate.

Electronic control device, comprising: a logic circuit (255) capable of reconfiguring a plurality of arithmetic circuits, including a first circuit and a second circuit; a reconfiguration controller (204) that reconfigures the arithmetic circuits based on reconfiguration commands and verifies the reconfigured arithmetic circuits; and a process controller (202) that sends the reconfiguration commands to the reconfiguration controller (204) and commands the arithmetic circuits to perform operations, wherein the reconfiguration controller (204) reconfigures and verifies the first circuit when a first reconfiguration command is received, The process controller (202) of the first circuit commands to perform an operation when the verification of the first circuit by the reconfiguration controller (204) is complete. After the first circuit has been reconfigured, the process controller (202) sends a second reconfiguration command to the reconfiguration controller (204) and orders the reconfiguration controller (204) to start the reconfiguration of the second circuit until the first circuit has completed its operation.

Systems and methods for synthesis of a modulated RF signal using a variety of modulation schemes are described. An embodiment includes a direct frequency synthesizer with frequency modulated continuous wave (FMCW) modulation that includes: a high speed BAW resonator that generates a frequency signal; a BAW oscillator that receives the frequency signal and generates an output BAW clock signal (BAW CLK); a frequency and phase estimation circuit that receives a reference clock signal from a reference clock (REF CLK) and the BAW CLK and generates a frequency error and a phase error; a frequency chirp generator that receives chirp parameters, a chirp sync signal and generates a nominal frequency control word (FCW); and a high speed digital to analog converter (HS DAC) that receives the BAW CLK and the codeword and outputs an analog signal.

The invention relates to a YOLO v3 post-processing hardware acceleration method based on a look-up table method, which comprises the following steps of: 1) establishing two look-up tables according to two operators of sigmoid and exp functions involved in a decoding calculation process; 2) analyzing the required storage space according to the quantization bits and the network structure; 3) distributing a corresponding BRAM storage block for the lookup table according to the required storage space; 4) calculating the data to be decoded, and putting a calculation result into a lookup table; 5) inputting to-be-decoded data, putting the to-be-decoded data into the cache unit, and arranging the to-be-decoded data; 6) reading data to be decoded, and searching corresponding calculation data from the lookup table; 7) inputting the calculation data into a parallel calculation unit to obtain decoding data; and 8) putting the decoded data back to the initial position in the cache unit. According to the method, the lookup table is established, the to-be-decoded data in YOLO v3 post-processing is subjected to decoding calculation, post-processing calculation is completed under the condition that few storage resources are used, the hardware scale is remarkably reduced, and the post-processing efficiency is improved.

The embodiment of the application provides a kind of wide frequency signal dynamic generation method and system based on multiple clock sources, the method comprises: by field programmable gate array real-time monitoring target frequency, and based on the frequency band of target frequency belongs to automatically switched to corresponding target clock source;When the target clock source is switched, the phase difference corresponding to the new and old target clock source is corrected by phase compensation register, and the compensation value is loaded to the phase offset register of direct digital frequency synthesis chip;Based on direct digital frequency synthesis chip, generate the fundamental wave waveform of wide frequency signal, and superimpose multiple harmonic components by sub-accumulation method, and the amplitude of each harmonic is independently controlled by look-up table method;The output signal of power amplifier is extracted by analog-digital converter, and the error information of measured waveform and theoretical waveform is extracted and dynamically corrected phase offset register and harmonic amplitude look-up table coefficient, and output target wide frequency signal.The application realizes the unity of wide frequency coverage, high resolution and fast response.

The application discloses a waveform generation circuit and method based on FPGA, and relates to the technical field of waveform generation.The waveform generation circuit comprises a field programmable gate array and a digital-to-analog conversion chip.In the field programmable gate array, a memory access module is used to access the memory to obtain configuration information and data information corresponding to a self-defined waveform.A selection module and a control module are used to generate selection signals and control signals according to the configuration information and the data information in sequence, so that the output of a waveform generation module is controlled, the waveform generation module outputs a self-defined waveform digital signal according to the data information, and finally, the digital-to-analog conversion chip outputs the self-defined waveform according to the self-defined waveform digital signal.The application uses the FPGA to replace a special hardware circuit, reduces the production and development cost, and can generate waveforms of different types of print heads by modifying the configuration information in the memory, so that the update and replacement are simple.

A method of generating electrical signal waveforms. A generator includes a digital processing circuit, a memory circuit in communication with the digital processing circuit defining a lookup table, a digital synthesis circuit in communication with the digital processing circuit and the memory circuit, and a digital-to-analog converter (DAC) circuit. The method includes generating a first and second digital electrical signal waveforms, combining the first and second waveforms to form a combined waveform, modifying the combined waveform to form a modified waveform The peak amplitude of the modified waveform does not exceed a predetermined amplitude value. The method includes generating a second waveform that is a function of the first waveform. The method includes modifying a frequency of the first waveform to form a frequency modified first waveform and combining the frequency modified first and second waveforms to form a combined waveform.

This application discloses a precision capacitance sensing system, comprising a modulation signal source, a sensitive probe, a differential transformer bridge, a signal amplification link, an analog multiplier, and a low-pass filter circuit, all connected in sequence. It also includes a demodulation reference signal source, the output of which is connected to the second input of the analog multiplier. The demodulation reference signal source is used to generate a multi-frequency combination demodulation reference signal, which is composed of a fundamental frequency component and at least two harmonic components superimposed. This invention also discloses a precision capacitance sensing method. By employing a specially designed demodulation reference signal, this application ensures that the system output remains constant within a continuously varying range of the demodulation phase difference, thereby achieving complete insensitivity to phase difference fluctuations and effectively overcoming the performance bottleneck that has long constrained high-precision capacitance sensing.