119results about "Computations using residue arithmetic" patented technology

The SRT operational circuit comprises an input module, a floating point conversion module, a calculation module and an output module, the input module is configured to output an initial operand, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; if the calculation module is configured to perform division operation or root extraction operation by adopting the first operand based on the SRT algorithm, the output module is configured to perform mantissa rounding on a division result or a root extraction result after the calculation of the calculation module is completed and output a floating point result, so that the operation accuracy of an integer in the circuit is improved, and the universality of the circuit is improved.

Computer-implemented methods for locking a blockchain transaction based on undetermined data are described. The invention is implemented using a blockchain network. This may, for example, be the Bitcoin blockchain. A locking node may include a locking script in a blockchain transaction to lock a digital asset. The locking script includes a public key for a determined data source and instructions to cause a validating node executing the locking script to verify the source of data provided in an unlocking script by: a) generating a modified public key based on the public key for the determined data source and based on data defined in the unlocking script; and b) evaluating a cryptographic signature in the unlocking script based on the modified public key. The blockchain transaction containing the locking script is sent by the locking node to the blockchain network. The lock may be removed using a cryptographic signature generated from a private key modified based on the data.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

According to an embodiment, an arithmetic device outputting an arithmetic result on a finite field with characteristic P includes a hardware processor. The hardware processor performs readout processing of a plurality of input values. The hardware processor performs, for each word, arithmetic operations with respect to the plurality of input values by using a value being based on the characteristic P and a comparison value between each input value of the plurality of input values and the characteristic P. The hardware processor outputs a first output value resulting from computing a value being based on each input value of the plurality of input values, the comparison value, and the characteristic P. The hardware processor outputs a second output value resulting from comparing the first output value and the characteristic P.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

A modular operation device for handling a modular multiplication, comprises a controller, configured to divide a multiplicand into a plurality of multiplicand words, a multiplier into a plurality of multiplier words, and a modulus into a plurality of modulus words; a first plurality of processing elements, coupled to the controller, configured to compute a first plurality of updated carry results and a first plurality of updated sum results; a second plurality of processing elements, coupled to the controller, configured to compute a second plurality of updated carry results and a second plurality of updated sum results; and a reduction element, coupled to the controller, configured to compute a resulting remainder according to the second plurality of updated carry results and the second plurality of updated sum results.

The application discloses a privacy protection neural network inference method based on multi-point evaluation. K Segment k Polynomial, and a safe multiplication tree and a safe remainder tree are established, and then a remainder polynomial is safely evaluated. Since the polynomial power to be evaluated in the online stage is reduced, the number of self-multiplication items is reduced, thereby reducing the communication round number of overall polynomial evaluation, reducing the number of calls of the safe multiplication triplets in the secret sharing, and correspondingly reducing the offline pre-computation cost. In addition, the layered structure of the safe multiplication tree and the remainder tree supports parallel computation of multi-point input, and can fully utilize the parallel computation capacity of a modern multi-core processor or a GPU.

The invention relates to an apparatus and a method for number-theoretical transformation instructions. Instructions are executed for performing a number-theory transform (NTT). For example, one embodiment includes: a decode circuit to decode the instruction; one or more packed data registers to store a first, second, and third plurality of source packed data elements and corresponding result packed data elements; and execution circuitry to execute the NTT using a butterfly operation including Montgomery multiplication of a source packed data element of the second plurality of source packed data elements and a corresponding source packed data element of the third plurality of source packed data elements using a modulus value or an inverse of the modulus value to generate a product. The product is added to a corresponding source packed data element of the first plurality of source packed data elements to obtain a first result, and the product is subtracted from the corresponding source packed data element of the first plurality of source packed data elements to obtain a second result.

The present disclosure provides a method for generating an isogeny-based ring signature. The method includes executing a setup algorithm to establish public parameters includ¬ ing a base elliptic curve, generating key pairs for a plurality of users, and executing a signing algorithm by a signer. The signing algorithm involves selecting a random isogeny, iteratively computing isogenies, scalar values, basis points, subgroups, and additional isogenies for users in a ring, computing signer-specific isogenies and subgroups, deriving a dual isogeny, and outputting a ring signature comprising the computed isogenies and basis points. The method enables generation of an anonymous ring signature based on isogeny computations over elliptic curves, providing enhanced security in cryptographic systems.

A numerical conversion method for a public key cryptography system includes accumulating a first value by using a first modular addition loop according to the first value for generating a second value after a first predetermined loop count is reached, accumulating the second value by using a second modular addition loop according to the second value for generating a third value after a second predetermined loop count is reached, inputting the third value to a Montgomery modular exponentiation function for generating a Montgomery conversion parameter, and converting a first conversion value in an integer domain into a second conversion value in a Montgomery domain.

The invention relates to a modular multiplication method and device based on a parallel array architecture, computing equipment and a medium. The method comprises the following steps: performing initialization processing on variables of all processing units to obtain initial variable data; according to a preset calculation parameter and the input data set, performing data updating on the initial variable data to obtain a data updating result; and determining a modular multiplication calculation result based on the data updating result, the input data set and a preset modular multiplication parameter. By the adoption of the method, it is ensured that all the processing units are in the same state at the beginning of calculation, and calculation confusion caused by initial value difference is avoided; data processing is carried out according to the preset calculation parameters and the input data set, and each processing unit can efficiently complete own tasks in the process, so that unnecessary calculation and waiting time is reduced; and then the input data set, the updated data updating result and the preset modular multiplication parameter are combined for calculation, so that the accuracy and reliability of modular multiplication calculation are effectively improved.

The invention discloses a Riscv instruction-based SRT operational circuit, which comprises an input module, a floating point conversion module, a calculation module and an output module, and is characterized in that the input module is configured to output an initial operand based on the Riscv instruction, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; the calculation module is configured to perform division operation or complementation operation by adopting a first operand; and when the initial operand is a floating-point number, the calculation module is configured to perform division operation or root extraction operation by adopting the initial operand, and the output module is configured to output a calculation result after the calculation of the calculation module is completed, so that the power consumption and the area of the circuit are reduced, the hardware cost is reduced, and the universality and the working performance of the circuit are improved.

The present disclosure relates to a reciprocal operation apparatus and a processor. The reciprocal operation apparatus includes a lookup table circuit configured to find out a second operand which is a reciprocal of a first operand from a preset reciprocal operation table according to the first operand, wherein the preset reciprocal operation table includes a plurality of entries, each of which is configured to represent an operand and a reciprocal of the operand.

Method for determining a modular inverse of a number Q modulo a module P, Q and P being prime numbers, P being masked in first parts, the method comprising the determinations: - (S2) of a first and a second non-zero multiplicative masks which are prime to each other, - (S4) of another masked module by applying the first multiplicative mask to the module, - (S6) of a masked number equal to the product of the second multiplicative mask and the number, - (S10) of an intermediate inverse D resulting from a multiplication of a multiplicative inverse of the other masked module by the first multiplicative mask modulo the masked number, - (S12) of each second part of a masking of a dividend having the value (-D ▪ P + 1) mod N with N equal to P ▪ Q, with the multiplication of D and of a third distinct part of the same masking of the module, - (S14) of the exact division of the dividend by Q, in hidden form.

According to various embodiments, a security device is provided comprising a modular reducer configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word, wherein each binary number consists of n bits by one or more first iterations comprising, in reaction to a first detector of the security device detecting that the most significant bit (MSB) of the binary number is set, changing the binary number by deleting its MSB and adding the difference between 2n−1 and the modulus to the binary number, followed by one or more second iterations comprising, in reaction to a second detector of the security device detecting that the MSB of the sum of the binary number with the difference between 2n−1 and the modulus is set, setting the binary number to that sum, wherein the MSB of the sum is deleted.

Computer-implemented method for determining a Gaussian integer congruent to a given Gaussian integer modulo a Gaussian integer modulus, wherein the norm of the Gaussian integer is smaller than the norm of the square of the Gaussian integer modulus, wherein a real integer base raised to a first integer exponent having a norm larger than that of the real and larger than that of the imaginary part of the Gaussian integer modulus is considered, wherein a second integer exponent is considered that is equal to or smaller than -2 and wherein a third integer exponent is considered, that is equal to or larger than the first integer exponent raised by one, and wherein a variable value candidate for the Gaussian integer congruent is considered that is first initialized with the given Gaussian integer and wherein the Gaussian integer is, either fully or in truncated form, decremented by a multiple of the Gaussian integer modulus, wherein the multiple of the Gaussian integer modulus is evaluated by calculating an auxiliary product of a component-wisely down rounded quotient of the current value of the variable value candidate for the Gaussian integer congruent and the real integer base raised to the sum of the first integer exponent and the second integer exponent with a prefactor and by calculating a component-wisely down rounded quotient of this auxiliary product and the real integer base raised to the difference of the third integer exponent and the second integer exponent and multiplying this latter quotient with the Gaussian integer modulus. In the Computer-implemented method for determining a reduction of a given Gaussian integer modulo a Gaussian integer modulus first a Gaussian integer congruent to a modulo reduction of a given Gaussian integer modulo a Gaussian integer modulus is determined with the method described before and the Gaussian integer congruent is further reduced with a final reduction. These methods are used in computer-implemented cryptographic methods and error-correction methods.

The invention discloses a modular inverse operation hardware implementation method and device and electronic equipment, and belongs to the technical field of computers. The method comprises the following steps: for a module value p of a target elliptic curve, pre-calculating a plurality of secondary parameters related to the module value p, and issuing the secondary parameters to a chip for caching; the secondary parameters comprise a plurality of Montgomery domain basic parameters and auxiliary parameters obtained based on p shift operation; matching a target Montgomery domain basic parameter from the plurality of Montgomery domain basic parameters according to a combination of an input data form and an output data form of modular inverse operation to serve as a modal conversion parameter; initializing a plurality of operation variables according to input data of modular inverse operation, a modular value p and a modal conversion parameter; and performing modular inverse operation on the plurality of operation variables based on the auxiliary parameters to obtain output data of the modular inverse operation. The hardware resource occupation of modular inverse operation can be reduced, and the operation efficiency is improved.

The application discloses a large number modular multiplication acceleration method and architecture based on static random access memory (SRAM) in-memory computing. According to the input multiplicand, multiplier and modulus, the modular multiplication operation is decomposed into multiple large integer multiplication operations based on the Barrett modular multiplication process. According to the components in the decomposed large integer multiplication operations as the polling operands, the components are sequentially input into the in-memory computing multiplication-addition macro array in the SRAM to perform multiplication-addition operations and generate partial sums. The partial sums are aggregated and added to obtain the execution results of the large integer multiplication operations. The execution results are subjected to a shift and truncation operation, and the results after the shift and truncation are subtracted from the modulus to obtain the modular multiplication result of the multiplicand and the multiplier with respect to the modulus. The application reduces the iteration number and resource occupation of high-bit-width modular multiplication operation through hardware reuse and parallel scheduling based on the SRAM in-memory computing and the Barrett modular multiplication process, and improves the operation efficiency and scalability.

Apparatus and methods for prime field modular reduction are described. As an example, a customized modular reduction digital circuit is described for reducing an n-bit integer based on a modulus, where the modulus includes a k-bit integer for use with a cryptographic algorithm. A customized modular reduction digital circuit includes a first circuit to generate at least two partial results by processing: (1) k lower order significant bits of an n-bit integer, and (2) at least a subset of bits for a congruent representation corresponding to any n-k higher order bits of the n-bit integer whose significance is higher than the most significant bit of the k-bit integer. The customized modular reduction digital circuit also includes a second circuit to process the at least two partial results output by the first circuit to generate a reduced version of the n-bit integer for use with the cryptographic algorithm.

A processing unit includes a redundant residue number generation circuit configured to convert first operand data and second operand data into a plurality of first operand redundant residue number sets, and a plurality of second operand redundant residue number sets based on a redundant residue number system (RRNS) using first to T-th moduli. T is a natural number equal to or greater than four. The processing unit includes a plurality of arithmetic circuits configured to perform operations using the plurality of first operand redundant residue number sets and the plurality of second operand redundant residue number sets, and a reconstruction circuit configured to recover result data based on the RRNS into result data based on a weighted number system.

The method of generating a child public key with a hardware wallet apparatus having a housing enclosing a cavity and at least one printed circuit board located in the cavity, and a computing device mounted to the at least one printed circuit board, the computing device having a hardware-implemented elliptic curve function, the method generally has: generating a parent public key using the hardware-implemented elliptic curve function of the computing device, a parent private key, and a first number registered in a memory of the computing device; subsequently to said generating the parent public key, resetting the first number in the memory of the computing device; and subsequently to said resetting the first number; generating a child public key using the hardware-implemented elliptic curve function of the computing device, a child private key, and the first number registered in the memory of the computing device.

A processor with an elliptic curve cryptography algorithm and a processing method thereof, including a register storing a public key pointer pointing to a public key. In response to a single elliptic curve cryptography algorithm instruction of an instruction set architecture, the processor obtains a plaintext input from a first memory space, performs an elliptic curve cryptography algorithm encryption operation on the plaintext input using the public key obtained through the register, encrypts the plaintext input into a ciphertext output, and writes the ciphertext output to a second memory space.

To protect content from an unauthorized access.SOLUTION: A permutation algorithm using modular arithmetic is applied to cells of one or more specific fields of a database or other file type. This permutation reorders the cells of the one or more specific fields without altering content of any individual cell, thereby hiding relationships between cells of the one or more permuted fields and the other information in the associated records. The permutation algorithm may use modular addition and modular subtraction, in either order. Different permutation algorithms may use varying numbers of parameters. To locate a specific cell in a permuted field, the parameter(s) from the permutation, identification information of the specific record associated with the cell, and identification information of the specific permuted field are applied in a modular arithmetic operation.SELECTED DRAWING: None

The invention relates to a calculation accelerator (10) adapted to carry out calculations according to a first cryptosystem and a second cryptosystem, the first cryptosystem being a lattice-based cryptosystem and the second cryptosystem being a code-based cryptosystem, the calculation accelerator (10) comprising several calculation modules, each calculation module applying an operation on input signals to obtain an output signal, namely: - a first calculation module (M1) configurable to implement modular addition or carryless addition, - a second calculation module (M2) configurable to implement identity with relation to one of the input signals, modular subtraction, modular addition and carryless addition, - a third calculation module (M3) configurable to implement integer multiplication and carryless multiplication, and - a fourth calculation module (M4) configurable to implement identity with relation to one of the input signals; modular subtraction, modular addition and carryless addition.

The invention relates to a kernel mode network coding and decoding method based on inline assembly matrix operation, which comprises the following steps of: constructing a kernel module, and inputting an input parameter into the kernel module for coding or decoding; the kernel module comprises Cauchy coding and Cauchy decoding; the Cauchy coding and the Cauchy decoding comprise the following steps of: 1, pre-allocating a memory, and initializing a multiplication table and a division table; 2, generating a Cauchy matrix; when coding is needed, executing the step 3; when decoding is needed, executing the step 4; 3, coding the input parameters by using Cauchy coding, and accelerating calculation by using an SIMD instruction set acceleration module to obtain coded data; and 4, decoding the input parameters by using Cauchy decoding, accelerating calculation by using an SIMD instruction set acceleration module, and outputting decoded original input data. Through the modular design, the flexibility and reusability of the system are improved, the network coding and decoding functions can be loaded and unloaded as required, and maintenance and upgrading are facilitated.

The invention relates to a calculation accelerator (10) adapted to carry out calculations according to a first cryptosystem and a second cryptosystem, the first cryptosystem being a lattice-based cryptosystem and the second cryptosystem being a code-based cryptosystem, the calculation accelerator (10) comprising several calculation modules, each calculation module applying an operation on input signals to obtain an output signal, namely: - a first calculation module (M1) configurable to implement modular addition or carryless addition, - a second calculation module (M2) configurable to implement identity with relation to one of the input signals, modular subtraction, modular addition and carryless addition, - a third calculation module (M3) configurable to implement integer multiplication and carryless multiplication, and - a fourth calculation module (M4) configurable to implement identity with relation to one of the input signals; modular subtraction, modular addition and carryless addition.

The invention discloses an elliptic system derivative parameter fast calculation disc which comprises a center ring, and the center ring is sequentially connected with a middle ring and a side ring through a mortise and tenon structure. A pointer is fixed to the center of the center ring through a fixing shaft. Scales are arranged on the central ring, the middle ring and the side rings; the pointer is in a rectangular shape with an opening on one side, and the opening end of the pointer clamps the circle center of the center ring through a fixing shaft. The method overcomes the defects that manual calculation is large in labor amount and large in repeated labor amount, simplifies deep theoretical tedious calculation and numerous and jumbled data searching into simple operation of one-to-one-pair, has the advantages of wonderful conception, scientific design, simple structure, simple and convenient operation, easy popularization, high applicability, low cost, convenience in carrying and the like, and is suitable for popularization and application. Good popularization and application prospects are realized.