290results about "Computations using residue arithmetic" patented technology

A method comprises receiving a modulus for a number-theoretic transform of a polynomial and selecting a plurality of prime moduli whose product forms the modulus for the number-theoretic transform, wherein the plurality of prime moduli are selected by giving preference to prime moduli having fewer ones in a binary representation of the prime moduli. For each prime modulus in the plurality of prime moduli: dividing a coefficient of the polynomial into segments and performing modular reduction of the segments relative to the prime modulus. Performing the modular reduction of at least one segment comprises implementing a multiplication of a value by a modular reduction of a base value relative to the prime modulus using a shift-add-unit having a smaller area requirement than a modular multiplier. A modular reduction of the coefficient relative to the prime modulus is determined based on the modular reductions of the segments.

A processor includes an instruction fetch unit that fetches instructions to be executed, an architected register file including a plurality of registers for storing source and destination operands, and an execution unit for executing a Galois multiply instruction. The execution unit includes a carryless multiplier configured to multiply operands of the Galois multiply instruction to generate a product. The execution unit further includes a modular reduction circuit configured to receive the product and determine, based on a logical combination of the product and a fixed polynomial, a reduced product having a fewer number of bits than the product. The execution unit is configured to store the reduced product to the architected register file as a result of the Galois multiply instruction.

The invention provides an efficient calculation method and device for polynomial modular multiplication based on a coaccelerator, and the method comprises the steps: obtaining an original polynomial pair, adjusting the coefficient of each original polynomial in a preset modulus range into a format for number theory transformation, and obtaining a preprocessed polynomial; the time domain coefficient of the preprocessed polynomial is converted into frequency domain representation by executing NTT transformation, and polynomial frequency domain representation is obtained; loading the polynomial frequency domain representation from a memory, and carrying out element-by-element dot multiplication on the polynomial frequency domain representation in parallel by a plurality of processing units in the co-accelerator; reading the point multiplication result, and performing NTT (inverse number theory) transformation on the point multiplication result to convert the frequency domain data into time domain representation so as to obtain polynomial time domain representation; and the processor adjusts the polynomial time domain representation to obtain a polynomial modular multiplication result of the original polynomial pair.

The invention discloses a sparse polynomial multiplication accelerator circuit applied to an HQC algorithm, and belongs to the field of post quantum cryptography algorithm hardware acceleration. Comprising a sparse polynomial non-zero coefficient index register set, a state register set, a multiplication and addition unit, a control state machine and an address generation module. The sparse polynomial non-zero coefficient index register set is used for storing indexes of sparse polynomial non-zero coefficients and providing the indexes for the control state machine, and the control state machine further inputs the obtained indexes to the address generation module; the state register group is used for configuring and representing the working state of the accelerator, storing information of registers and providing information for the address generation module and the control state machine; the address generation module is used for calculating address information and feeding back a result to the control state machine; and the control state machine reads the coefficient of the dense polynomial from the external RAM and inputs the coefficient into the multiplication and addition unit for calculation, and after the multiplication and addition unit completes calculation, the control state machine writes a calculation result into the external RAM.

The invention discloses a hardware acceleration system and method based on a multi-core architecture and related equipment, and relates to the technical field of computers, the hardware acceleration system based on the multi-core architecture comprises a CPU and a field programmable gate array based on the multi-core architecture, the field programmable gate array based on the multi-core architecture comprises a plurality of multi-scalar calculation acceleration cores; the CPU splits a multi-scalar multiplication task into a plurality of multi-scalar multiplication subtasks, and sends the plurality of multi-scalar multiplication subtasks to the field programmable gate array based on the multi-core architecture; the field programmable gate array based on the multi-core architecture receives the plurality of multi-scalar multiplication subtasks, and respectively processes the corresponding split multi-scalar multiplication subtasks based on the plurality of multi-scalar calculation acceleration cores; according to the invention, the hardware resource utilization rate of the field programmable gate array is improved.

The SRT operational circuit comprises an input module, a floating point conversion module, a calculation module and an output module, the input module is configured to output an initial operand, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; if the calculation module is configured to perform division operation or root extraction operation by adopting the first operand based on the SRT algorithm, the output module is configured to perform mantissa rounding on a division result or a root extraction result after the calculation of the calculation module is completed and output a floating point result, so that the operation accuracy of an integer in the circuit is improved, and the universality of the circuit is improved.

In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

The embodiment of the invention provides a method and a device for determining processing parameters for a rounding multiplication circuit and a modulo multiplication circuit. The method for determining the processing parameters of the rounding multiplication circuit comprises the steps that a low-order transformation matrix used for modular multiplication is obtained, the target modulus of the modular multiplication is k-th power of r, when the low-order transformation matrix is used for applying combined operation to multiplier segments of two multipliers, the operation result shows a low-order partial segment of a product, and the lower-order partial segment of the product is k-th power of r; wherein the multiplier segment is determined by dividing a multiplier into k segments with a cardinal number of r. Secondly, target transformation is conducted on the low-order transformation matrix through a mapping matrix in an inverse diagonal form, a high-order transformation matrix used for rounding multiplication is obtained, rounding multiplication is conducted on a target modulus, and when the high-order transformation matrix is used for applying the combined operation to a multiplier segment, an operation result shows a high-order part segment of a product; the high-order transformation matrix is used as a processing parameter of the rounding multiplication circuit.

Provided in the present application is a fast modular multiplication system based on base transformation. The fast modular multiplication system comprises: a precomputation layer, which is used for performing base transformation processing on a first modular multiplication input A and a second modular multiplication input B, which are inputted; a polynomial modular multiplication layer, which is used for sequentially performing grouped multiplication processing and recombination and reduction processing on the first modular multiplication input A and the second modular multiplication input B which have been subjected to base transformation processing; an iterative reduction layer, which is used for sequentially performing several instances of mapping and wiring processing and accumulation processing on a polynomial which has been subjected to the recombination and reduction processing and includes the first modular multiplication input A and the second modular multiplication input B; and a radix restoration layer, which is used for converting, from a radix-X to binary, a polynomial which has been subjected to the last instance of accumulation processing and includes the first modular multiplication input A and the second modular multiplication input B. In the present application, the fast modular multiplication system reduces the usage of circuit hardware, and thus the area of a circuit is saved on, and more advantages in terms of both area and speed exist compared with a conventional modular multiplication system.

The invention discloses a privacy protection neural network reasoning method based on multi-point evaluation. According to the method, in the reasoning process of the privacy protection neural network, a given nonlinear function is constructed into a K-segment k-degree polynomial, a safe multiplication tree and a safe remainder tree are established, and then the remainder polynomial is safely evaluated. Due to the fact that the polynomial power needing to be evaluated in the online stage is reduced, the number of self-multiplication terms is reduced, the number of communication rounds of overall polynomial evaluation is reduced, the number of calling times of a secure multiplication triple in secret sharing is reduced, and the overhead of offline pre-calculation is correspondingly reduced. In addition, the hierarchical structure of the secure multiplication tree and the remainder tree supports multi-point input parallel computing, and the parallel computing capability of a modern multi-core processor or a GPU can be fully utilized.

Computer-implemented methods for locking a blockchain transaction based on undetermined data are described. The invention is implemented using a blockchain network. This may, for example, be the Bitcoin blockchain. A locking node may include a locking script in a blockchain transaction to lock a digital asset. The locking script includes a public key for a determined data source and instructions to cause a validating node executing the locking script to verify the source of data provided in an unlocking script by: a) generating a modified public key based on the public key for the determined data source and based on data defined in the unlocking script; and b) evaluating a cryptographic signature in the unlocking script based on the modified public key. The blockchain transaction containing the locking script is sent by the locking node to the blockchain network. The lock may be removed using a cryptographic signature generated from a private key modified based on the data.

Provided are a device, system, and computer program product for a near memory processing device to process coefficient elements resulting from decomposition of polynomials. A near memory processing device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. Coefficients of a polynomial are decomposed into a number of levels of the coefficient elements. Each level of coefficient elements comprises a limb. A device control receives hierarchical commands, from an application, that map operations to perform on limbs of coefficient elements to the enclaves and that map operations for the enclaves to the tiles in the enclaves. The device controller distributes operations for the tiles in the hierarchical commands to perform on the coefficient elements to the enclaves to distribute operations to perform on the coefficient elements to the tiles.

The invention discloses a low-delay Montgomery modular multiplier. The modular multiplier comprises an iteration control unit, a parallel part and generation unit, a quotient operation unit of a multi-stage pipeline, an output shifting unit, a part and compression unit and a final reduction unit. According to the modular multiplier, an intermediate result of each round of iteration is expressed in a triple form, and the number of compression stages is reduced while long-bit-width addition is avoided. According to the method, shift operation is introduced, the quotient operation process is dispersed to a plurality of cycles for pipeline implementation, at the cost of introducing a plurality of additional cycles, the key path of each round of iteration is greatly shortened, the overall output delay of the modular multiplier is greatly reduced, the method is suitable for scenes with high-speed operation requirements, and the longer the modulus length is, the more obvious the acceleration effect is.

A method of operating a homomorphic encryption operation accelerator includes performing a number theoretic transform (NTT) operation on each of first homomorphic ciphertext and second homomorphic ciphertext, and performing a base conversion operation by adding a partial sum using a first value of the NTT operation.

The invention discloses an integer divider and method for realizing Radix-16 operation, a chip and electronic equipment, and belongs to the technical field of electronics. The integer divider comprises a preprocessing module, an iterative calculation module and a post-processing module, wherein the iterative calculation module comprises four levels of Radix-2 sub-operation modules which are connected in sequence; the step of generating the 1-bit quotient and the remainder update by the current-level Radix-2 in the primary iteration Radix-16 comprises the following steps of: obtaining an initialized divisor d and a partial remainder wj; determining a 1-bit quotient qj of the current level Radix-2 according to the partial remainder wj; obtaining an updated partial remainder wj + 1 according to a preset iteration recursion rule, and outputting the updated partial remainder wj + 1 to a next-level Radix-2 sub-operation module; and the post-processing module combines the 1-bit quotients generated by each level of Radix-2 to generate 4-bit quotients, and combines the 4-bit quotients as a final quotient value of Radix-16 division operation.

A computer-implemented method includes receiving performing a fused modular multiply and add operation to compute d=((a*b)+c) % p, wherein a, b, and c, are provided as a set of operands. A first multiply-and-accumulate unit computes a binary multiplication to compute a*b. A second multiply-and-accumulate unit computes a first intermediate result by updating a result of the binary multiplication using p. An accumulator of a third multiply-and-accumulate unit is initialized with c. The third multiply-and-accumulate unit computes a second intermediate result using the first intermediate result and c. An adder unit subtracts a portion of the second intermediate result from a portion of the result of the binary multiplication. The output of the adder is provided as a result of the fused modular multiply and add operation.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

The invention relates to a modular multiplication compressor circuit, belongs to the technical field of design of modular multipliers and compressors, and solves the problems of long data transmission delay, high hardware overhead and poor flexibility of discrete modular multipliers and compressors in the prior art. The input configuration unit is used for generating first to-be-processed data, a first initial processing parameter, a second initial processing parameter and a third initial processing parameter; the data initial processing unit is used for performing data processing on the first to-be-processed data and the second to-be-processed original data based on the first initial processing parameter, the second initial processing parameter and the third initial processing parameter to generate initial processing output data and quotient calculation output data; the switching unit is used for sending the initial processing output data to the compression processing unit or the modular multiplication processing unit; the compression processing unit is used for generating compression data based on the initial processing output data, the quotient solving output data and the modulus; and the modular multiplication processing unit is used for generating modular multiplication data based on the initial processing output data, the third initial processing parameter and the modulus.

Provided in the present application are a quantum circuit construction method and apparatus, and a device, a storage medium and a product. The method comprises: preparing, on the basis of a modulus N, a first quantum register that comprises 2n first quantum bits and a second quantum register that comprises n first quantum bits, n being the binary expansion length of the modulus N; obtaining an equal-probability quantum superposition state of the first quantum register by constructing a Hadamard gate; constructing a first modular multiplication module and 2n-1 second modular multiplication modules on the second quantum register; sequentially using a plurality of first quantum bits as control bits, sequentially using the first modular multiplication module and the 2n-1 second modular multiplication modules as controlled parties, and constructing 2n controlled unitary gates; and performing inverse Fourier transformation and measurement on the first quantum register to obtain a phase estimation result corresponding to a modular function period r. The solution of the present application provides support for solving the problem of larger-scale computation.

Provided are a near memory device, system, and method for processing coefficient elements resulting from decomposition of polynomials. The near memory device includes a plurality of enclaves and a plurality of interconnected tiles on each enclave. A tile includes a memory and a processing element to perform operations on decomposed coefficients stored in the memory of the tile. An enclave controller in an enclave of the enclaves receives an operation for coefficients of a polynomial. Each of the coefficients are decomposed into a number of levels of coefficient elements. The enclave controller distributes the coefficient elements to the tiles in the enclave to have processing elements of the tiles load and process the coefficient elements and store the processed results.

The embodiment of the invention provides a modular reduction circuit, a modular reduction method and a method for determining circuit design parameters. The modular reduction circuit is used for calculating a modular result of an operand with a 2n-bit width on a preset modulus M with an n-bit width, and specifically comprises a lookup table circuit which comprises d lookup tables realized by a storage unit and d first sub-results for lookup of data corresponding to d fragments to perform modular operation on M, and the d fragments are obtained by dividing high (n-m)-bit data of the operand; the adding circuit comprises a plurality of adders and is used for accumulating the d first sub-results to obtain a second sub-result; the iteration circuit comprises a first subtracter and is used for calculating to obtain a third sub-result of the low n + m-bit data of the operand for modulo M through an iteration subtraction mode; the fusion circuit is used for fusing the second sub-result and the third sub-result to obtain a fourth sub-result; and the adjusting circuit is used for performing subtraction-based adjustment on the fourth sub-result to obtain a modulo result.

According to an embodiment, an arithmetic device outputting an arithmetic result on a finite field with characteristic P includes a hardware processor. The hardware processor performs readout processing of a plurality of input values. The hardware processor performs, for each word, arithmetic operations with respect to the plurality of input values by using a value being based on the characteristic P and a comparison value between each input value of the plurality of input values and the characteristic P. The hardware processor outputs a first output value resulting from computing a value being based on each input value of the plurality of input values, the comparison value, and the characteristic P. The hardware processor outputs a second output value resulting from comparing the first output value and the characteristic P.

The invention discloses a one-dimensional structured data hypothesis test evaluation method based on zero-knowledge proof, and aims to verify and evaluate the distribution consistency of synthetic data and real data under the condition of strictly protecting the real data and sensitive statistical information thereof. The method comprises the following steps: firstly, for discrete variables and continuous variables, respectively calculating an expected frequency and an observation frequency by adopting a category frequency statistics mode and an equal-width binning mode, and measuring the distribution deviation of synthetic data and real data by adopting chi-square goodness of fit test; and then reconstructing the calculation process of the test statistics into an equivalent form only containing integer addition and multiplication so as to adapt to finite field calculation. And based on the integer formula, constructing a constraint circuit and generating a zero-knowledge proof. According to the invention, a prover can prove the correctness of the hypothesis test result to a verifier under the condition that real data is not disclosed, so that the privacy of the real data is guaranteed, and the credible evaluation of the effectiveness of the synthetic data is realized.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

A modular operation device for handling a modular multiplication, comprises a controller, configured to divide a multiplicand into a plurality of multiplicand words, a multiplier into a plurality of multiplier words, and a modulus into a plurality of modulus words; a first plurality of processing elements, coupled to the controller, configured to compute a first plurality of updated carry results and a first plurality of updated sum results; a second plurality of processing elements, coupled to the controller, configured to compute a second plurality of updated carry results and a second plurality of updated sum results; and a reduction element, coupled to the controller, configured to compute a resulting remainder according to the second plurality of updated carry results and the second plurality of updated sum results.

A decompression method determines image element values from compressed data representing a block of image element values relating to a respective one or more channels. For each of the channels, an indication of a first number of bits representing difference values between the data values and an origin value for the channel is read from the compressed data. For each of the channels, a second number of bits is obtained, wherein representations of the difference values for each of the channels are included in the compressed data using the second number of bits for that channel. The obtained second numbers of bits for the respective channels are used to read the representations of the difference values for the image element values being decompressed. Based on the representations of the difference values, a difference value is determined in accordance with the first number of bits for the channel. For each of the one or more channels, the data value relating to the channel for each of the image element values being decompressed is determined using: (i) the origin value for the channel, and (ii) the determined difference value for the channel for the image element value.