190results about "Computations using residue arithmetic" patented technology

The SRT operational circuit comprises an input module, a floating point conversion module, a calculation module and an output module, the input module is configured to output an initial operand, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; if the calculation module is configured to perform division operation or root extraction operation by adopting the first operand based on the SRT algorithm, the output module is configured to perform mantissa rounding on a division result or a root extraction result after the calculation of the calculation module is completed and output a floating point result, so that the operation accuracy of an integer in the circuit is improved, and the universality of the circuit is improved.

The invention discloses a privacy protection neural network reasoning method based on multi-point evaluation. According to the method, in the reasoning process of the privacy protection neural network, a given nonlinear function is constructed into a K-segment k-degree polynomial, a safe multiplication tree and a safe remainder tree are established, and then the remainder polynomial is safely evaluated. Due to the fact that the polynomial power needing to be evaluated in the online stage is reduced, the number of self-multiplication terms is reduced, the number of communication rounds of overall polynomial evaluation is reduced, the number of calling times of a secure multiplication triple in secret sharing is reduced, and the overhead of offline pre-calculation is correspondingly reduced. In addition, the hierarchical structure of the secure multiplication tree and the remainder tree supports multi-point input parallel computing, and the parallel computing capability of a modern multi-core processor or a GPU can be fully utilized.

Computer-implemented methods for locking a blockchain transaction based on undetermined data are described. The invention is implemented using a blockchain network. This may, for example, be the Bitcoin blockchain. A locking node may include a locking script in a blockchain transaction to lock a digital asset. The locking script includes a public key for a determined data source and instructions to cause a validating node executing the locking script to verify the source of data provided in an unlocking script by: a) generating a modified public key based on the public key for the determined data source and based on data defined in the unlocking script; and b) evaluating a cryptographic signature in the unlocking script based on the modified public key. The blockchain transaction containing the locking script is sent by the locking node to the blockchain network. The lock may be removed using a cryptographic signature generated from a private key modified based on the data.

The invention discloses an integer divider and method for realizing Radix-16 operation, a chip and electronic equipment, and belongs to the technical field of electronics. The integer divider comprises a preprocessing module, an iterative calculation module and a post-processing module, wherein the iterative calculation module comprises four levels of Radix-2 sub-operation modules which are connected in sequence; the step of generating the 1-bit quotient and the remainder update by the current-level Radix-2 in the primary iteration Radix-16 comprises the following steps of: obtaining an initialized divisor d and a partial remainder wj; determining a 1-bit quotient qj of the current level Radix-2 according to the partial remainder wj; obtaining an updated partial remainder wj + 1 according to a preset iteration recursion rule, and outputting the updated partial remainder wj + 1 to a next-level Radix-2 sub-operation module; and the post-processing module combines the 1-bit quotients generated by each level of Radix-2 to generate 4-bit quotients, and combines the 4-bit quotients as a final quotient value of Radix-16 division operation.

Devices, systems, and methods for secure modular addition and subtraction are provided. A modular adder and subtractor circuit with masking circuit includes an arithmetic to Boolean (A2B) conversion operator configured to convert (i) a second sum and (ii) a value determined based on a first sum, to Boolean resulting in first and second Boolean values, a shifter configured to (i) make a most significant bit of the first Boolean value a least significant bit resulting in a shifted first Boolean value and (ii) make the most significant bit of the second Boolean value a least significant bit resulting in a shifted second Boolean value, and a Boolean to arithmetic (B2A) conversion operator, configured to convert a representation of the shifted first Boolean value and a representation of the shifted second Boolean value to arithmetic representation resulting in first and second arithmetic values, respectively.

The embodiment of the invention provides a modular reduction circuit, a modular reduction method and a method for determining circuit design parameters. The modular reduction circuit is used for calculating a modular result of an operand with a 2n-bit width on a preset modulus M with an n-bit width, and specifically comprises a lookup table circuit which comprises d lookup tables realized by a storage unit and d first sub-results for lookup of data corresponding to d fragments to perform modular operation on M, and the d fragments are obtained by dividing high (n-m)-bit data of the operand; the adding circuit comprises a plurality of adders and is used for accumulating the d first sub-results to obtain a second sub-result; the iteration circuit comprises a first subtracter and is used for calculating to obtain a third sub-result of the low n + m-bit data of the operand for modulo M through an iteration subtraction mode; the fusion circuit is used for fusing the second sub-result and the third sub-result to obtain a fourth sub-result; and the adjusting circuit is used for performing subtraction-based adjustment on the fourth sub-result to obtain a modulo result.

According to an embodiment, an arithmetic device outputting an arithmetic result on a finite field with characteristic P includes a hardware processor. The hardware processor performs readout processing of a plurality of input values. The hardware processor performs, for each word, arithmetic operations with respect to the plurality of input values by using a value being based on the characteristic P and a comparison value between each input value of the plurality of input values and the characteristic P. The hardware processor outputs a first output value resulting from computing a value being based on each input value of the plurality of input values, the comparison value, and the characteristic P. The hardware processor outputs a second output value resulting from comparing the first output value and the characteristic P.

The invention discloses a one-dimensional structured data hypothesis test evaluation method based on zero-knowledge proof, and aims to verify and evaluate the distribution consistency of synthetic data and real data under the condition of strictly protecting the real data and sensitive statistical information thereof. The method comprises the following steps: firstly, for discrete variables and continuous variables, respectively calculating an expected frequency and an observation frequency by adopting a category frequency statistics mode and an equal-width binning mode, and measuring the distribution deviation of synthetic data and real data by adopting chi-square goodness of fit test; and then reconstructing the calculation process of the test statistics into an equivalent form only containing integer addition and multiplication so as to adapt to finite field calculation. And based on the integer formula, constructing a constraint circuit and generating a zero-knowledge proof. According to the invention, a prover can prove the correctness of the hypothesis test result to a verifier under the condition that real data is not disclosed, so that the privacy of the real data is guaranteed, and the credible evaluation of the effectiveness of the synthetic data is realized.

A multi-bit linear-feedback shift register (LFSR) counter comprises a plurality of flip-flops serially coupled to one another with a separate flip-flop for each bit of a number of bits of the multi-bit counter, wherein each flip-flop has an individual binary value that, when combined with binary values of the other flip-flops, generates a unique sequence of bits representative of a unique state for the plurality of flip-flops; exclusive-or (XOR) logic between a pair of flip-flops based upon, at least in part, a plurality of taps for a primitive polynomial defined for the number of bits; and a look-up read-only table (LUT) mapping the unique sequence of bits generated by the plurality of flip-flops to a sequential decimal count value based upon, at least in part, an initial unique sequence of bits generated by the plurality of flip-flops.

Provided is an NTT acceleration chip, including: a twiddle factor computing module, including a plurality of pre-computing units and a plurality of real-time computing units, where the plurality of pre-computing units is configured to compute several initial lines of twiddle factors and an inter-line step factor in parallel by using a primitive root of unity; and the plurality of real-time computing units is configured to repeatedly and iteratively compute other lines of twiddle factors in parallel according to the inter-line step factor; a transposition module, including a plurality of transposition units, configured to perform transposition processing on an input sequence in parallel, to obtain a transposed sequence; and an NTT computing module, including a plurality of butterfly computing units, configured to perform a butterfly operation of orders and a point quantity in parallel according to the twiddle factors and the transposed sequence, to obtain an output sequence.

A modular operation device for handling a modular multiplication, comprises a controller, configured to divide a multiplicand into a plurality of multiplicand words, a multiplier into a plurality of multiplier words, and a modulus into a plurality of modulus words; a first plurality of processing elements, coupled to the controller, configured to compute a first plurality of updated carry results and a first plurality of updated sum results; a second plurality of processing elements, coupled to the controller, configured to compute a second plurality of updated carry results and a second plurality of updated sum results; and a reduction element, coupled to the controller, configured to compute a resulting remainder according to the second plurality of updated carry results and the second plurality of updated sum results.

Methods and compression units for compressing a block of image data, the block of image data comprising a plurality of image element values, the image element values being divisible into at least a first value and a second value such that the block of image data comprises a two-dimensional block of first values, the method comprising: compressing a first data set comprising all or a portion of the two-dimensional block of first values in accordance with a first fixed-length compression algorithm to generate a first compressed block by: identifying common base information for the first data set; and identifying a fixed-length parameter for each first value in the first data set, the fixed-length parameter being zero, one or more than one bits in length; and forming a compressed block for the block of image data based on the first compressed block.

The application discloses an SRAM computing integrated NTT accelerator, a chip and electronic equipment, wherein the NTT accelerator comprises a computing integrated butterfly unit, an array decoder, a controller, a module approximation simple unit and an inter-column data router; the computing integrated butterfly unit is used for accelerating the NTT algorithm, realizing two kinds of butterfly operation operations, and storing input data of one-time butterfly operation and intermediate data generated in the calculation process; the array decoder and the controller are used for controlling the working state of each computing integrated butterfly unit when the butterfly operation is performed; the module approximation simple unit is used for processing the modulo operation of the data output after the multiplication of the multiplier is completed; the inter-column data router is connected with the input and output of each butterfly unit, is used for writing initial data into the butterfly unit, and is used for transmitting the calculation result of each stage to the corresponding unit, and preparing for the operation of the next stage. The application supports bit parallel operation, guarantees that the butterfly operation of one stage of NTT can be completed at the same time, and maximizes the operation efficiency.

The application discloses a privacy protection neural network inference method based on multi-point evaluation. K Segment k Polynomial, and a safe multiplication tree and a safe remainder tree are established, and then a remainder polynomial is safely evaluated. Since the polynomial power to be evaluated in the online stage is reduced, the number of self-multiplication items is reduced, thereby reducing the communication round number of overall polynomial evaluation, reducing the number of calls of the safe multiplication triplets in the secret sharing, and correspondingly reducing the offline pre-computation cost. In addition, the layered structure of the safe multiplication tree and the remainder tree supports parallel computation of multi-point input, and can fully utilize the parallel computation capacity of a modern multi-core processor or a GPU.

The invention relates to an apparatus and a method for number-theoretical transformation instructions. Instructions are executed for performing a number-theory transform (NTT). For example, one embodiment includes: a decode circuit to decode the instruction; one or more packed data registers to store a first, second, and third plurality of source packed data elements and corresponding result packed data elements; and execution circuitry to execute the NTT using a butterfly operation including Montgomery multiplication of a source packed data element of the second plurality of source packed data elements and a corresponding source packed data element of the third plurality of source packed data elements using a modulus value or an inverse of the modulus value to generate a product. The product is added to a corresponding source packed data element of the first plurality of source packed data elements to obtain a first result, and the product is subtracted from the corresponding source packed data element of the first plurality of source packed data elements to obtain a second result.

The present disclosure provides a method for generating an isogeny-based ring signature. The method includes executing a setup algorithm to establish public parameters includ¬ ing a base elliptic curve, generating key pairs for a plurality of users, and executing a signing algorithm by a signer. The signing algorithm involves selecting a random isogeny, iteratively computing isogenies, scalar values, basis points, subgroups, and additional isogenies for users in a ring, computing signer-specific isogenies and subgroups, deriving a dual isogeny, and outputting a ring signature comprising the computed isogenies and basis points. The method enables generation of an anonymous ring signature based on isogeny computations over elliptic curves, providing enhanced security in cryptographic systems.

A numerical conversion method for a public key cryptography system includes accumulating a first value by using a first modular addition loop according to the first value for generating a second value after a first predetermined loop count is reached, accumulating the second value by using a second modular addition loop according to the second value for generating a third value after a second predetermined loop count is reached, inputting the third value to a Montgomery modular exponentiation function for generating a Montgomery conversion parameter, and converting a first conversion value in an integer domain into a second conversion value in a Montgomery domain.

The invention discloses an update control method and device, a chip system, a storage medium and a program product, and belongs to the technical field of computers. The method comprises the following steps: after a first device receives an update query request sent by a second device, if it is determined that the second device has an update demand, mapping a device identifier of the second device to a random number in a preset numerical range, and obtaining a target equal value (n) according to the number of days between a preset date and a current date and a target equal value (n); determining a target value range corresponding to the current date in the preset value range; if the random number is not within the target value range, the second device is forbidden to perform silent updating on the current date; and if the random number is within the target value range, allowing the second device to perform silent updating on the current date. According to the method and the device, the original silent update traffic of all the second devices within one day is scheduled to n days, and uniform distribution of the traffic is realized, so that the downloading speed during silent update can be improved, and the user experience is improved.

The invention relates to a modular multiplication method and device based on a parallel array architecture, computing equipment and a medium. The method comprises the following steps: performing initialization processing on variables of all processing units to obtain initial variable data; according to a preset calculation parameter and the input data set, performing data updating on the initial variable data to obtain a data updating result; and determining a modular multiplication calculation result based on the data updating result, the input data set and a preset modular multiplication parameter. By the adoption of the method, it is ensured that all the processing units are in the same state at the beginning of calculation, and calculation confusion caused by initial value difference is avoided; data processing is carried out according to the preset calculation parameters and the input data set, and each processing unit can efficiently complete own tasks in the process, so that unnecessary calculation and waiting time is reduced; and then the input data set, the updated data updating result and the preset modular multiplication parameter are combined for calculation, so that the accuracy and reliability of modular multiplication calculation are effectively improved.

The invention provides an encryption and decryption method, an encryption and decryption system and computer equipment based on modular exponential operation. The encryption and decryption method comprises the following steps: receiving plaintext data, generating public key data, encrypting intermediate data and a first storage table; when the first index meets a preset condition, executing encryption modular index operation; when the repeated plaintext data is not stored in the first storage table, storing the updated plaintext data in the first storage table; when the repeated plaintext data is stored in the first storage table, obtaining the index position and the number of the plaintext data in the first storage table to obtain the encryption cycle length; judging whether the current first index meets a preset condition or not; when the current first index meets the preset condition, executing a second modular multiplication operation according to the current encrypted intermediate data, the preset loop data and the encrypted loop length; and when the current first index does not meet the preset condition, outputting the current encrypted intermediate data as ciphertext data. According to the method, modular exponent operation is optimized through circular detection, and the encryption and decryption efficiency is remarkably improved.

The invention discloses a Riscv instruction-based SRT operational circuit, which comprises an input module, a floating point conversion module, a calculation module and an output module, and is characterized in that the input module is configured to output an initial operand based on the Riscv instruction, a first end of the floating point conversion module is connected with the input module, a first end of the calculation module is connected with the floating point conversion module and the input module, and a second end of the calculation module is connected with the output module. The output module is connected with the second end of the calculation module; when the initial operand is an integer, the floating point conversion module is configured to perform floating point conversion on the initial operand to output a first operand; the calculation module is configured to perform division operation or complementation operation by adopting a first operand; and when the initial operand is a floating-point number, the calculation module is configured to perform division operation or root extraction operation by adopting the initial operand, and the output module is configured to output a calculation result after the calculation of the calculation module is completed, so that the power consumption and the area of the circuit are reduced, the hardware cost is reduced, and the universality and the working performance of the circuit are improved.

The present disclosure relates to a reciprocal operation apparatus and a processor. The reciprocal operation apparatus includes a lookup table circuit configured to find out a second operand which is a reciprocal of a first operand from a preset reciprocal operation table according to the first operand, wherein the preset reciprocal operation table includes a plurality of entries, each of which is configured to represent an operand and a reciprocal of the operand.

Method for determining a modular inverse of a number Q modulo a module P, Q and P being prime numbers, P being masked in first parts, the method comprising the determinations: - (S2) of a first and a second non-zero multiplicative masks which are prime to each other, - (S4) of another masked module by applying the first multiplicative mask to the module, - (S6) of a masked number equal to the product of the second multiplicative mask and the number, - (S10) of an intermediate inverse D resulting from a multiplication of a multiplicative inverse of the other masked module by the first multiplicative mask modulo the masked number, - (S12) of each second part of a masking of a dividend having the value (-D ▪ P + 1) mod N with N equal to P ▪ Q, with the multiplication of D and of a third distinct part of the same masking of the module, - (S14) of the exact division of the dividend by Q, in hidden form.

According to various embodiments, a security device is provided comprising a modular reducer configured to perform a modulo reduction by a modulus of each binary number of a sequence of binary numbers forming a data word, wherein each binary number consists of n bits by one or more first iterations comprising, in reaction to a first detector of the security device detecting that the most significant bit (MSB) of the binary number is set, changing the binary number by deleting its MSB and adding the difference between 2n−1 and the modulus to the binary number, followed by one or more second iterations comprising, in reaction to a second detector of the security device detecting that the MSB of the sum of the binary number with the difference between 2n−1 and the modulus is set, setting the binary number to that sum, wherein the MSB of the sum is deleted.

Computer-implemented method for determining a Gaussian integer congruent to a given Gaussian integer modulo a Gaussian integer modulus, wherein the norm of the Gaussian integer is smaller than the norm of the square of the Gaussian integer modulus, wherein a real integer base raised to a first integer exponent having a norm larger than that of the real and larger than that of the imaginary part of the Gaussian integer modulus is considered, wherein a second integer exponent is considered that is equal to or smaller than -2 and wherein a third integer exponent is considered, that is equal to or larger than the first integer exponent raised by one, and wherein a variable value candidate for the Gaussian integer congruent is considered that is first initialized with the given Gaussian integer and wherein the Gaussian integer is, either fully or in truncated form, decremented by a multiple of the Gaussian integer modulus, wherein the multiple of the Gaussian integer modulus is evaluated by calculating an auxiliary product of a component-wisely down rounded quotient of the current value of the variable value candidate for the Gaussian integer congruent and the real integer base raised to the sum of the first integer exponent and the second integer exponent with a prefactor and by calculating a component-wisely down rounded quotient of this auxiliary product and the real integer base raised to the difference of the third integer exponent and the second integer exponent and multiplying this latter quotient with the Gaussian integer modulus. In the Computer-implemented method for determining a reduction of a given Gaussian integer modulo a Gaussian integer modulus first a Gaussian integer congruent to a modulo reduction of a given Gaussian integer modulo a Gaussian integer modulus is determined with the method described before and the Gaussian integer congruent is further reduced with a final reduction. These methods are used in computer-implemented cryptographic methods and error-correction methods.

The embodiment of the invention discloses an integer division operation method and device, a medium and equipment, and the method comprises the steps: determining first data and second data which is used for carrying out division operation with the first data, and the first data and the second data are of an integer type; performing data type conversion on the first data to obtain floating point type third data; carrying out reciprocal operation on the third data through a reciprocal arithmetic unit to obtain fourth data of a floating point type; and carrying out multiplication operation on the second data and the fourth data through a multiplier so as to determine an operation result obtained by dividing the second data by the first data. According to the embodiment of the invention, integer division operation can be realized through universal hardware such as a reciprocal arithmetic unit and a multiplier, a special division operation circuit is avoided, and the hardware overhead is effectively reduced.