The invention discloses an RISC-V processor-oriented finite field modular operation acceleration implementation method. Comprising the following steps: 1, constructing an unsaturated multi-limb representation model of finite field elements in a 64-bit general register of a processor; 2, based on a multiplication instruction execution
delay characteristic of the RISC-V processor, designing a calculation and memory access interleaved
instruction scheduling strategy; 3, carrying out decoupling scheduling on
carry propagation and a modular reduction path by adopting a
delay correction mechanism in the general register; 4, aiming at modular square operation, constructing an instruction level reduction path in a processor
instruction set environment, and realizing cross-limb carry
processing through a logic shift instruction and an unsigned comparison instruction; and 5, realizing a
delay accumulation and
mask correction mechanism of modular addition and subtraction operation on a register level by using a redundant bit width represented by unsaturation. According to the method, on the premise of not changing the mathematical structure of the original cryptographic
algorithm, the operation acceleration which is several times of the existing implementation is realized by optimizing the register resources and
instruction scheduling of the processor.