46 results about "Parallel pipeline" patented technology

The invention relates to a fractional order PID (Proportion Integration Differentiation) control method and system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: 1, setting fractional order PID related parameters according to the requirements of a controlled object; 2, calculating a fractional order calculus weight coefficient according to the fractional order PID related parameters, and storing the fractional order calculus weight coefficient in the FPGA; 3, collecting a state feedback signal of the controlled object, and calculating an integral term operator and a differential term operator; step 4, calculating control output and performing amplitude limiting processing, and updating the state of the controlled object by using the control output after the amplitude limiting processing; and 5, repeating the steps 1-4 to realize fractional order PID closed-loop control. By optimizing a discrete convolution algorithm, adopting a parallel pipeline architecture and configurable parameter design and combining fixed-point number operation and security boundary constraint, the numerical stability and hardware security of the system under high-speed operation are ensured, the calculation speed is remarkably increased while the operation precision is ensured, and the method is suitable for large-scale popularization and application. And the method is suitable for control occasions with extremely high real-time requirements.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The invention relates to the technical field of production line scheduling, in particular to a production line resource scheduling control method and system, and the method comprises the steps: connecting end equipment of each production line through a parallel pipeline and a controllable valve to form a shared equipment resource pool, and obtaining the operation data information of each production line when a production request is received, the operation data information comprises the material flow and the equipment load rate of the end equipment, performing calculation based on the material flow and a preset target yield to obtain a demand calculation result, and dynamically scheduling the end equipment in the shared equipment resource pool based on the equipment load rate and the demand calculation result. According to the technical scheme of the invention, by constructing the'shared equipment resource pool ', the barrier that the resources of the traditional production lines are isolated is broken, and the elastic allocation and sharing of the resources across the production lines are realized, so that the resource utilization rate of the end equipment is improved, and the comprehensive output efficiency of the whole production system is improved.

The invention discloses a hardware-based SOFTMAX function calculation method and device. The hardware-based SOFTMAX function calculation method comprises the following steps: receiving a multi-dimensional input vector corresponding to an SOFTMAX function through an input port; uniformly dividing the multi-dimensional input vector into a plurality of data segments according to an element sequence through a channel distributor, and distributing the data segments to corresponding operation channels; performing an exponential operation on the data segment using the operation channel to generate a local exponential vector; aggregating the local exponent vectors with an accumulator to generate a global exponent sum; distributing the global index sum to each operation channel, so that the operation channels generate output sub-vectors according to the local index vectors and the global index sum; and splicing the output sub-vectors according to the element sequence through a recombination unit to generate an SOFTMAX output vector. The efficient SOFTMAX function hardware acceleration calculation under the multi-channel parallel pipeline processing architecture is realized, and the calculation performance and throughput are improved by several times compared with the traditional serial software implementation.

The application discloses a data synchronization method and system with full-link back pressure characteristics, comprising: configuring metadata of a synchronization task; starting incremental synchronization of a binlog log, and selectively performing full synchronization; routing generated add, delete, modify and query events to a distributed parallel Stream pipeline; and distributing the events to an Actor entity in an Actor model shard cluster according to dimension fields configured for each table in an asynchronous request response mode; performing event persistence and state updating, and complex conversion logic based on the current state, and returning the result to the Stream pipeline; performing message batching, sorting and deduplication processing on Response events by the Stream pipeline; writing the result to a Sink data source, and performing an asynchronous ACK mechanism to ensure reliable synchronization. The application can quickly realize complex model synchronization conversion between heterogeneous data sources through highly configurable synchronization tasks, and has the characteristics of short link, few components and efficient synchronization.

The invention discloses a quantum measurement and control instruction assembly line parallel processing system, which adopts a double-thread framework, connects a producer thread and a consumer thread through a limited-capacity buffer queue, and can ensure the execution sequence of quantum measurement and control instructions and improve the execution efficiency of the quantum measurement and control instructions at the same time. The problems that in an existing measurement and control equipment system, serial processing efficiency is low, and the resource utilization rate is insufficient are solved, namely the technical defects that when an upper computer generates an instruction, external equipment is idle, and when the external equipment executes the instruction, the upper computer is idle are overcome, and a parallel assembly line strategy of upper computer instruction generation and external equipment instruction execution is achieved. The processing efficiency and the resource utilization rate are remarkably improved, and the method has high universality, expandability and a perfect exception processing mechanism.

The embodiment of the invention discloses a method for evaluating the training income of a large model, a device for evaluating the training income of the large model, electronic equipment and a computer readable storage medium. The large model comprises a plurality of sub-modules. The method comprises the following steps: acquiring the actual operation execution duration of each sub-module in a plurality of sub-modules of the large model in a graphic calculation unit; obtaining a parallel pipeline strategy of the large model, wherein the parallel pipeline strategy indicates a strategy adopted when a plurality of devices train the large model in a distributed manner; based on the parallel pipeline strategy of the large model and the running time of each sub-module in the large model, executing a plurality of waiting operations in a central processing unit to simulate actual operations executed by each sub-module in a graphic computing unit; and determining a training revenue of the large model based on execution results of the plurality of waiting operations executed in the central processing unit.

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.

The invention discloses a distributed storage test acceleration method and device, electronic equipment and a storage medium, and relates to the technical field of distributed storage. Operation semantics and dependency relationship recognition is performed on a test case of a to-be-tested distributed storage system, and the test case is decomposed into test slices capable of being independently executed; and constructing a multi-layer parallel pipeline comprising a test environment preparation layer, a test data management layer, a test operation execution layer and a test result verification layer based on the dependency relationship to realize parallel processing of test slices. In the execution process, system resources and test slice execution states are monitored in real time, dynamic scheduling distribution is carried out according to monitoring results and dependency relationships, distributed collection and consistency verification are carried out on parallel execution results, and a test report is generated. The problems that in the prior art, due to linear execution of test cases, insufficient resource utilization and lack of systematicness of result verification, the test period is long, resource waste is serious, and test reliability is insufficient can be solved.

This invention claims protection for a CNN-LSTM algorithm neural network accelerator based on FPGA. The CNN hardware implementation includes a data input line buffer module, a convolution calculation module, a ReLU activation function module, an intermediate result buffer module, and a pooling calculation module. The LSTM hardware implementation includes an LSTM control module, a gate function calculation module, and a sigmoid activation function linear approximation module. The FC hardware implementation includes an FC control module, a fully connected layer calculation module, a ReLU activation function module, and a data output buffer. The purpose of this invention is to design a high-performance, low-power, and highly flexible CNN-LSTM neural network accelerator tailored to specific application scenarios. The innovation lies in the fact that, compared to traditional neural network accelerators, this invention uses a parallel pipelined design method to implement a CNN-LSTM algorithm neural network accelerator, which significantly improves the low power consumption and data throughput of the neural network accelerator. Furthermore, the parallel processing capabilities of the FPGA enable the algorithm to run at a faster speed.

A system and method for designing a general-purpose static multi-issue CPU using static pipelining of automatically parallelized code is proposed. A multicore and / or multiprocessor integrated circuit has multiple processing units and / or processing pipelines that simultaneously process instructions for data by executing parallelized processing machine code. The execution of parallelized processing code by a multicore and / or multiprocessor integrated circuit that performs parallel processing involves the occurrence of latency, which is given by the idle time of the processing unit between the time the processing unit processes a particular block of instructions in the processing code for data and sends the data back, and the time the processing unit receives the data necessary to execute a successive block of instructions in the processing code. The parallel pipeline includes means for (i) forwarding by providing data forwarding from the MEM stage as an EX / MEM register to the EX stage as an ID / EX stage register, (ii) exchange by providing result exchange between pipelines by making the Ex-MEM stage register results accessible to the EX stage of the parallel pipeline, and (iii) means for branch pipeline flushing with control hazards by flushing only pipelines that depend on one pipeline that calculates conditions based on branch addresses.

The embodiment of the invention discloses an FPGA (Field Programmable Gate Array) model reasoning hardware adaptation method based on a Qwen-2 low-bit quantization technology. According to the embodiment of the invention, quantitative perception training is carried out on a Transform layer of a Qwen-2 model so as to keep reasoning precision; converting the quantized weight and activation value into a fixed-point format supported by the FPGA and generating a quantization parameter table; according to DSP and BRAM resource distribution of the FPGA, mapping low-bit matrix operation to a DSP unit, storing quantization parameters in the BRAM, and planning a task scheduling sequence; a parallel pipeline is designed for an attention layer and a feed-forward layer, low-bit storage optimization is carried out on key value cache, and dynamic quantization adjustment is carried out on an activation value; and finally, deploying to an FPGA for testing, and performing closed-loop optimization on a hardware mapping strategy or quantization granularity based on delay and resource data. According to the method, the model precision is effectively maintained while the storage and calculation overhead is remarkably reduced.

The invention discloses a parallel pipeline flow distribution method and device, and relates to the technical field of parallel pipeline flow distribution. The parallel pipeline flow distribution method comprises the steps that the flow of a first branch is adjusted to reach the target flow a1, the first valve opening value D1 of the first branch is locked, then the flow of a second branch is adjusted to reach the target flow a2, the second valve opening value D2 of the second branch is locked, and the rest can be done in the same way, and finally, the flow of the nth branch is adjusted to reach the target flow an, the nth valve opening value Dn of the nth branch is locked, and the total valve opening value D0 is locked, so that flow adjustment of all the branches is completed. The parallel pipeline flow distribution device is suitable for the parallel pipeline flow distribution method. The invention aims to provide the parallel pipeline flow distribution method and the device thereof so as to solve the technical problem that in the prior art, parallel pipeline flow distribution adjustment is complex to a certain extent.

A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.

The invention relates to a multi-protocol high-speed data conversion system based on an FPGA (Field Programmable Gate Array), belongs to the field of communication and data processing, and aims to solve the technical problems of congestion and high delay caused by protocol incompatibility and data traffic burst in high-speed multi-protocol data conversion. According to the technical scheme, a data input sub-channel buffer module realizes physical isolation and flow control, an intelligent arbitration and scheduling module performs differentiated scheduling and starvation compensation based on a priority weight mechanism, a protocol conversion module analyzes and converts a protocol format, and a parallel assembly line collaborative architecture improves efficiency through assembly line processing; the technical effects are that high-efficiency and reliable conversion and transmission of high-speed data are realized, and system compatibility and expandability are enhanced.

The present application relates to a kind of parallel four neighborhood real-time multi-spot center detection method based on FPGA, belong to optical measurement and laser radar technical field, solve the problem of high hardware resource occupation of existing FPGA multi-spot detection algorithm, calculation precision loss and insufficient real-time nature.Techinical scheme includes: through two-stage median filter, adaptive binarization and morphological processing module to complete image preprocessing;Label assignment, equivalence table merging and centroid calculation are realized using four neighborhood center detection module, and label analysis and coordinate accumulation are synchronously completed based on three-stage pipeline architecture.The present application realizes low resource occupation multi-spot sub-pixel level positioning by hardware-level parallel pipeline processing, improves detection real-time nature and environmental adaptability, and provides accurate and stable spot center detection scheme for high dynamic scene.

The utility model discloses a municipal pipeline reinforcing device, and relates to the field of municipal pipe networks. The device comprises a protecting and reinforcing culvert pipe, a triple bearing and reinforcing assembly is arranged in the protecting and reinforcing culvert pipe and comprises a bearing and fixing block used for being fixedly connected into the protecting and reinforcing culvert pipe and three sets of pipeline protecting ferrules fixedly connected into the bearing and fixing block, and the bearing and fixing block is used for being fixedly connected into the protecting and reinforcing culvert pipe. The pipeline protection sleeve ring is used for protecting a pipeline, a friction fixing soft cushion is arranged in the pipeline protection sleeve ring, the friction fixing soft cushion abuts against the pipeline, and the friction fixing soft cushion is used for pressing the pipeline and preventing the pipeline from vibrating in the pipeline protection sleeve ring to cause local damage. According to the device, the effect of external force on the triple parallel type pipeline is reduced, the triple parallel type pipeline can be supported in the culvert pipe and can also be fixed to a cement base, and the triple parallel type pipeline can be supported in different environments.

The invention discloses a method, device and equipment for concurrently improving replication efficiency based on RANGE and a medium, and relates to the technical field of solid state disks, the method comprises the steps that a replication command from a host is received, and the replication command comprises multiple pieces of source range description information and a target initial logic block address; calculating a corresponding target logic block address range for each piece of source range description information based on the target initial logic block address; distributing copy tasks corresponding to the plurality of pieces of source range description information of the target logic block address range obtained through calculation to a plurality of processing cores of the solid state disk for concurrent execution; and after all the copy tasks are executed, returning an execution result to the host. According to the method, serial processing is converted into parallel assembly lines, so that the execution efficiency of the copy command and the system throughput are remarkably improved, and the data consistency is ensured.

The application discloses a kind of multi-station product parallel test method and system based on multiple single-chip machine linkage, including the carrier plate loaded with multiple products to be tested is moved to initial test position, the linkage positioning of multiple stations is carried out, and the identity information of each product is identified in parallel by issuing synchronous trigger instruction to the code scanner of all stations by host computer, and test task is distributed to the single-chip machine of corresponding station based on the identification result;Each station's single-chip machine is made to execute parallel pipeline test according to the distributed task by communication bus, and the test progress and state information of each station are synchronized in real time during testing, forming a globally shared system state table;After each station completes testing, the test results of all stations are collected by host computer, and collaborative foolproofing judgment is carried out in combination with identity information to generate batch test report;Real-time synchronization, collaborative decision and fault linkage of multiple-station testing are realized, so as to greatly improve efficiency while ensuring test quality.

The invention discloses financial data FPGA processing equipment based on a space-time prediction algorithm. The financial data FPGA processing equipment comprises an FPGA chip, a level conversion interface and a liquid cooling heat dissipation system. A special logic circuit is configured in the FPGA, a core calculation module is mapped into a four-stage parallel pipeline structure, 32 DSP48E1 units are integrated, calculation is accelerated in parallel through hardware, future data processing delay is reduced to 0.8 ms from 12 ms, and power consumption is reduced by 40%. The device is suitable for financial scenes such as high-frequency transactions and the like with extremely high real-time requirements.

The application discloses a video stream compression and decompression method and system based on OpenMP thread nesting, adopts parallel pipeline to process video frame data, simplifies original JPEG coding, compresses RGB data into YCbCr data for transmission, adopts OpenMP thread nesting to process the compression and decompression of the video frame data in a multithreading mode under the condition that the outer thread processes the video frame data by using the parallel pipeline, effectively improves the support resolution and fluency of remote playing video, saves the engineering cost of client computing, and improves user experience.

The invention discloses a positioning method for embedding a special-shaped thin-wall cooling pipeline into a thin-wall radiator in the field of casting and pouring of castings, which comprises the following steps: preparing a single-hole fixing block and a double-hole fixing block, enabling the distance between two holes to be consistent with the distance between parallel pipelines, and enabling the hole shapes to be matched with the pipelines; arranging to a welding tool according to the pipeline form, enabling parallel pipelines to penetrate through double-hole fixing blocks, and enabling other pipelines to penetrate through single-hole fixing blocks; welding to form a special-shaped pipeline; the device is installed on a mold, and the fixing block is fixed to the mold. And pouring after mold closing and fixing. According to the method, full-length positioning is achieved by covering the pipeline through the fixing block, alloy liquid impact displacement is avoided, the method is suitable for a complex structure containing parallel pipelines, and relative displacement or deformation of the parallel pipelines can be prevented.

The invention provides a quantum computing task processing method and device, electronic equipment and a storage medium. The method comprises the steps that a quantum computing task to be processed is acquired; decomposing the quantum computing task into a plurality of sub-tasks, and configuring the number of redundant copies for each sub-task; a quantum processor is controlled to execute the multiple sub-tasks in sequence, and each sub-task is independently calculated for multiple times according to the number of corresponding redundant copies; when the quantum processor executes the current subtask, verifying a calculation result of a previous completed subtask through the coprocessor to obtain a verification result; and controlling a task execution process of the quantum processor according to the verification result. Therefore, a parallel pipeline mechanism of quantum computing and classical verification is established, and the quantum processor and the coprocessor can work cooperatively, so that the idle waiting time is shortened, and the computing efficiency is improved.

This invention relates to the field of image processing technology and discloses a method for detecting the offset of parallel pipelines under a train. The invention establishes a static reference information acquisition step, a dynamic information acquisition step, a trend judgment step, and a loosening warning step. Images are acquired using image processing methods during both stationary and moving train phases. The method then determines whether there is a high risk of pipeline loosening, facilitating early warning before loosening occurs and allowing maintenance personnel to intervene in advance, preventing pipeline damage caused by collisions. The trend judgment step consists of two parts: risk pre-screening and loosening trend score calculation. In the risk pre-screening step, a preliminary scoring threshold is calculated using partial data to determine if high-risk pipeline sections exist. If high-risk sections are found, a loosening trend score is calculated to quickly identify high-risk pipelines. The loosening trend score calculation step incorporates actual operating scenarios to improve the accuracy of risk assessment.

Methods, apparatuses, and systems related to an apparatus implementing a geardown mode in a parallel pipeline configuration. The apparatus can include mechanisms to manage signal timing across multiple data processing pipelines for different communication speeds. While operating in a geardown mode, the apparatus can capture a sync pulse in two or more data pipelines. The apparatus can identify the pipeline that first captured the sync pulse and suppress the operation of the other pipelines.

The invention relates to the technical field of computer science and artificial intelligence, and discloses a calculation acceleration method of matrix multiplication and an asynchronous processing method of a many-core processor, which can optimize a weight data storage structure and adapt to memory access characteristics of a chip architecture by performing off-line arrangement processing on an initial quantization weight matrix. And the memory access efficiency of subsequent data reading and operation is improved. Furthermore, the line-by-line inverse quantization operation is executed by utilizing a parallel lookup table mode, the low-precision quantization weight can be quickly recovered into high-precision data, and the processing speed can be improved by virtue of parallel calculation while the inverse quantization precision is ensured. Furthermore, a double-cache mode is utilized, asynchronous device parallel pipeline is designed, matrix multiplication is executed, a result is obtained, core calculation needed by MXFP4 model reasoning is completed, key output is provided for model reasoning, and calculation performance and precision are both considered.

The application relates to an acceleration method of an SM3 cryptographic hash algorithm and an instruction set processor, wherein the acceleration method is based on an SM3 extension instruction set, parallel pipeline and instruction level parallel technology are adopted to accelerate the execution of the SM3 cryptographic hash algorithm; the SM3 extension instruction set adopts a RISC architecture, and comprises an SM3 message word extension instruction and an SM3 working variable word iteration update instruction; the SM3 message word extension instruction adopts a multi-message word parallel extension algorithm to accelerate an SM3 message extension function; the SM3 working variable word iteration update instruction adopts a multi-round iteration fusion algorithm to accelerate an SM3 iteration compression function. The instruction set processor supports the SM3 message word extension instruction and the SM3 working variable word iteration update instruction to be executed in a pipeline mode, and the delay is 1 beat and 5 beats respectively. The application can significantly improve the speed of the processor in executing the SM3 cryptographic hash algorithm.

The application discloses a distributed storage test acceleration method and device, electronic equipment and a storage medium, relates to the technical field of distributed storage, and through operation semantics and dependency relationship identification of a test case of a to-be-tested distributed storage system and decomposition into independently executable test slices, a multilayer parallel pipeline including a test environment preparation layer, a test data management layer, a test operation execution layer and a test result verification layer is constructed based on the dependency relationship to realize parallel processing of the test slices, and system resources and test slice execution states are monitored in real time during execution and are dynamically scheduled and distributed according to the monitoring results and the dependency relationship, and meanwhile, parallel execution results are distributed collected, consistency verified and test reports are generated, so that the problems of long test period, serious resource waste and insufficient test reliability caused by linear execution of test cases, insufficient resource utilization and lack of systematicness of result verification in the prior art can be solved.

The invention relates to the technical field of compiling, in particular to a pattern file compiling method, a compiler and electronic equipment, and the compiling method comprises the following steps: decomposing a huge whole pattern file into a plurality of processing blocks according to a preset rule, and converting a single and huge compiling task into a large number of sub-tasks which can be independently processed. On the basis, the processing blocks are compiled in parallel by utilizing a multi-thread technology, so that a plurality of CPU cores can work simultaneously, and the original lengthy sequential execution time is greatly compressed. Finally, the multi-thread technology is adopted again in the link stage, all the intermediate files are organized into the final executable file in parallel, and the situation that the final synthesis stage becomes a new performance bottleneck is avoided. The whole-course parallel assembly line from compiling to linking is particularly suitable for processing large-scale Pattern files of ten millions of rows, the compiling time can be remarkably shortened, and the compiling efficiency is improved.

The present application relates to the technical field of automatic production deployment, and particularly relates to a method and device for automatic deployment, computer equipment and a storage medium. The method comprises the following steps: listening to a physical mounting event of a USB device; if the USB device is found to be connected, verifying the legality of the USB device; if the USB device is verified, entering an environment locking mode; constructing a parallel pipeline system comprising a reading thread, a checking thread and a writing thread, and performing stream processing on data of the USB device; listening to a physical removal event of the USB device; and if the USB device is found to be removed, automatically triggering a system restart. An operator only needs to perform two actions of 'inserting' and'removing', and the time consumption of a single machine is about 4 seconds, zero touch and zero false touch. After testing the same batch of aged USB disks, the stream checking mechanism successfully intercepts all read errors caused by bad blocks, and the firmware integrity of the deployed device reaches 100%, solving the problem of low production efficiency caused by reliance on manual interaction.