71 results about "Parallel pipeline" patented technology

A test system has ovens configured to hold devices under test (DUTs), DUT switches, each connected to the DUTs in an oven, splitters, each splitter connected to a DUT switch, an instrument switch connected to one output of each splitter, the other output of each splitter connected to a test instrument, and one or more processors to control the instrument switch to select one of the DUT switches connected to an oven, control the selected DUT switch to connect each DUT in the oven to a channel of the test and measurement instrument, use machine learning to tune the DUT to a set of parameters until the DUT passes or fails, repeat the connecting, tuning, and testing of each DUT until all DUTs in an oven have been tested, and repeat the selection and control of the DUT switches until each DUT in each oven has been tuned and tested.

The invention relates to a fractional order PID (Proportion Integration Differentiation) control method and system based on an FPGA (Field Programmable Gate Array). The method comprises the following steps of: 1, setting fractional order PID related parameters according to the requirements of a controlled object; 2, calculating a fractional order calculus weight coefficient according to the fractional order PID related parameters, and storing the fractional order calculus weight coefficient in the FPGA; 3, collecting a state feedback signal of the controlled object, and calculating an integral term operator and a differential term operator; step 4, calculating control output and performing amplitude limiting processing, and updating the state of the controlled object by using the control output after the amplitude limiting processing; and 5, repeating the steps 1-4 to realize fractional order PID closed-loop control. By optimizing a discrete convolution algorithm, adopting a parallel pipeline architecture and configurable parameter design and combining fixed-point number operation and security boundary constraint, the numerical stability and hardware security of the system under high-speed operation are ensured, the calculation speed is remarkably increased while the operation precision is ensured, and the method is suitable for large-scale popularization and application. And the method is suitable for control occasions with extremely high real-time requirements.

A system and method for universal static multi-transmit CPU design with a static pipeline for automatically parallelizing code is presented. A multi-core and / or multi-processor integrated circuit (2) has a plurality of processing units (21) and / or processing pipelines (53) that simultaneously process instructions for data by executing parallel processing machine code (32). The execution of the parallelized processing code (32) by the parallel processing multi-core and / or multi-processor integrated circuit (2) comprises the occurrence of a delay time (26), wherein the delay time is given by an idle time between the processing unit (21) returning the data after processing a specific instruction block of the processing code (32) for the data and receiving the data required by the processing unit (21) to execute a consecutive instruction block of the processing code (32). The parallel pipeline (53) comprises means for: (i) forwarding by providing a data forwarding from a MEM stage as an EX / MEM register to an EX stage as an ID / EX-stage register; (ii) exchanging by making the results of the Ex-ME-phase registers accessible by the Ex phase of a parallel pipeline (53) to provide a result exchange between the pipelines; and (iii) implementing branch pipeline refresh by providing control conflicts by refreshing only those pipelines (53) dependent on one pipeline (53) based on branch address computation conditions.

The invention relates to the technical field of production line scheduling, in particular to a production line resource scheduling control method and system, and the method comprises the steps: connecting end equipment of each production line through a parallel pipeline and a controllable valve to form a shared equipment resource pool, and obtaining the operation data information of each production line when a production request is received, the operation data information comprises the material flow and the equipment load rate of the end equipment, performing calculation based on the material flow and a preset target yield to obtain a demand calculation result, and dynamically scheduling the end equipment in the shared equipment resource pool based on the equipment load rate and the demand calculation result. According to the technical scheme of the invention, by constructing the'shared equipment resource pool ', the barrier that the resources of the traditional production lines are isolated is broken, and the elastic allocation and sharing of the resources across the production lines are realized, so that the resource utilization rate of the end equipment is improved, and the comprehensive output efficiency of the whole production system is improved.

The present invention discloses an error correction method and system for FPGA, which relates to the technical field of data encoding and decoding, and includes: generating Galois field elements based on the received symbol vector and the primitive polynomial, and calculating the syndrome polynomial through 8-symbol parallel processing; calculating the coefficients of the error location polynomial through the BM iterative algorithm based on the syndrome polynomial; calculating the error location by parallel substituting 10 Galois field elements through the Chien search method based on the error location polynomial; establishing the evaluation polynomial and the error pattern calculation formula, and performing polynomial division calculation through the derivative of the error location polynomial to obtain the error pattern; performing error code judgment based on the error location and the error pattern, and correcting the error symbol through the XOR operation in the Galois field to obtain the updated symbol vector. The present application adopts a parallel pipeline design structure, which enables the FPGA to automatically and real-time correct the received error module data without retransmission, effectively improving the real-time performance and reliability of error correction.

The invention discloses a dynamic instruction fetch and instruction coverage method and a processor based on a double-track assembly line, and the dynamic instruction fetch method comprises the steps: when the current instruction fetch is a branch instruction, two instructions are fetched from a current instruction PC value plus 4 and a branch target address at the same time in a next clock period; and when the instruction is a non-branch instruction, taking one instruction in the next clock period. According to the instruction coverage method, primary and secondary parallel assembly lines are set, the primary assembly line processes an instruction with a previous instruction PC value plus 4, and the secondary assembly line processes a branch target address instruction; when branch jumping and target address matching are judged in the execution stage, instructions in all stages of the secondary assembly line cover instructions in corresponding stages of the main assembly line. The method can solve the problems of high delay, large misprediction penalty and low power consumption efficiency of branch prediction, and improves the performance of a processor.

The invention belongs to the field of data processing, and provides a contract number generation method and device with multiple parallel pipeline serial numbers, a medium and equipment. The method comprises the steps of obtaining a to-be-processed business contract form, analyzing a form field, and calling a contract coding scheme pre-configured and associated with the form field; according to the contract coding scheme, acquiring incremental dimension attributes, corresponding attribute values and incremental dimension attribute grouping information in the form fields; wherein the same incremental dimension attribute is divided into the same group in advance, and each group corresponds to one pipeline serial number; traversing information of all groups, and determining an incremental dimension attribute value and a maximum pipeline serial number of each group; and combining and splicing the incremental dimension attribute value and the maximum pipeline serial number of each group according to a coding preview style of the contract coding scheme to form a final unique contract number containing a plurality of pipeline serial numbers. The method is suitable for the situation that a single serial number needs to contain a plurality of pipeline serial numbers.

The invention discloses a hardware-based SOFTMAX function calculation method and device. The hardware-based SOFTMAX function calculation method comprises the following steps: receiving a multi-dimensional input vector corresponding to an SOFTMAX function through an input port; uniformly dividing the multi-dimensional input vector into a plurality of data segments according to an element sequence through a channel distributor, and distributing the data segments to corresponding operation channels; performing an exponential operation on the data segment using the operation channel to generate a local exponential vector; aggregating the local exponent vectors with an accumulator to generate a global exponent sum; distributing the global index sum to each operation channel, so that the operation channels generate output sub-vectors according to the local index vectors and the global index sum; and splicing the output sub-vectors according to the element sequence through a recombination unit to generate an SOFTMAX output vector. The efficient SOFTMAX function hardware acceleration calculation under the multi-channel parallel pipeline processing architecture is realized, and the calculation performance and throughput are improved by several times compared with the traditional serial software implementation.

The invention discloses a storage and calculation integrated architecture-based convolutional code parallel pipeline decoding acceleration system and method, and the system comprises a global data scheduling module which is used for slicing convolutional code data from magnetic tape storage equipment according to a set rule and carrying out the scheduling through a multi-stage cache mechanism; the storage and calculation integrated unit array is used for storing data tiles and intermediate results output by the global data scheduling module and executing convolution operation, path metric calculation and survival path selection through a reconfigurable calculation unit; the parallel pipeline controller is used for dynamically distributing decoding tasks and controlling the pipeline rhythm of the storage and calculation integrated unit array; the self-adaptive resource configuration module is used for monitoring system load in real time and dynamically adjusting a data distribution strategy and computing resource scheduling; the verification and error correction unit is used for performing verification and error correction on the decoding result output by the storage and calculation integrated unit array and then outputting the decoding result; according to the decoding acceleration system and method, high-efficiency and low-delay convolutional code decoding is realized.

The present invention discloses a control system and method applicable to a parallel pipeline, relating to the technical field of pipeline transportation, including: a main pipeline, one end of the main pipeline is connected to a fluid source device, and the other end branches out multiple branch pipelines; a plurality of fluid control devices, each fluid control device is arranged on a corresponding branch pipeline, the fluid control device includes a first on-off part, a temporary storage cavity and a second on-off part that are connected in sequence, the first on-off part is used to control the on-off of the fluid upstream of the branch pipeline, an adjustment part is arranged in the temporary storage cavity, the adjustment part is used to adjust the internal volume of the temporary storage cavity, and the second on-off part is used to control the on-off of the fluid in the temporary storage cavity; a controller, which is used to control the actions of the first on-off part, the adjustment part and the second on-off part. The present invention can reduce the sudden change of fluid flow rate generated by the traditional semiconductor glue pump when used in a parallel pipeline, improve the discharge volume accuracy, enable the discharge volume accuracy of each pipeline in the parallel pipeline to meet the actual requirements, and reduce the cost of the equipment.

The application discloses a data synchronization method and system with full-link back pressure characteristics, comprising: configuring metadata of a synchronization task; starting incremental synchronization of a binlog log, and selectively performing full synchronization; routing generated add, delete, modify and query events to a distributed parallel Stream pipeline; and distributing the events to an Actor entity in an Actor model shard cluster according to dimension fields configured for each table in an asynchronous request response mode; performing event persistence and state updating, and complex conversion logic based on the current state, and returning the result to the Stream pipeline; performing message batching, sorting and deduplication processing on Response events by the Stream pipeline; writing the result to a Sink data source, and performing an asynchronous ACK mechanism to ensure reliable synchronization. The application can quickly realize complex model synchronization conversion between heterogeneous data sources through highly configurable synchronization tasks, and has the characteristics of short link, few components and efficient synchronization.

The invention discloses a quantum measurement and control instruction assembly line parallel processing system, which adopts a double-thread framework, connects a producer thread and a consumer thread through a limited-capacity buffer queue, and can ensure the execution sequence of quantum measurement and control instructions and improve the execution efficiency of the quantum measurement and control instructions at the same time. The problems that in an existing measurement and control equipment system, serial processing efficiency is low, and the resource utilization rate is insufficient are solved, namely the technical defects that when an upper computer generates an instruction, external equipment is idle, and when the external equipment executes the instruction, the upper computer is idle are overcome, and a parallel assembly line strategy of upper computer instruction generation and external equipment instruction execution is achieved. The processing efficiency and the resource utilization rate are remarkably improved, and the method has high universality, expandability and a perfect exception processing mechanism.

The embodiment of the invention discloses a method for evaluating the training income of a large model, a device for evaluating the training income of the large model, electronic equipment and a computer readable storage medium. The large model comprises a plurality of sub-modules. The method comprises the following steps: acquiring the actual operation execution duration of each sub-module in a plurality of sub-modules of the large model in a graphic calculation unit; obtaining a parallel pipeline strategy of the large model, wherein the parallel pipeline strategy indicates a strategy adopted when a plurality of devices train the large model in a distributed manner; based on the parallel pipeline strategy of the large model and the running time of each sub-module in the large model, executing a plurality of waiting operations in a central processing unit to simulate actual operations executed by each sub-module in a graphic computing unit; and determining a training revenue of the large model based on execution results of the plurality of waiting operations executed in the central processing unit.

The application discloses a convolution code parallel pipeline decoding acceleration system and method based on a memory-compute integrated architecture, comprising: a global data scheduling module, which is used for slicing convolution code data from a magnetic tape storage device according to a set rule and scheduling the data through a multi-level cache mechanism; a memory-compute integrated unit array, which is used for storing data tiles and intermediate results output from the global data scheduling module and performing convolution operation, path metric calculation and surviving path selection through a reconfigurable computing unit; a parallel pipeline controller, which is used for dynamically allocating decoding tasks and controlling the pipeline beat of the memory-compute integrated unit array; an adaptive resource configuration module, which is used for monitoring the system load in real time and dynamically adjusting data distribution strategies and computing resource scheduling; and a check and error correction unit, which is used for checking and correcting the decoding results output from the memory-compute integrated unit array and then outputting the results; the decoding acceleration system and method realize efficient and low-delay convolution code decoding.

The invention discloses a distributed storage test acceleration method and device, electronic equipment and a storage medium, and relates to the technical field of distributed storage. Operation semantics and dependency relationship recognition is performed on a test case of a to-be-tested distributed storage system, and the test case is decomposed into test slices capable of being independently executed; and constructing a multi-layer parallel pipeline comprising a test environment preparation layer, a test data management layer, a test operation execution layer and a test result verification layer based on the dependency relationship to realize parallel processing of test slices. In the execution process, system resources and test slice execution states are monitored in real time, dynamic scheduling distribution is carried out according to monitoring results and dependency relationships, distributed collection and consistency verification are carried out on parallel execution results, and a test report is generated. The problems that in the prior art, due to linear execution of test cases, insufficient resource utilization and lack of systematicness of result verification, the test period is long, resource waste is serious, and test reliability is insufficient can be solved.

This invention claims protection for a CNN-LSTM algorithm neural network accelerator based on FPGA. The CNN hardware implementation includes a data input line buffer module, a convolution calculation module, a ReLU activation function module, an intermediate result buffer module, and a pooling calculation module. The LSTM hardware implementation includes an LSTM control module, a gate function calculation module, and a sigmoid activation function linear approximation module. The FC hardware implementation includes an FC control module, a fully connected layer calculation module, a ReLU activation function module, and a data output buffer. The purpose of this invention is to design a high-performance, low-power, and highly flexible CNN-LSTM neural network accelerator tailored to specific application scenarios. The innovation lies in the fact that, compared to traditional neural network accelerators, this invention uses a parallel pipelined design method to implement a CNN-LSTM algorithm neural network accelerator, which significantly improves the low power consumption and data throughput of the neural network accelerator. Furthermore, the parallel processing capabilities of the FPGA enable the algorithm to run at a faster speed.

A system and method for designing a general-purpose static multi-issue CPU using static pipelining of automatically parallelized code is proposed. A multicore and / or multiprocessor integrated circuit has multiple processing units and / or processing pipelines that simultaneously process instructions for data by executing parallelized processing machine code. The execution of parallelized processing code by a multicore and / or multiprocessor integrated circuit that performs parallel processing involves the occurrence of latency, which is given by the idle time of the processing unit between the time the processing unit processes a particular block of instructions in the processing code for data and sends the data back, and the time the processing unit receives the data necessary to execute a successive block of instructions in the processing code. The parallel pipeline includes means for (i) forwarding by providing data forwarding from the MEM stage as an EX / MEM register to the EX stage as an ID / EX stage register, (ii) exchange by providing result exchange between pipelines by making the Ex-MEM stage register results accessible to the EX stage of the parallel pipeline, and (iii) means for branch pipeline flushing with control hazards by flushing only pipelines that depend on one pipeline that calculates conditions based on branch addresses.

The embodiment of the invention discloses an FPGA (Field Programmable Gate Array) model reasoning hardware adaptation method based on a Qwen-2 low-bit quantization technology. According to the embodiment of the invention, quantitative perception training is carried out on a Transform layer of a Qwen-2 model so as to keep reasoning precision; converting the quantized weight and activation value into a fixed-point format supported by the FPGA and generating a quantization parameter table; according to DSP and BRAM resource distribution of the FPGA, mapping low-bit matrix operation to a DSP unit, storing quantization parameters in the BRAM, and planning a task scheduling sequence; a parallel pipeline is designed for an attention layer and a feed-forward layer, low-bit storage optimization is carried out on key value cache, and dynamic quantization adjustment is carried out on an activation value; and finally, deploying to an FPGA for testing, and performing closed-loop optimization on a hardware mapping strategy or quantization granularity based on delay and resource data. According to the method, the model precision is effectively maintained while the storage and calculation overhead is remarkably reduced.

The invention discloses a parallel pipeline flow distribution method and device, and relates to the technical field of parallel pipeline flow distribution. The parallel pipeline flow distribution method comprises the steps that the flow of a first branch is adjusted to reach the target flow a1, the first valve opening value D1 of the first branch is locked, then the flow of a second branch is adjusted to reach the target flow a2, the second valve opening value D2 of the second branch is locked, and the rest can be done in the same way, and finally, the flow of the nth branch is adjusted to reach the target flow an, the nth valve opening value Dn of the nth branch is locked, and the total valve opening value D0 is locked, so that flow adjustment of all the branches is completed. The parallel pipeline flow distribution device is suitable for the parallel pipeline flow distribution method. The invention aims to provide the parallel pipeline flow distribution method and the device thereof so as to solve the technical problem that in the prior art, parallel pipeline flow distribution adjustment is complex to a certain extent.

A data parallel pipeline may specify multiple parallel data objects that contain multiple elements and multiple parallel operations that operate on the parallel data objects. Based on the data parallel pipeline, a dataflow graph of deferred parallel data objects and deferred parallel operations corresponding to the data parallel pipeline may be generated and one or more graph transformations may be applied to the dataflow graph to generate a revised dataflow graph that includes one or more of the deferred parallel data objects and deferred, combined parallel data operations. The deferred, combined parallel operations may be executed to produce materialized parallel data objects corresponding to the deferred parallel data objects.

The invention relates to a multi-protocol high-speed data conversion system based on an FPGA (Field Programmable Gate Array), belongs to the field of communication and data processing, and aims to solve the technical problems of congestion and high delay caused by protocol incompatibility and data traffic burst in high-speed multi-protocol data conversion. According to the technical scheme, a data input sub-channel buffer module realizes physical isolation and flow control, an intelligent arbitration and scheduling module performs differentiated scheduling and starvation compensation based on a priority weight mechanism, a protocol conversion module analyzes and converts a protocol format, and a parallel assembly line collaborative architecture improves efficiency through assembly line processing; the technical effects are that high-efficiency and reliable conversion and transmission of high-speed data are realized, and system compatibility and expandability are enhanced.

The invention provides an LDPC (Low Density Parity Check) decoding method and device, equipment and a storage medium. The method comprises the following steps: dividing a check matrix into multiple layers according to rows; combining the plurality of layers to obtain a plurality of layer groups; wherein each layer group is numbered in sequence; and based on each layer group, decoding according to an inverted sequence. According to the method provided by the invention, after the rows are layered, the layers are grouped, and decoding is carried out according to an inverted sequence based on each layer group, so that processing time delay caused by layer jump can be avoided, and implementation of parallel pipeline is facilitated.

The present invention provides a unidirectional multi-branch parallel pipeline structure and its application. The structure includes a first-stage pipe and a second-stage pipe connected in sequence; the second-stage pipe includes at least six independently arranged first branch pipes, second branch pipes, third branch pipes, fourth branch pipes, fifth branch pipes and sixth branch pipes with the same pipe diameter; the first branch pipe, the second branch pipe, the third branch pipe, the fourth branch pipe, the fifth branch pipe and the sixth branch pipe are respectively communicated with the first-stage pipe, and the height of the inlet of the first branch pipe > the height of the inlet of the second branch pipe > the height of the inlet of the third branch pipe > the height of the inlet of the fourth branch pipe > the height of the inlet of the fifth branch pipe > the height of the inlet of the sixth branch pipe; a first fillet is arranged on the outer side of the connection between the first-stage pipe and the first branch pipe, and a second fillet is arranged on the outer side of the connection between the first-stage pipe and the sixth branch pipe. Through the present application, the flow distribution of the fuel cell system is made uniform and the performance is stable.

The present application relates to a kind of parallel four neighborhood real-time multi-spot center detection method based on FPGA, belong to optical measurement and laser radar technical field, solve the problem of high hardware resource occupation of existing FPGA multi-spot detection algorithm, calculation precision loss and insufficient real-time nature.Techinical scheme includes: through two-stage median filter, adaptive binarization and morphological processing module to complete image preprocessing;Label assignment, equivalence table merging and centroid calculation are realized using four neighborhood center detection module, and label analysis and coordinate accumulation are synchronously completed based on three-stage pipeline architecture.The present application realizes low resource occupation multi-spot sub-pixel level positioning by hardware-level parallel pipeline processing, improves detection real-time nature and environmental adaptability, and provides accurate and stable spot center detection scheme for high dynamic scene.

The utility model relates to a flexible parallel pipeline Y-shaped flow dividing device which comprises a branch pipe A and a branch pipe B. One end of the branch pipe A and one end of the branch pipe B are connected with a downstream branch pipe through a socket joint or a sleeve type flexible joint, the other end of the branch pipe A and one end of the branch pipe B are connected with a T-shaped flow dividing bin, and the joint of the T-shaped flow dividing bin and the branch pipe A and the joint of the T-shaped flow dividing bin and the branch pipe B are wrapped with fixing piers in a semi-surrounding mode. And a stress pier is arranged above the fixed pier and surrounds and wraps the branch pipe A and the branch pipe B, and the structure of the stress pier is in a diffusion type towards the downstream. According to the utility model, one-to-two shunting can be realized for projects with parallel layout requirements. The device not only ensures the distribution and scheduling of the water quantity of the water delivery pipeline, but also meets the engineering specificity requirements.

The utility model discloses a municipal pipeline reinforcing device, and relates to the field of municipal pipe networks. The device comprises a protecting and reinforcing culvert pipe, a triple bearing and reinforcing assembly is arranged in the protecting and reinforcing culvert pipe and comprises a bearing and fixing block used for being fixedly connected into the protecting and reinforcing culvert pipe and three sets of pipeline protecting ferrules fixedly connected into the bearing and fixing block, and the bearing and fixing block is used for being fixedly connected into the protecting and reinforcing culvert pipe. The pipeline protection sleeve ring is used for protecting a pipeline, a friction fixing soft cushion is arranged in the pipeline protection sleeve ring, the friction fixing soft cushion abuts against the pipeline, and the friction fixing soft cushion is used for pressing the pipeline and preventing the pipeline from vibrating in the pipeline protection sleeve ring to cause local damage. According to the device, the effect of external force on the triple parallel type pipeline is reduced, the triple parallel type pipeline can be supported in the culvert pipe and can also be fixed to a cement base, and the triple parallel type pipeline can be supported in different environments.

The invention discloses a method, device and equipment for concurrently improving replication efficiency based on RANGE and a medium, and relates to the technical field of solid state disks, the method comprises the steps that a replication command from a host is received, and the replication command comprises multiple pieces of source range description information and a target initial logic block address; calculating a corresponding target logic block address range for each piece of source range description information based on the target initial logic block address; distributing copy tasks corresponding to the plurality of pieces of source range description information of the target logic block address range obtained through calculation to a plurality of processing cores of the solid state disk for concurrent execution; and after all the copy tasks are executed, returning an execution result to the host. According to the method, serial processing is converted into parallel assembly lines, so that the execution efficiency of the copy command and the system throughput are remarkably improved, and the data consistency is ensured.

The application discloses a kind of multi-station product parallel test method and system based on multiple single-chip machine linkage, including the carrier plate loaded with multiple products to be tested is moved to initial test position, the linkage positioning of multiple stations is carried out, and the identity information of each product is identified in parallel by issuing synchronous trigger instruction to the code scanner of all stations by host computer, and test task is distributed to the single-chip machine of corresponding station based on the identification result;Each station's single-chip machine is made to execute parallel pipeline test according to the distributed task by communication bus, and the test progress and state information of each station are synchronized in real time during testing, forming a globally shared system state table;After each station completes testing, the test results of all stations are collected by host computer, and collaborative foolproofing judgment is carried out in combination with identity information to generate batch test report;Real-time synchronization, collaborative decision and fault linkage of multiple-station testing are realized, so as to greatly improve efficiency while ensuring test quality.

The invention discloses financial data FPGA processing equipment based on a space-time prediction algorithm. The financial data FPGA processing equipment comprises an FPGA chip, a level conversion interface and a liquid cooling heat dissipation system. A special logic circuit is configured in the FPGA, a core calculation module is mapped into a four-stage parallel pipeline structure, 32 DSP48E1 units are integrated, calculation is accelerated in parallel through hardware, future data processing delay is reduced to 0.8 ms from 12 ms, and power consumption is reduced by 40%. The device is suitable for financial scenes such as high-frequency transactions and the like with extremely high real-time requirements.

This invention discloses a batch design method for anchor blocks in multi-row parallel pipelines. When there are many anchor blocks in multi-row parallel pipelines, the anchor block design requires individual operation using a single anchor block design program, which is inefficient. This invention selects a dedicated EXCEL file for pre-processing basic anchor block data based on the actual number of water pipelines; it uses EXCEL macro commands to process the data in the dedicated EXCEL file to generate a basic anchor block data file; based on the basic anchor block data file, it uses AutoCAD VBA technology to sequentially complete the batch automated design of anchor block shapes, anchor block plan views, and section views according to the anchor block numbering order, and generates an anchor block shape parameter file; it automatically annotates the main dimensions; finally, it uses EXCEL macro commands to process the anchor block shape parameter file to generate the final anchor block shape parameter table. This method is convenient to operate, provides intuitive results, and facilitates subsequent construction drawing generation, further improving the efficiency of anchor block design.