Hierarchical parallel pipelined operation of analog and digital circuits

Abstract

A hierarchical parallel pipelined circuit includes a first stage with a plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A second stage includes a second plurality of sampling circuits and a plurality of corresponding analog or digital circuits that receive an output from the plurality of sampling circuits. A multi-frequency, multi-phase clock clocks the first and second stages, the multi-frequency, multi-phase clock providing a first clock having a first frequency having either a single or plurality of phases, and a second clock having a second frequency having a plurality of phases. A first phase of a plurality of phases is phase locked to the first phase of the first clock. The clock frequency multiplied by the number of parallel devices in each stage is the throughput of the circuit and is kept constant across the stages.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention is related to high-throughput discrete-time systems with parallel pipelined architectures, and more particularly, to high-speed analog front-end circuits, such as time-interleaved analog-to-digital converters and to programmable gain amplifiers that precede the analog-to-digital converters. [0003] 2. Related Art [0004] Many modern data communications systems use parallel pipelined architectures in order to increase the data throughput. In essence, this approach utilizes a number of identical pipelined sub-circuits arranged in parallel. Another term for this architecture is “time interleaving.”[0005]FIG. 1A illustrates a conventional time interleaved analog-to-digital converter (ADC). As shown in FIG. 1A, an analog voltage Va is sampled by track-and-hold amplifiers 102A-102P. The track-and-hold amplifiers 102A-102P are clocked by clocks fadcA-fadcP, as shown in the figure. The outputs of the tra...

AI Technical Summary

Problems solved by technology

The problem with this approach is that the slow running block in the backend limits the system clock frequency.

However, the front-end bandwidth can not be scaled-down to match the slow clock, because the front-end has to track the fast varying signal, and / or the matching or noise (kT / C) requirements may prevent the scaling.

The front-end is usually the bottleneck in mismatch and noise because of the signal amplification in the front-end stage.

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