31 results about "Rapid single flux quantum" patented technology

A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data input. A serial address and data enter the address input and the data input in parallel. A shift sequence is transmitted on the single shift input. The data flows before the shift sequence on the shift input is complete. The data is shifted through the crossbar switch using a clock that is generated on-chip using a clock recovery circuit. The decoder converts a binary address input into a serial address and includes an N-bit counter with a plurality of toggle flip-flops. The crossbar switch is implemented using superconductor digital electronics such as rapid single flux quantum (RSFQ) logic.

A magnetic resonance system, comprising at least one SQUID, configured to receive a radio frequency electromagnetic signal, in a circuit configured to produce a pulsatile output having a minimum pulse frequency of at least 1 GHz which is analyzed in a processor with respect to a timebase, to generate a digital signal representing magnetic resonance information. The processor may comprise at least one rapid single flux quantum circuit. The magnetic resonance information may be image information. A plurality of SQUIDs may be provided, fed by a plurality of antennas in a spatial array, to provide parallel data acquisition. A broadband excitation may be provided to address a range of voxels per excitation cycle. The processor may digitally compensate for magnetic field inhomogeneities.

A method and apparatus for using a multi-user detector for reducing multiple access interference (MAI) in a direct sequence CDMA wireless system such as W-CDMA. A superconducting rapid single flux quantum (RSFQ) RF digital receiver operating in combination with an RSFQ successive interference canceller (SIC) is located in the base stations of the wireless system. In the present invention, the RSFQ SIC is a vector machine capable of processing the cross-correlation matrices using an iterative method to decorrelate the user binary code sequences from the input signal in which the interference components are removed. According, the reduction in interference results in a significant increase in system capacity while improving cellular coverage area.

A Rapid Single-Flux-Quantum ("RSFQ") encoder output interface device is provided. The RSFQ output interface device includes a variable phase multi-junction voltage controlled oscillator (VCO) that provides multiple clock signals having similar frequencies based on a DC bias current setting. The multiple clock signals are phase shifted from one other based on a flux bias current setting. The clock signals are then mixed together according to logic states of a data stream to provide an encoded output data stream. The encoded output data stream can be in a phase shifted keying (PSK) format. The PSK format can be provided in binary, quadrature or other PSK formats. The Single-Flux-Quantum (SFQ) voltage pulses of the encoded output data stream are converted to a voltage level appropriate for transmitting over a wire.

Supercooled electronics often use Rapid Single Flux Quantum (RSFQ) digital circuits. The output voltages from RSFQ devices are too low to be directly interfaced with semiconductor electronics, even if the semiconductor electronics are cooled. Techniques for directly interfacing RSFQ digital circuits with semiconductor electronics are disclosed using a novel inverting transimpedance digital amplifier in conjunction with a non-inverting transimpedance digital amplifier to create a differential transimpedance digital amplifier that permits direct interfacing between RSFQ and semiconductor electronics.

The invention includes a novel differentiator cell, a novel resample unit cell, and precision synchronization circuitry to ensure proper timing of the circuits and systems at the anticipated ultra-high speed of operation. The novel differentiator cell includes circuitry for combining a carry input signal, a data bit signal and the output signal of a NOT cell and applying the signals as distinct and separate pulses to the input of a toggle flip-flop (TFF) for producing an asynchronous carry output and a clocked data output. The novel differentiator cells can be interconnected to form a multi-bit differentiator circuit using appropriate delay and synchronization circuitry to compensate for delays in producing the carry output of each cell which is applied to a succeeding cell. The novel resample cell includes a non-destructive reset-set flip-flop (RSN) designed to receive a data bit, at its set input, at a slow clock rate, which data is repeatedly read out of the RSN at a fast clock rate, until the RSN is reset. The novel differentiator and resampler cells can be interconnected, for example, to form the differentiator and up-sampling sections of a digital interpolation filter (DIF). Also, the relative clocking of bit slices (columns) in such a DIF may be achieved by using the fast clock signal to synchronize the slow clock which controls data entry. The circuits of the invention can be advantageously implemented with Josephson Junctions in rapid-single-flux-quantum (RSFQ) logic.

A superconducting multi-bit digital mixer, designed using rapid single flux quantum (RSFQ) logic, for multiplying two independent digital streams, at least one of these comprising a plurality of parallel bit lines, wherein the output is also a similar plurality of bit lines. In a preferred embodiment, one of the digital streams represents a local oscillator signal, and the other digital stream digital radio frequency input from an analog-to-digital converter. The multi-bit mixer comprises an array of bit-slices, with the local oscillator signal generated using shift registers. This multi-bit mixer is suitable for an integrated circuit with application to a broadband digital radio frequency receiver, a digital correlation receiver, or a digital radio frequency transmitter. A synchronous pulse distribution network is used to ensure proper operation at data rates of 20 GHz or above.

A digital programmable frequency divider is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), and RSFQ D flip-flop and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of frequency division and the frequency divider selectively imparts a respective frequency division for any of 2^N states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.

A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an N^th-order bandpass sigma-delta ADC, with the order “N” being at least 2. The ADC includes a sequence of stages, which stages include feedback loops and resonators. The ADC further includes active superconducting components which directionally couple resonator pairs of adjacent stages. The active superconducting components electrically shield the higher order resonator from the lower order resonator. These active superconductor components include a superconducting quantum interference device (SQUID) amplifier, which is inductively coupled to the higher order resonator, and may include a Josephson transmission line (JTL), which is configured to electrically connect the SQUID amplifier to the lower order resonator. The first stage of ADC may employ an implicit feedback loop.

Routing and distribution of radio-frequency (RF) signals is commonly achieved in the analog domain. However, improved performance and simplified circuit architectures may be obtained by first digitizing the RF signal, and then carrying out all routing in the digital domain. A new generation of scalable digital switches has been developed, which routes both the data and clock signals together, this being necessary to maintain the integrity of the digitized RF signal. Given the extremely high switching speeds necessary for these applications (tens of GHz), this is implemented using Rapid-Single-Flux-Quantum (RSFQ) logic with superconducting integrated circuits. Such a digital switch matrix may be applied to either the receiver or transmitter components of an advanced multi-band, multi-channel digital transceiver system, and is compatible with routing of signals with different clock frequencies simultaneously within the same switch matrix.

The present invention discloss an ALU that can be operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using a half adder that uses a superconductor rapid single flux quantum logic device. The ALU using a half adder includes a half adder using a superconductor rapid single flux quantum logic device as a logic circuit, and a switching unit that has input ports respectively connected to a sum output port and a carry output port of the half adder and is operated as an OR gate, an AND gate, an adder gate and an exclusive OR gate using output signals of the half adder. The switching unit includes a first switch having an input port connected to the sum output port of the half adder, a second switch having an input port connected to the carry output port of the half adder and an output port connected to an output port of the first switch, and a third switch having an input port connected to the carry output port of the half adder.

A high-speed lookup table is designed using Rapid Single Flux Quantum (RSFQ) logic elements and fabricated using superconducting integrated circuits. The lookup table is composed of an address decoder and a programmable read-only memory array (PROM). The memory array has rapid parallel pipelined readout and slower serial reprogramming of memory contents. The memory cells are constructed using standard non-destructive reset-set flip-flops (RSN cells) and data flip-flops (DFF cells). An n-bit address decoder is implemented in the same technology and closely integrated with the memory array to achieve high-speed operation as a lookup table. The circuit architecture is scalable to large two-dimensional data arrays.

The present invention provides a low-temperature superconductive reading circuit based on the ERSFQ (Energy-efficient Rapid Single Flux Quantum) and a reading system. The circuit comprises: m superconduction quantum interference devices connected with a low-temperature superconductive sensor array and configured to convert the multi-output signals of the low-temperature superconductive sensor array to multiple SFQ pulse signals; an ERSFQ circuit connected with the m superconduction quantum interference devices and configured to convert the multiple SFQ pulse signals into the binary system one-way pulse signals for outputting; and a driving amplification circuit connected with the ERSFQ circuit and configured to perform amplification output of the binary system one-way pulse signals, wherein m is an integer of larger than 1. The low-temperature superconductive reading circuit based on ERSFQ and the reading system solve the problems that the reading amplification circuit is large in heat load and the circuit system anti-noise interference capability is bad in the prior art.

A programmable phase shifter is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ inverter and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of phase shift and the phase shifter selectively imparts a respective phase shift for any of 2^N states that can be represented by the digital word. The RSFQ logic elements utilize Josephson junctions which operate in the superconducting temperature domain.

The invention relates to an arithmetic logic unit operation method and system for a superconduction single magnetic flux quantum processor. A superconduction RSFQ (Rapid Single Flux Quantum) technology is adopted to overcome the problem of low speed and high power consumption of a traditional prior. Meanwhile, an arithmetic logic unit in the high-speed single magnetic flux quantum processor adoptsa summator of a 16-bit serial-parallel structure for operation processing, and the serial-parallel system structure has higher operation speed than the operation speed of a serial structure and needsfew hardware resources than the parallel structure. While ultra-high speed is realized, ultra-low power consumption is guaranteed. On the basis of a condition that the RSFQ large-scale integrated circuit technology at home and abroad meets a 64-bit RSFQ microprocessor core component, a 64-bit RSFQ ALU (Arithmetic Logical Unit) is subjected to logic design, and a foundation is laid for designing ultra high speed 64-bit RSFT microprocessors and computer systems.