67 results about "Exclusive or" patented technology

A method of encrypting data is disclosed. The method comprises determining, at a first node associated with a first public-private key pair of a cryptography system having a first private key (VA) and a first public key (PA), a common secret (S1) common with the first node and a second node, wherein the second node is associated with a second public-private key pair of the cryptography system having a second private key (VB) and a second public key (PB). The common secret is determined on the basis of the first private key and the second public key, and the properties of the cryptography system are such that the common secret can be determined on the basis of the second private key and the first public key. An encryption key, based on the common secret, is determined for encryption of data (M), and the data is encrypted on the basis of the encryption key, wherein the step of encrypting data includes an exclusive or (XOR) operation.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises an asynchronous data acquisition module for acquiring an asynchronous event pulse sequence of a discrete execution node; the mapping transformation module establishes an addressing mapping relation between an event source and a memory logic bit plane and generates an original differential bitmap; the bitmap filtering module is used for hedging paired logic flipping signals by utilizing an exclusive-OR logic self-reversal principle and filtering jitter interference at the edges of the signals so as to generate a net value difference bit plane; the state synchronization processing module performs in-situ upset updating on the state global bitmap through address offset addressing according to the bit identifier, and through a bitmap differential synchronization mechanism, asynchronous state updating without transaction lock constraint is achieved, calculation blocking generated by high-frequency pulse impact is relieved, and the real-time performance and stability of system data throughput are enhanced.

The invention discloses a data distribution statistical method, a storage device and data distribution detection equipment. The method comprises the steps that a controller determines target data in a storage unit based on a data distribution acquisition request in response to the received data distribution acquisition request; the controller obtains cache data corresponding to the target data in the storage cache according to the target data, wherein the cache data comprises at least two pages of cache page data; the controller performs logical operation on the at least two cache page data to obtain a logical operation result, the logical operation comprises AND operation, or the logical operation comprises XOR operation and AND operation; the controller obtains at least three target numbers based on the cache page data and the result that the data is one in the logical operation result; and the controller sends the at least three target numbers to an external controller, so that the external controller generates a data distribution result of the corresponding storage unit in a linear equation solution form based on the target numbers. In this way, the calculation occupation of the data distribution task on the external CPU is reduced.

A method of encrypting data is disclosed. The method comprises determining, at a first node associated with a first public-private key pair of a cryptography system having a first private key (VA) and a first public key (PA), a common secret (S1) common with the first node and a second node, wherein the second node is associated with a second public-private key pair of the cryptography system having a second private key (VB) and a second public key (PB). The common secret is determined on the basis of the first private key and the second public key, and the properties of the cryptography system are such that the common secret can be determined on the basis of the second private key and the first public key. An encryption key, based on the common secret, is determined for encryption of data (M), and the data is encrypted on the basis of the encryption key, wherein the step of encrypting data includes an exclusive or (XOR) operation.

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

The application discloses a memory data management method, an electronic device, a storage medium and a program product, relates to the technical field of storage, and comprises the following steps: realizing memory data management based on a native memory management mechanism and a page fault exception mechanism, processing the physical address of to-be-encrypted data by using a first key through step-by-step encryption, performing exclusive or operation on the obtained first ciphertext and the to-be-encrypted data, and storing the obtained second ciphertext into a red-black tree in a memory space, so that the encryption range is expanded, the data security is improved, the memory space and the red-black tree are fully utilized, and the addition, deletion and modification performance is improved. The target second ciphertext to be migrated is further encrypted and written into a swap area file. The method is realized by using pure software and does not depend on specific hardware devices. The technical problems of poor compatibility, high cost, being not conducive to large-scale application and great influence on system performance are solved, the technical effects of good compatibility, reduced cost, convenience for large-scale application and reduced influence on system performance are achieved.

A system and method for a secret-sharing encoding and decoding using exclusive OR (XOR) operations. A first apparatus includes a data splitting circuit to receive a secret and generate first, second, third, and fourth secret segments based on the secret and a secret share encoding circuit to generate first, second, third, and fourth secret shares by application of XOR operations to the first, second, third, and fourth secret segments. A second apparatus includes a secret share decoding circuit to receive first, second, third, and fourth secret shares and generate first, second, third, and fourth secret segments by application of an XOR operation to share encoded data of the first, second, third, and fourth secret shares, and a data aggregating circuit to: receive the first, second, third, and fourth secret segments; and recreate a secret by combining the first, second, third, and fourth secret segments.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

The invention discloses a binary MDS array code structure with high erasure correction performance and a decoding method, and the decoding method achieves the rapid calculation of a syndrome vector through an optimized scheduling algorithm, only needs the exclusive or and cyclic shift operation, reduces the calculation complexity to a linear level O (n), and remarkably improves the data recovery speed. Compared with a traditional RS code and an existing array code, high reliability is guaranteed, the technical problem that storage efficiency and calculation complexity are difficult to consider at the same time is solved, and the method is suitable for large-scale distributed storage scenes such as cloud computing and artificial intelligence training. According to the binary MDS array code structure with the high erasure performance and the decoding method, the fault-tolerant capability is improved to five-node failure, and the high-reliability storage requirement is met; the decoding calculation complexity is obviously reduced, and only xor and shift operations are needed; the storage efficiency reaches the upper bound of the MDS theory, and the storage cost is reduced; and efficient data recovery is realized under the configuration that the code length n is equal to 11 and the redundancy r is equal to 5.

The present application relates to a kind of program-controlled resistance card and its program-controlled resistor smooth control method, device, wherein the method includes obtaining the resistance card coding combination corresponding to current resistance value and target resistance value;Difference mask is calculated by exclusive or operation, and the relay set to be changed is identified;Based on the strategy of greedy algorithm, in the form of successive single-step switching, the relay that makes instantaneous resistance value closest to target value is selected from the set identified by difference mask and is operated;Switching and state updating are iteratively executed until difference mask is zero;Finally, switching completion signal is output.The device includes state acquisition, difference analysis, switching decision and driving execution module, and through the orderly single-step relay switching control, smooth transition in the resistance value change process is realized, the extreme state such as open circuit or short circuit is effectively avoided, the switching precision and system reliability are significantly improved, and it is suitable for precision test measurement and automation control field.

The invention discloses an error correction coding method and device of a memory bank, electronic equipment and a storage medium, and relates to the technical field of error correction coding in a memory data reading and transmission process. According to the method, a 12-bit first check bit is generated based on a 12-bit first data bit and a reconstructed parity check matrix, and the reconstructed parity check matrix unifies the data column weight of the first data bit as 6 and the check column weight as 1; arranging the first data bits and the first check bits according to an alternating sequence to generate interleaving code words; splitting the interleaved code word into a second data bit and a second check bit, and calculating according to the second data bit and the reconstructed parity check matrix to obtain a third check bit; performing XOR operation on the second check bit and the third check bit to obtain a syndrome; and according to the syndrome and a preset combined syndrome rule table, performing a correction operation to obtain a corrected first data bit, thereby solving the problem of errors of multiple adjacent bit data in a data transmission process, and reducing the complexity and delay of a coding and decoding module.

The application relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises the following modules: an asynchronous data acquisition module which collects asynchronous event pulse sequences of discrete execution nodes; a mapping transformation module which establishes an addressing mapping relationship between an event source and a memory logic bit plane and generates an original differential bit map; a bit map filtering module which uses the self-reflection principle of exclusive or logic to pair up logical flip signals, filters out the jitter interference of signal edges to generate a net value differential bit plane; and a state synchronization processing module which implements in-situ flip update of a state global bit map through address offset addressing according to a bit identifier. Through the bit map differential synchronization mechanism, the application realizes asynchronous state update without transaction lock constraint, alleviates the calculation blockage caused by high-frequency pulse impact, and enhances the real-time performance and stability of system data throughput.

The invention provides a method and a system for realizing AES (Advanced Encryption Standard) based on an FPGA (Field Programmable Gate Array), and relates to the field of channel transmission encryption and decryption, the method comprises the following steps: a plaintext is subjected to byte replacement, row shift, column mixing and round key addition circulation (N-1) rounds based on the FPGA, the Nth round is subjected to byte replacement, row shift and round key addition to obtain a ciphertext, and the number N of circulation rounds is designed according to the length of a key. The byte replacement comprises the following steps of: storing a byte lookup table by using an RAM (Random Access Memory) in an FPGA chip, and mapping a new byte in the lookup table according to each byte of the state equation to replace an original byte; the row shifting comprises the step of respectively circularly shifting the second row, the third row and the fourth row of the 4 * 4 state equation leftwards by 1, 2 and 3 bytes; column mixing comprises the following steps: left-multiplying a matrix of the state equation by a fixed matrix; the round key addition comprises the steps that the state equation and the round key are subjected to bitwise exclusive OR, a new state equation is obtained, and the round key is obtained through key expansion. According to the invention, the AES can be realized on the FPGA with fewer logic resources.

The embodiment of the invention provides a program compiling method and device.The method comprises the steps that a target source code is obtained, the target source code is compiled into a first intermediate representation, and a first instruction in the first intermediate representation has the capacity of storing first target data to a first target address in an encrypted memory of a trusted execution environment; adding a second intermediate representation to the first intermediate representation, the second intermediate representation being used for applying an XOR operation to the first target data through a randomly generated first random number to obtain first modified data, and storing the first random number to a target area in the encrypted memory; the first modification data replaces the first target data based on the first instruction; and generating a target machine code based on the first intermediate representation after the second intermediate representation is added.

The present invention discloses a secure pseudo-random number generator and method for high throughput of FPGA. The solution of the present invention is based on FPGA, and designs a 12-round permutation function and its module. In each round, a series of linear and non-linear operations are performed to fully scramble the input data; a round constant generator of a non-linear feedback shift register is designed, and exclusive OR operations are performed with data at specific positions; a counter and a logic circuit are set to optimize the processing of round constants to increase non-linear changes; a time threshold mechanism is set to re-seed operations regularly. The present invention significantly reduces and saves hardware resources, while also improving data randomness and anti-attack capabilities, improving the utilization rate of round constant storage resources, realizing high-throughput, efficient, and highly random pseudo-random number generation, achieving a balance between security and performance, improving efficiency, unpredictability, and hardware resource utilization rate, ensuring randomness and security during long-term operation.

The invention relates to a gating signal adjusting method, electronic equipment, a storage medium and a product, and the method comprises the steps: generating a target leading output signal based on a read enable signal; the target preamble output signal is a preamble output signal of which the data strobe signal DQS period number captured in an effective window reaches a DQS period number threshold value; based on the target leading output signal, respectively performing gating fine tuning on a leading gating path and a trailing gating path through a logic circuit to obtain a leading gating signal and a trailing gating signal; the rising edge of the leading gate control signal is aligned with the first rising edge of a leading section of the DQS, and the rising edge of the trailing gate control signal is aligned with the last rising edge of a trailing section of the DQS; and performing exclusive-or operation on the leading gate control signal and the trailing gate control signal to obtain a target gate control signal.

The invention relates to a key detection jitter removal implementation method. A key detection jitter removal system is constructed; according to the constructed key detection jitter removal system, a counting controller, a counter, a judgment module and a control module are connected in sequence, the counting controller is used for carrying out XOR operation on a key input signal and a jitter removal output signal, the counter is used for outputting a count value, and the judgment module is used for judging whether the count reaches a threshold value or not; the control module is used for negating the de-jitter output signal or keeping the de-jitter output signal; setting a signal and a de-jitter method; and inputting the key input into the key detection and jitter removal system, thereby realizing key detection and jitter removal. According to the simple key detection jitter removal method realized by adopting the FPGA, the jitter when the key is pressed down can be eliminated, the jitter when the key is lifted can also be eliminated, and the configuration is flexible. And meanwhile, the jitter detection time can be flexibly controlled by configuring a counter value.

The present invention provides an SRAM PUF key extraction method based on correlation judgment, comprising: an initial registration phase: powering on the SRAM, configuring and initializing variables; calculating the exclusive OR of a data block and its cyclic shifts of different points to obtain the number of cyclic shift points and the number of negatively correlated bits when the maximum negative correlation occurs; selecting N valid data blocks whose maximum negatively correlated bit numbers are greater than a set threshold; using N bits of hidden random numbers to control whether the valid data blocks are cyclically shifted according to the number of their maximum negatively correlated cyclic shift points; linearly encoding a randomly generated PUF output random number; performing an exclusive OR operation on the encoding result and the hidden random number to obtain auxiliary data; a reconstruction phase: powering on the SRAM, initializing variables, and obtaining a valid data block based on the auxiliary data selection; restoring an approximate random number of the hidden random number using the valid data block and the auxiliary data; performing an exclusive OR operation on the approximate random number and the auxiliary data to obtain a codeword before error correction; and performing linear encoding on the codeword to correct errors and restore the PUF output random number.

A communication device has a control section that generates a code word obtained by encoding information bits using an extended polar code that applies a stop of polarization achieved by addition of an XOR (Exclusive OR) operation and deletion based on the XOR operation, and a transmission section that transmits the code word to another communication device.

The invention discloses a data processing method and device, equipment and a storage medium, and relates to the technical field of data security storage, in the method, on one hand, in the encoding process, a first check block is considered, that is, not only is group division performed on a first sub-data block, but also group division is performed on the first check block, on the other hand, when a third check block is generated, group division is performed on a second sub-data block; for one of the second check blocks, the intermediate data block subjected to the exclusive-or operation with the second check block is not obtained based on the first check block corresponding to the second check block. On the basis of the two aspects, at least part of the finally obtained third check blocks comprise the first check blocks, and the first check blocks and the second check blocks obtained on the basis of the same coding function are not included in the same third check blocks. Therefore, when a single data block and a single check block are recovered, all the first sub-data blocks and all the second sub-data blocks do not need to be read, so that bandwidth consumption can be reduced, and the problem that in some technologies, the recovery bandwidth consumption of the check block is large can be solved.

A test device for a memory device includes a first exclusive OR (XOR) gate configured to output a first operation signal by performing an XOR operation between a clock signal and an output signal output from the memory device, an oscillator configured to output an oscillation signal, and an output circuit configured to determine a period of the oscillation signal. The output circuit may be configured to count a number of rising edges of the oscillation signal while the first operation signal is maintained at a high level, and determine an access time of the memory device based on the counted number of the rising edges, and a period of the oscillation signal.

The invention belongs to the field of quantum security multi-party computing, and discloses a verifiable quantum security multi-party XOR protocol based on super-dense coding. According to the preprocessing stage, for n participants Pj and two classical bits held by each participant, P0 obtains specific aggregation information of the classical bits of each participant through a super-dense coding means under the condition that only n quantum bits are transmitted, and meanwhile it is ensured that P0 cannot obtain the part, which is not authorized to check, of the bits held by each participant, so that the P0 is not allowed to check the part of the classical bits of each participant; through the method, the communication overhead in multi-party computing is greatly reduced. In the calculation stage, real input is hidden by using the secret key and the auxiliary value generated in the preprocessing stage, and exclusive-or operation is carried out under the condition that privacy input is not leaked. The protocol does not need the participation of a trusted third party, the trust dependence is eliminated, and decentralized security is realized; quantum state input is supported, and future quantum computing threats are defended; whether someone maliciously tampers the calculated value or not in the exclusive OR seeking process can be verified, and the method is suitable for sensitive scenes such as privacy calculation and conjoint analysis.

A system and method for a secret-sharing encoding and decoding using exclusive OR (XOR) operations. A first apparatus includes a data splitting circuit to receive a secret and generate first, second, third, and fourth secret segments based on the secret and a secret share encoding circuit to generate first, second, third, and fourth secret shares by application of XOR operations to the first, second, third, and fourth secret segments. A second apparatus includes a secret share decoding circuit to receive first, second, third, and fourth secret shares and generate first, second, third, and fourth secret segments by application of an XOR operation to share encoded data of the first, second, third, and fourth secret shares, and a data aggregating circuit to: receive the first, second, third, and fourth secret segments; and recreate a secret by combining the first, second, third, and fourth secret segments.

A method for processing a packet by an electronic device is provided. The method includes identifying a first packet including a first part, a second part, and a cyclic redundancy check (CRC) part, obtaining a second value by modifying a first value of the first part of the first packet, obtaining a third value by performing an exclusive or (XOR) operation on the first value and the obtained second value, obtaining a fourth value which is a CRC value for the obtained third value, obtaining a fifth value which is a CRC value corresponding to concatenation of the third value and a number of zeros corresponding to a length of the second part of the first packet, based on the length of the second part of the first packet and the obtained fourth value, obtaining a sixth value by performing the XOR operation on a value of the CRC part of the first packet and the obtained fifth value, and generating a second packet including a first part having the second value, a second part which is the same as the second part of the first packet, and a CRC part having the sixth value.

The application provides a multi-mode codec hardware implementation system, method, storage medium and device. The method comprises the following steps: a first data distribution control module distributes first input data to data selectors or mode control modules of different calculation engines according to first data distribution control parameters; the mode control module controls the exclusive OR operation of first data and second data, or controls the passing of the second data; a second data distribution control module distributes the output data of the mode control module to the data selectors of different calculation engines according to second data distribution control parameters; and a check control module controls whether an old check P or Q participates in calculation, and a calculation unit performs calculation based on the old check and the output data from the data selector. The application uses one calculation engine to realize three writing modes, adopts the calculation engine multiplexing mode to realize the RAID5 and RAID6 algorithms by using one hardware, so that the hardware resource utilization rate is significantly improved, and the hardware circuit area is greatly reduced.

A method for implementing a fast UBDM transform includes receiving a first input vector via a processor, and partitioning the first vector to produce a magnitude vector and a sign vector. A second vector comprising a modified magnitude vector and a modified sign vector is generated by applying a permutation to the vector value vector to produce the modified magnitude vector, converting the sign vector to an intermediate sign vector based on an algorithm, and applying a non-linear layer to the intermediate sign vector. Each non-linear layer comprises a permutation, an S-box transform, a diffusion linear operation, and / or an exclusive OR operation. A plurality of linear layers are applied to the second vector to produce a third vector, the third vector being a transformed version of the first vector. A first signal representing the third vector is sent to at least one transmitter for sending a second signal representing the transformed data vector.

The application provides a dynamic encoding method and device based on parallel filters, which is applied to a Reed Solomon encoder provided with a parallel first-order filter array: a target check byte quantity value and a plurality of information data bytes are acquired; the target check byte quantity value is decoded and converted into a thermometer code vector, a parallel first-order filter array is logically cut, and an enabled first-order filter is connected to a bimodal exclusive OR tree; the information data bytes are broadcast to the first-order filter by using a prefix and the exclusive OR tree, and a Galois field multiplication and addition operation is synchronously executed by the first-order filter to iteratively update an internal register state; the internal register state of the first-order filter is iteratively processed by using a suffix and the exclusive OR tree, and a check byte is output in real time to complete a dynamic encoding process. Through the above method, real-time dynamic configuration of encoding parameters and efficient encoding operation are realized, and chip power consumption is effectively reduced, timing performance is optimized, and continuity and reliability of an encoding process are improved.

The application discloses a construction method and device of a block cipher round function, electronic equipment and a storage medium, wherein the method comprises the following steps: performing bit-by-bit exclusive or whitening of a key generation round function initial state on a plaintext block; replacing 32 S-box units of the round function one by one by using an S-box with multiple bits; performing bit grouping on the replaced round function, performing exclusive or on the bit grouping with a multi-bit constant, and performing position permutation on 32 positions of the round function as an S-box unit, so that there is no 9-round impossible differential based on the iteration of the round function, and there is also no 9-round effective differential route; multiplying each column of an intermediate state matrix of the round function by a preset matrix from the left to perform column mixing, and performing bit-by-bit exclusive or on the round function after the column mixing and a round key; and obtaining a final state of the round function after multiple iterations. Thus, the problems of high resource occupation in the hardware efficient implementation of the existing block cipher algorithm and low software implementation efficiency are solved.

The disclosure provides a kind of embedded simulation switch's power utilization information acquisition terminal fault simulation method and device, specifically, terminal receives remote host instruction, obtains switch trigger mask, trigger target value, state precondition, fault data template and reset condition by parsing;Current global state vector of terminal is generated, and it is compared by being operated with precondition mask and expected value, if it is satisfied, then according to trigger mask and target value, update global state vector, flip or set corresponding logic switch;When logic switch enters trigger state, locate to the data cache area of key function node, first backup original target data, then execute bit by bit exclusive or operation to cache area data and fault template, complete the generation and injection of fault data;Reset condition is monitored continuously during simulation execution, reset all logic switches to default state, and using backup data restores data cache area to original state, clear simulation trace, terminate fault simulation process.