43 results about "Exclusive or" patented technology

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises an asynchronous data acquisition module for acquiring an asynchronous event pulse sequence of a discrete execution node; the mapping transformation module establishes an addressing mapping relation between an event source and a memory logic bit plane and generates an original differential bitmap; the bitmap filtering module is used for hedging paired logic flipping signals by utilizing an exclusive-OR logic self-reversal principle and filtering jitter interference at the edges of the signals so as to generate a net value difference bit plane; the state synchronization processing module performs in-situ upset updating on the state global bitmap through address offset addressing according to the bit identifier, and through a bitmap differential synchronization mechanism, asynchronous state updating without transaction lock constraint is achieved, calculation blocking generated by high-frequency pulse impact is relieved, and the real-time performance and stability of system data throughput are enhanced.

A method of encrypting data is disclosed. The method comprises determining, at a first node associated with a first public-private key pair of a cryptography system having a first private key (VA) and a first public key (PA), a common secret (S1) common with the first node and a second node, wherein the second node is associated with a second public-private key pair of the cryptography system having a second private key (VB) and a second public key (PB). The common secret is determined on the basis of the first private key and the second public key, and the properties of the cryptography system are such that the common secret can be determined on the basis of the second private key and the first public key. An encryption key, based on the common secret, is determined for encryption of data (M), and the data is encrypted on the basis of the encryption key, wherein the step of encrypting data includes an exclusive or (XOR) operation.

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

The application discloses a memory data management method, an electronic device, a storage medium and a program product, relates to the technical field of storage, and comprises the following steps: realizing memory data management based on a native memory management mechanism and a page fault exception mechanism, processing the physical address of to-be-encrypted data by using a first key through step-by-step encryption, performing exclusive or operation on the obtained first ciphertext and the to-be-encrypted data, and storing the obtained second ciphertext into a red-black tree in a memory space, so that the encryption range is expanded, the data security is improved, the memory space and the red-black tree are fully utilized, and the addition, deletion and modification performance is improved. The target second ciphertext to be migrated is further encrypted and written into a swap area file. The method is realized by using pure software and does not depend on specific hardware devices. The technical problems of poor compatibility, high cost, being not conducive to large-scale application and great influence on system performance are solved, the technical effects of good compatibility, reduced cost, convenience for large-scale application and reduced influence on system performance are achieved.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

The invention discloses a binary MDS array code structure with high erasure correction performance and a decoding method, and the decoding method achieves the rapid calculation of a syndrome vector through an optimized scheduling algorithm, only needs the exclusive or and cyclic shift operation, reduces the calculation complexity to a linear level O (n), and remarkably improves the data recovery speed. Compared with a traditional RS code and an existing array code, high reliability is guaranteed, the technical problem that storage efficiency and calculation complexity are difficult to consider at the same time is solved, and the method is suitable for large-scale distributed storage scenes such as cloud computing and artificial intelligence training. According to the binary MDS array code structure with the high erasure performance and the decoding method, the fault-tolerant capability is improved to five-node failure, and the high-reliability storage requirement is met; the decoding calculation complexity is obviously reduced, and only xor and shift operations are needed; the storage efficiency reaches the upper bound of the MDS theory, and the storage cost is reduced; and efficient data recovery is realized under the configuration that the code length n is equal to 11 and the redundancy r is equal to 5.

The present application relates to a kind of program-controlled resistance card and its program-controlled resistor smooth control method, device, wherein the method includes obtaining the resistance card coding combination corresponding to current resistance value and target resistance value;Difference mask is calculated by exclusive or operation, and the relay set to be changed is identified;Based on the strategy of greedy algorithm, in the form of successive single-step switching, the relay that makes instantaneous resistance value closest to target value is selected from the set identified by difference mask and is operated;Switching and state updating are iteratively executed until difference mask is zero;Finally, switching completion signal is output.The device includes state acquisition, difference analysis, switching decision and driving execution module, and through the orderly single-step relay switching control, smooth transition in the resistance value change process is realized, the extreme state such as open circuit or short circuit is effectively avoided, the switching precision and system reliability are significantly improved, and it is suitable for precision test measurement and automation control field.

The invention discloses an error correction coding method and device of a memory bank, electronic equipment and a storage medium, and relates to the technical field of error correction coding in a memory data reading and transmission process. According to the method, a 12-bit first check bit is generated based on a 12-bit first data bit and a reconstructed parity check matrix, and the reconstructed parity check matrix unifies the data column weight of the first data bit as 6 and the check column weight as 1; arranging the first data bits and the first check bits according to an alternating sequence to generate interleaving code words; splitting the interleaved code word into a second data bit and a second check bit, and calculating according to the second data bit and the reconstructed parity check matrix to obtain a third check bit; performing XOR operation on the second check bit and the third check bit to obtain a syndrome; and according to the syndrome and a preset combined syndrome rule table, performing a correction operation to obtain a corrected first data bit, thereby solving the problem of errors of multiple adjacent bit data in a data transmission process, and reducing the complexity and delay of a coding and decoding module.

The application relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises the following modules: an asynchronous data acquisition module which collects asynchronous event pulse sequences of discrete execution nodes; a mapping transformation module which establishes an addressing mapping relationship between an event source and a memory logic bit plane and generates an original differential bit map; a bit map filtering module which uses the self-reflection principle of exclusive or logic to pair up logical flip signals, filters out the jitter interference of signal edges to generate a net value differential bit plane; and a state synchronization processing module which implements in-situ flip update of a state global bit map through address offset addressing according to a bit identifier. Through the bit map differential synchronization mechanism, the application realizes asynchronous state update without transaction lock constraint, alleviates the calculation blockage caused by high-frequency pulse impact, and enhances the real-time performance and stability of system data throughput.

The embodiment of the invention provides a program compiling method and device.The method comprises the steps that a target source code is obtained, the target source code is compiled into a first intermediate representation, and a first instruction in the first intermediate representation has the capacity of storing first target data to a first target address in an encrypted memory of a trusted execution environment; adding a second intermediate representation to the first intermediate representation, the second intermediate representation being used for applying an XOR operation to the first target data through a randomly generated first random number to obtain first modified data, and storing the first random number to a target area in the encrypted memory; the first modification data replaces the first target data based on the first instruction; and generating a target machine code based on the first intermediate representation after the second intermediate representation is added.

A communication device has a control section that generates a code word obtained by encoding information bits using an extended polar code that applies a stop of polarization achieved by addition of an XOR (Exclusive OR) operation and deletion based on the XOR operation, and a transmission section that transmits the code word to another communication device.

The invention discloses a data processing method and device, equipment and a storage medium, and relates to the technical field of data security storage, in the method, on one hand, in the encoding process, a first check block is considered, that is, not only is group division performed on a first sub-data block, but also group division is performed on the first check block, on the other hand, when a third check block is generated, group division is performed on a second sub-data block; for one of the second check blocks, the intermediate data block subjected to the exclusive-or operation with the second check block is not obtained based on the first check block corresponding to the second check block. On the basis of the two aspects, at least part of the finally obtained third check blocks comprise the first check blocks, and the first check blocks and the second check blocks obtained on the basis of the same coding function are not included in the same third check blocks. Therefore, when a single data block and a single check block are recovered, all the first sub-data blocks and all the second sub-data blocks do not need to be read, so that bandwidth consumption can be reduced, and the problem that in some technologies, the recovery bandwidth consumption of the check block is large can be solved.

The invention belongs to the field of quantum security multi-party computing, and discloses a verifiable quantum security multi-party XOR protocol based on super-dense coding. According to the preprocessing stage, for n participants Pj and two classical bits held by each participant, P0 obtains specific aggregation information of the classical bits of each participant through a super-dense coding means under the condition that only n quantum bits are transmitted, and meanwhile it is ensured that P0 cannot obtain the part, which is not authorized to check, of the bits held by each participant, so that the P0 is not allowed to check the part of the classical bits of each participant; through the method, the communication overhead in multi-party computing is greatly reduced. In the calculation stage, real input is hidden by using the secret key and the auxiliary value generated in the preprocessing stage, and exclusive-or operation is carried out under the condition that privacy input is not leaked. The protocol does not need the participation of a trusted third party, the trust dependence is eliminated, and decentralized security is realized; quantum state input is supported, and future quantum computing threats are defended; whether someone maliciously tampers the calculated value or not in the exclusive OR seeking process can be verified, and the method is suitable for sensitive scenes such as privacy calculation and conjoint analysis.

A method for processing a packet by an electronic device is provided. The method includes identifying a first packet including a first part, a second part, and a cyclic redundancy check (CRC) part, obtaining a second value by modifying a first value of the first part of the first packet, obtaining a third value by performing an exclusive or (XOR) operation on the first value and the obtained second value, obtaining a fourth value which is a CRC value for the obtained third value, obtaining a fifth value which is a CRC value corresponding to concatenation of the third value and a number of zeros corresponding to a length of the second part of the first packet, based on the length of the second part of the first packet and the obtained fourth value, obtaining a sixth value by performing the XOR operation on a value of the CRC part of the first packet and the obtained fifth value, and generating a second packet including a first part having the second value, a second part which is the same as the second part of the first packet, and a CRC part having the sixth value.

The application provides a multi-mode codec hardware implementation system, method, storage medium and device. The method comprises the following steps: a first data distribution control module distributes first input data to data selectors or mode control modules of different calculation engines according to first data distribution control parameters; the mode control module controls the exclusive OR operation of first data and second data, or controls the passing of the second data; a second data distribution control module distributes the output data of the mode control module to the data selectors of different calculation engines according to second data distribution control parameters; and a check control module controls whether an old check P or Q participates in calculation, and a calculation unit performs calculation based on the old check and the output data from the data selector. The application uses one calculation engine to realize three writing modes, adopts the calculation engine multiplexing mode to realize the RAID5 and RAID6 algorithms by using one hardware, so that the hardware resource utilization rate is significantly improved, and the hardware circuit area is greatly reduced.

A method for implementing a fast UBDM transform includes receiving a first input vector via a processor, and partitioning the first vector to produce a magnitude vector and a sign vector. A second vector comprising a modified magnitude vector and a modified sign vector is generated by applying a permutation to the vector value vector to produce the modified magnitude vector, converting the sign vector to an intermediate sign vector based on an algorithm, and applying a non-linear layer to the intermediate sign vector. Each non-linear layer comprises a permutation, an S-box transform, a diffusion linear operation, and / or an exclusive OR operation. A plurality of linear layers are applied to the second vector to produce a third vector, the third vector being a transformed version of the first vector. A first signal representing the third vector is sent to at least one transmitter for sending a second signal representing the transformed data vector.

The application provides a dynamic encoding method and device based on parallel filters, which is applied to a Reed Solomon encoder provided with a parallel first-order filter array: a target check byte quantity value and a plurality of information data bytes are acquired; the target check byte quantity value is decoded and converted into a thermometer code vector, a parallel first-order filter array is logically cut, and an enabled first-order filter is connected to a bimodal exclusive OR tree; the information data bytes are broadcast to the first-order filter by using a prefix and the exclusive OR tree, and a Galois field multiplication and addition operation is synchronously executed by the first-order filter to iteratively update an internal register state; the internal register state of the first-order filter is iteratively processed by using a suffix and the exclusive OR tree, and a check byte is output in real time to complete a dynamic encoding process. Through the above method, real-time dynamic configuration of encoding parameters and efficient encoding operation are realized, and chip power consumption is effectively reduced, timing performance is optimized, and continuity and reliability of an encoding process are improved.

The application discloses a construction method and device of a block cipher round function, electronic equipment and a storage medium, wherein the method comprises the following steps: performing bit-by-bit exclusive or whitening of a key generation round function initial state on a plaintext block; replacing 32 S-box units of the round function one by one by using an S-box with multiple bits; performing bit grouping on the replaced round function, performing exclusive or on the bit grouping with a multi-bit constant, and performing position permutation on 32 positions of the round function as an S-box unit, so that there is no 9-round impossible differential based on the iteration of the round function, and there is also no 9-round effective differential route; multiplying each column of an intermediate state matrix of the round function by a preset matrix from the left to perform column mixing, and performing bit-by-bit exclusive or on the round function after the column mixing and a round key; and obtaining a final state of the round function after multiple iterations. Thus, the problems of high resource occupation in the hardware efficient implementation of the existing block cipher algorithm and low software implementation efficiency are solved.

The disclosure provides a kind of embedded simulation switch's power utilization information acquisition terminal fault simulation method and device, specifically, terminal receives remote host instruction, obtains switch trigger mask, trigger target value, state precondition, fault data template and reset condition by parsing;Current global state vector of terminal is generated, and it is compared by being operated with precondition mask and expected value, if it is satisfied, then according to trigger mask and target value, update global state vector, flip or set corresponding logic switch;When logic switch enters trigger state, locate to the data cache area of key function node, first backup original target data, then execute bit by bit exclusive or operation to cache area data and fault template, complete the generation and injection of fault data;Reset condition is monitored continuously during simulation execution, reset all logic switches to default state, and using backup data restores data cache area to original state, clear simulation trace, terminate fault simulation process.

Techniques for rotation in response to an instance of a single instruction are described. In some examples, an exclusive OR is also performed. In some examples, the instruction has one or more fields for an opcode, a first source operand, a second source operand, a third source operand location, a destination operand location, and an immediate, wherein the opcode is to indicate execution circuitry is to rotate each data element of the third source operand by 1 to generate a rotated third source operand, exclusive or (XOR) corresponding data elements of the first source operand, the second source operand, and the rotated third source operand, rotate the XORed data elements by an amount indicated by the immediate, and store a result of the rotated, XORed data elements. In some examples, a dispatch port is associated with a different set of execution circuitry, wherein each different set of execution circuitry is to support a different maximum rotate amount, and wherein the immediate is to be used to determine which of the dispatch ports to use.

The invention relates to the technical field of communication, in particular to a CRC (Cyclic Redundancy Check) code generation circuit, a first input end of a jth first calculation unit is used for receiving a jth data block of current to-be-processed data, and when j = 1, a second input end is used for receiving data 0, when jgt; when 1, the first input end is used for receiving output data of the (j-1) th first calculation unit. The jth first calculation unit is used for generating output data and transmitting the output data to the first input end of the jth XOR unit. And the jth second calculation unit is used for generating output data and transmitting the output data to the second input end of the jth XOR unit. The jth XOR unit is used for generating output data and transmitting the output data to the jth input port of the J-path selector; and the J-path selector is used for gating the kth input port and outputting a CRC check code. According to the invention, combinational logic resources occupied by the CRC code generation circuit can be reduced, and the operation working frequency of the CRC code generation circuit is improved.

The application provides a key negotiation method based on a polar code and an electronic device, wherein the method is applied to a key encoding end, and the method comprises the following steps: generating a random sequence and a negotiation key; encoding the random sequence based on a preset cyclic redundancy check generation rule and a polar code encoding algorithm to obtain a first code word; performing an exclusive or operation on the negotiation key and the first code word to generate first information; and sending the first information to a key decoding end, so that the key decoding end decodes the first information to obtain a target key consistent with the negotiation key. The key negotiation method based on the polar code and the electronic device can effectively improve the decoding accuracy, and improve the consistency and overall reliability of the key negotiation.

The invention belongs to the technical field of integrated circuit design, and particularly relates to an in-memory floating-point number calculation circuit and method based on a spin-orbit moment magnetic random access memory, and the circuit comprises a row decoder, a writing circuit, an SOT-MRAM array, a sensing amplifier SA, a control module, a column selection unit, a shifter and a rounding circuit. When the floating-point number multiplication circuit is used for carrying out floating-point number multiplication, an exclusive-OR gate is further constructed through a majority of logic gates constructed in the storage array, and the adder and the multiplier respectively carry out floating-point number sign bit exclusive-OR operation, exponent bit addition operation and mantissa multiplication operation. The mantissa bit normalization and rounding operations are respectively completed by an array external shifter and a rounding circuit, and adders and multipliers with different bits can be constructed in the storage array according to the type of the floating-point number. The method and the device can support calculation of multiple types of floating-point numbers and effectively reduce power consumption of floating-point number calculation.

The application discloses a control bit generation method and device of an inverse butterfly network adopting a dynamic programming strategy, and solves the problem of poor flexibility of the control bit generation method of the inverse butterfly network in the prior art. The method comprises the following steps: obtaining preset data; determining the inverse butterfly network, the number of stages of the inverse butterfly network and the number of switching units in each stage of the inverse butterfly network according to the preset data; obtaining node extraction position information of a plurality of extraction nodes, a plurality of output nodes and a plurality of exclusive or operation results; traversing the inverse butterfly network, and calculating the switching position information corresponding to the plurality of extraction nodes in each stage; determining the exclusive or operation result corresponding to the extraction node; judging whether the exclusive or operation result is equal to a judgment value, if yes, setting the control bit of the switching unit position corresponding to the exclusive or operation result to 1, and saving the control bit in a control bit storage list; and the flexibility of generating the corresponding control bit algorithm of the inverse butterfly network according to the extraction demand is realized, and the efficiency is improved.

The application provides a device shadow processing method and device, electronic equipment and medium, and relates to the technical field of information security. The method comprises the following steps: determining a first key and a second key corresponding to the first key based on a first sub-key and a second sub-key obtained by performing key division on an initial key; performing data division on device data of a current device to obtain a plurality of data blocks and a position sequence between the data blocks; performing exclusive or operation on the plurality of data blocks and the second key respectively to obtain an exclusive or result corresponding to each data block; processing the exclusive or results corresponding to the plurality of data blocks respectively to obtain a ciphertext of the device data; and synchronizing the device data, a data identifier of the device data, the ciphertext, and a corresponding relationship between the data identifier and the ciphertext to a preconfigured device shadow. The method can increase the security of the key, and relevant personnel can still safely use the device shadow when the device and the device shadow are disconnected.

The application relates to a power grid data management method and device based on a blockchain platform, computer equipment and a readable storage medium. In the whole life management cycle of power grid data, early warning rule data is converted into a binary sequence D, a group of random binary keys K is generated through quantum entanglement or quantum randomness, a bitwise exclusive or operation is performed on the early warning rule data after processing of the binary sequence using the keys, ciphertext is obtained, an intelligent contract is generated based on the ciphertext, and the intelligent contract is chained and deployed, so that each node of the blockchain platform performs early warning on power grid data of the blockchain platform based on early warning rule data carried by the intelligent contract, effective data security guarantee is provided for power grid data management based on the blockchain platform, the early warning rule based on the encryption method can also be guaranteed not to be tampered with and to reach a rule consensus of the whole power grid, and therefore, safe management of power grid data can be realized.

The invention discloses high-speed bit error rate testing equipment, which relates to the technical field of data transmission testing and comprises an LVDS (Low Voltage Differential Signaling) receiving module for converting a single-ended signal sent by tested equipment into a high-speed differential signal, a USB (Universal Serial Bus) interface module for carrying out high-speed data interaction communication with an upper computer, and an FPGA (Field Programmable Gate Array) core module, the FPGA core module comprises a communication sub-module for obtaining original comparison data according to configuration parameters; the LVDS signal analysis sub-module is used for carrying out clock synchronization on the high-speed differential signals and carrying out double-edge sampling to obtain analysis data, and the comparison operation sub-module is used for carrying out proportion-by-proportion exclusive OR operation on original comparison data and the analysis data by adopting combinational logic to obtain an error rate calculation result. The method can be widely applied to testing of various devices adopting differential signals.

The present invention relates to an error correction code apparatus comprising a data input node configured to receive data to be encoded, and an encoder in communication with the data input node and configured to generate a first result by multiplying data bits by a first matrix, divide parity check bits into a first parity check group and a second parity check group based on a plurality of polynomials determined according to a second matrix, the first parity check group being obtained by multiplying the first result by the second matrix, the second parity check group being obtained by an exclusive OR operation on the first result and the first parity check group, multiply the first result by the second matrix to generate one or more first parity check bits in the first parity check group, perform an exclusive OR operation on the first result and the first parity check group to generate one or more second parity check bits in the second parity check group, and generate a codeword having the data bits and the parity check bits.

The present application relates to the technical field of traceability management, in particular to a food processing raw material traceability management system and method based on a block chain, which comprises an attribute data acquisition module, a version sequence construction module, a node consensus verification module, a version continuity determination module and a traceability chain management module.In the present application, the bottom attribute characteristics are constructed by mapping the physical detection signal to the discrete interval, the tamper risk is resisted by constructing the continuity index structure through the head-to-tail mapping and hash calculation according to the time sequence based on the network node query version sequence, the link data credibility is ensured by encapsulating and storing the data only when the characteristic aggregation voting reaches the set value through the interception of the characteristic by the numerous verification nodes in the distributed architecture, the topological abnormal gap is captured by measuring the path migration amount according to the adjacent serial number difference and span comparison, the synchronous extraction of the historical record is performed by the exclusive or logic judgment, the mapping associated gap is triggered to block the instruction when the difference mark is reversed, and the whole chain anti-fake management is realized to guarantee the authenticity.