10 results about "Exclusive or" patented technology

A communication device has a control section that generates a code word obtained by encoding information bits using an extended polar code that applies a stop of polarization achieved by addition of an XOR (Exclusive OR) operation and deletion based on the XOR operation, and a transmission section that transmits the code word to another communication device.

The application provides a multi-mode codec hardware implementation system, method, storage medium and device. The method comprises the following steps: a first data distribution control module distributes first input data to data selectors or mode control modules of different calculation engines according to first data distribution control parameters; the mode control module controls the exclusive OR operation of first data and second data, or controls the passing of the second data; a second data distribution control module distributes the output data of the mode control module to the data selectors of different calculation engines according to second data distribution control parameters; and a check control module controls whether an old check P or Q participates in calculation, and a calculation unit performs calculation based on the old check and the output data from the data selector. The application uses one calculation engine to realize three writing modes, adopts the calculation engine multiplexing mode to realize the RAID5 and RAID6 algorithms by using one hardware, so that the hardware resource utilization rate is significantly improved, and the hardware circuit area is greatly reduced.

The disclosure provides a kind of embedded simulation switch's power utilization information acquisition terminal fault simulation method and device, specifically, terminal receives remote host instruction, obtains switch trigger mask, trigger target value, state precondition, fault data template and reset condition by parsing;Current global state vector of terminal is generated, and it is compared by being operated with precondition mask and expected value, if it is satisfied, then according to trigger mask and target value, update global state vector, flip or set corresponding logic switch;When logic switch enters trigger state, locate to the data cache area of key function node, first backup original target data, then execute bit by bit exclusive or operation to cache area data and fault template, complete the generation and injection of fault data;Reset condition is monitored continuously during simulation execution, reset all logic switches to default state, and using backup data restores data cache area to original state, clear simulation trace, terminate fault simulation process.

Techniques for rotation in response to an instance of a single instruction are described. In some examples, an exclusive OR is also performed. In some examples, the instruction has one or more fields for an opcode, a first source operand, a second source operand, a third source operand location, a destination operand location, and an immediate, wherein the opcode is to indicate execution circuitry is to rotate each data element of the third source operand by 1 to generate a rotated third source operand, exclusive or (XOR) corresponding data elements of the first source operand, the second source operand, and the rotated third source operand, rotate the XORed data elements by an amount indicated by the immediate, and store a result of the rotated, XORed data elements. In some examples, a dispatch port is associated with a different set of execution circuitry, wherein each different set of execution circuitry is to support a different maximum rotate amount, and wherein the immediate is to be used to determine which of the dispatch ports to use.

The application discloses a control bit generation method and device of an inverse butterfly network adopting a dynamic programming strategy, and solves the problem of poor flexibility of the control bit generation method of the inverse butterfly network in the prior art. The method comprises the following steps: obtaining preset data; determining the inverse butterfly network, the number of stages of the inverse butterfly network and the number of switching units in each stage of the inverse butterfly network according to the preset data; obtaining node extraction position information of a plurality of extraction nodes, a plurality of output nodes and a plurality of exclusive or operation results; traversing the inverse butterfly network, and calculating the switching position information corresponding to the plurality of extraction nodes in each stage; determining the exclusive or operation result corresponding to the extraction node; judging whether the exclusive or operation result is equal to a judgment value, if yes, setting the control bit of the switching unit position corresponding to the exclusive or operation result to 1, and saving the control bit in a control bit storage list; and the flexibility of generating the corresponding control bit algorithm of the inverse butterfly network according to the extraction demand is realized, and the efficiency is improved.

The application provides a device shadow processing method and device, electronic equipment and medium, and relates to the technical field of information security. The method comprises the following steps: determining a first key and a second key corresponding to the first key based on a first sub-key and a second sub-key obtained by performing key division on an initial key; performing data division on device data of a current device to obtain a plurality of data blocks and a position sequence between the data blocks; performing exclusive or operation on the plurality of data blocks and the second key respectively to obtain an exclusive or result corresponding to each data block; processing the exclusive or results corresponding to the plurality of data blocks respectively to obtain a ciphertext of the device data; and synchronizing the device data, a data identifier of the device data, the ciphertext, and a corresponding relationship between the data identifier and the ciphertext to a preconfigured device shadow. The method can increase the security of the key, and relevant personnel can still safely use the device shadow when the device and the device shadow are disconnected.

The application provides a heterojunction structure with perpendicular magnetic anisotropy at room temperature and an application thereof. The heterojunction structure comprises a van der Waals topological material layer and a two-dimensional magnetic material layer, wherein the thickness of the van der Waals topological material layer is 5-20 nm, and the thickness of the two-dimensional magnetic material layer is 1-10 nm. The application further provides a room-temperature full van der Waals spin-orbit torque magnetic memory comprising the above heterojunction structure, a room-temperature full van der Waals magnetoresistance device based on a topological insulator, and a device for implementing exclusive OR logic operation, a device for implementing bit counting operation, a device for implementing matrix-vector multiplication operation, and corresponding methods. The technical scheme of the application realizes the construction of a heterojunction structure with perpendicular magnetic anisotropy at room temperature and a spin electronic prototype device, and the prepared heterojunction structure and spin prototype device are simple, and the preparation method is simple to operate.

The application discloses a kind of parallelization multiplication operation methods of floating point number based on FPGA, comprising the following steps: based on the representation under IEEE754 different precision, design a kind of low-precision storage mode that can be blocked, including the design of exponent block and floating block;Then design arbitrary variable bit floating block fixed-point addition, variable bit floating block fixed-point multiplication is realized by the way of multiplication pool;Then using FPGA, the multiplication calculation result between the sign bit and the exponent bit of the multiplicand and the multiplier is obtained by exclusive or operation and fixed-point addition, the multiplication calculation result of the significand bit of the multiplicand and the multiplier is obtained by fixed-point multiplication;Finally, the obtained multiplication calculation result is normalized.The application can be effectively applied in memory computing, with the increase of the number of blocks, the data calculation delay can be significantly reduced, and the variable precision can improve the flexibility of calculation.