80 results about "Exclusive or" patented technology

The embodiment of the invention provides a data coding method and a related device. The coding complexity is reduced while the code word length and the redundancy cost of an inner code are not changed. Specifically, for a first data stream subjected to outer code coding, every continuous k bits in the first data stream need to be subjected to inner code coding, and k is an odd number greater than 1. The other bits except one target bit in the k bits are subjected to XOR pairwise to obtain (k-1) / 2 bits in total. Further, a bit sequence including (k-1) / 2 bits and a target bit is subjected to second FEC coding to obtain p check bits. Wherein the n bits in the code word of the inner code after the inner code is coded comprise continuous k bits and p check bits. It can be seen that the embodiment of the invention adopts a mode of first exclusive OR and then encoding, for example, code word processing of (128, 119) can be realized through an encoder of (69, 60), and the encoding complexity is reduced while the code word length of an inner code and the redundancy cost are not changed.

A method of encrypting data is disclosed. The method comprises determining, at a first node associated with a first public-private key pair of a cryptography system having a first private key (VA) and a first public key (PA), a common secret (S1) common with the first node and a second node, wherein the second node is associated with a second public-private key pair of the cryptography system having a second private key (VB) and a second public key (PB). The common secret is determined on the basis of the first private key and the second public key, and the properties of the cryptography system are such that the common secret can be determined on the basis of the second private key and the first public key. An encryption key, based on the common secret, is determined for encryption of data (M), and the data is encrypted on the basis of the encryption key, wherein the step of encrypting data includes an exclusive or (XOR) operation.

The present application relates to the field of communication technology, especially to a CRC check code generation circuit, wherein the first input end of the jth first calculation unit is used for receiving the jth data block of current data to be processed, when j=1, the second input end is used for receiving data 0, when j>1, the first input end is used for receiving the output data of the j-1th first calculation unit. The jth first calculation unit is used for generating output data, which is transmitted to the first input end of the jth exclusive or unit. The jth second calculation unit is used for generating output data, which is transmitted to the second input end of the jth exclusive or unit. The jth exclusive or unit is used for generating output data, which is transmitted to the jth input port of the J-way selector; the J-way selector is used for selecting the kth input port and outputting the CRC check code. The present application can reduce the combination logic resources occupied by the CRC check code generation circuit and improve the operation frequency of the CRC check code generation circuit.

The invention relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises an asynchronous data acquisition module for acquiring an asynchronous event pulse sequence of a discrete execution node; the mapping transformation module establishes an addressing mapping relation between an event source and a memory logic bit plane and generates an original differential bitmap; the bitmap filtering module is used for hedging paired logic flipping signals by utilizing an exclusive-OR logic self-reversal principle and filtering jitter interference at the edges of the signals so as to generate a net value difference bit plane; the state synchronization processing module performs in-situ upset updating on the state global bitmap through address offset addressing according to the bit identifier, and through a bitmap differential synchronization mechanism, asynchronous state updating without transaction lock constraint is achieved, calculation blocking generated by high-frequency pulse impact is relieved, and the real-time performance and stability of system data throughput are enhanced.

The invention discloses a data distribution statistical method, a storage device and data distribution detection equipment. The method comprises the steps that a controller determines target data in a storage unit based on a data distribution acquisition request in response to the received data distribution acquisition request; the controller obtains cache data corresponding to the target data in the storage cache according to the target data, wherein the cache data comprises at least two pages of cache page data; the controller performs logical operation on the at least two cache page data to obtain a logical operation result, the logical operation comprises AND operation, or the logical operation comprises XOR operation and AND operation; the controller obtains at least three target numbers based on the cache page data and the result that the data is one in the logical operation result; and the controller sends the at least three target numbers to an external controller, so that the external controller generates a data distribution result of the corresponding storage unit in a linear equation solution form based on the target numbers. In this way, the calculation occupation of the data distribution task on the external CPU is reduced.

A method of encrypting data is disclosed. The method comprises determining, at a first node associated with a first public-private key pair of a cryptography system having a first private key (VA) and a first public key (PA), a common secret (S1) common with the first node and a second node, wherein the second node is associated with a second public-private key pair of the cryptography system having a second private key (VB) and a second public key (PB). The common secret is determined on the basis of the first private key and the second public key, and the properties of the cryptography system are such that the common secret can be determined on the basis of the second private key and the first public key. An encryption key, based on the common secret, is determined for encryption of data (M), and the data is encrypted on the basis of the encryption key, wherein the step of encrypting data includes an exclusive or (XOR) operation.

Methods for performing a fast read-only memory (ROM) test are disclosed. In the first method, a signature is generated by performing a first set of N read operations utilizing an extended read-cycle, followed by a second set of N read operations utilizing an at-speed read-cycle, where N is an integer greater than or equal to 2. The retrieved data is combined using modulo addition and subtraction operations and stored in a signature register. In the second, a signature is generated by performing two read operations utilizing an extended read-cycle, followed by two read operations utilizing an at-speed read-cycle. The retrieved data is combined using exclusive OR (XOR) operations and stored in a signature register. The final signature is compared to a predetermined value to determine if any errors were detected. Both methods provide a robust test capable of detecting various ROM errors while minimizing test time and complexity.

The application discloses a memory data management method, an electronic device, a storage medium and a program product, relates to the technical field of storage, and comprises the following steps: realizing memory data management based on a native memory management mechanism and a page fault exception mechanism, processing the physical address of to-be-encrypted data by using a first key through step-by-step encryption, performing exclusive or operation on the obtained first ciphertext and the to-be-encrypted data, and storing the obtained second ciphertext into a red-black tree in a memory space, so that the encryption range is expanded, the data security is improved, the memory space and the red-black tree are fully utilized, and the addition, deletion and modification performance is improved. The target second ciphertext to be migrated is further encrypted and written into a swap area file. The method is realized by using pure software and does not depend on specific hardware devices. The technical problems of poor compatibility, high cost, being not conducive to large-scale application and great influence on system performance are solved, the technical effects of good compatibility, reduced cost, convenience for large-scale application and reduced influence on system performance are achieved.

A system and method for a secret-sharing encoding and decoding using exclusive OR (XOR) operations. A first apparatus includes a data splitting circuit to receive a secret and generate first, second, third, and fourth secret segments based on the secret and a secret share encoding circuit to generate first, second, third, and fourth secret shares by application of XOR operations to the first, second, third, and fourth secret segments. A second apparatus includes a secret share decoding circuit to receive first, second, third, and fourth secret shares and generate first, second, third, and fourth secret segments by application of an XOR operation to share encoded data of the first, second, third, and fourth secret shares, and a data aggregating circuit to: receive the first, second, third, and fourth secret segments; and recreate a secret by combining the first, second, third, and fourth secret segments.

Methods, error correction circuits, and circuit modules using error correction circuits are provided for performing co-bit calculations for error correction by means of circuit complexity reduction. Methods and related devices for co-bit computations for error correction by means of circuit complexity reduction are provided. The method comprises: in an error correction circuit using a predetermined error correction code, configuring a first group of XOR operational circuits in a plurality of XOR operational circuits corresponding to a predetermined codeword length, rather than all XOR operational circuits in the plurality of XOR operational circuits, so as to reduce the circuit complexity of the error correction circuit and improve the error correction efficiency of the error correction circuit. Wherein the first set of XOR operational circuits may be a set of optimized XOR operational circuits implemented based on co-located bit coverage reduction; and performing the co-bit calculation using the first set of XOR operational circuits for error correction corresponding to a shorter codeword length, where a smaller XOR operand and a shorter critical path length can be achieved.

The invention discloses a binary MDS array code structure with high erasure correction performance and a decoding method, and the decoding method achieves the rapid calculation of a syndrome vector through an optimized scheduling algorithm, only needs the exclusive or and cyclic shift operation, reduces the calculation complexity to a linear level O (n), and remarkably improves the data recovery speed. Compared with a traditional RS code and an existing array code, high reliability is guaranteed, the technical problem that storage efficiency and calculation complexity are difficult to consider at the same time is solved, and the method is suitable for large-scale distributed storage scenes such as cloud computing and artificial intelligence training. According to the binary MDS array code structure with the high erasure performance and the decoding method, the fault-tolerant capability is improved to five-node failure, and the high-reliability storage requirement is met; the decoding calculation complexity is obviously reduced, and only xor and shift operations are needed; the storage efficiency reaches the upper bound of the MDS theory, and the storage cost is reduced; and efficient data recovery is realized under the configuration that the code length n is equal to 11 and the redundancy r is equal to 5.

The present invention relates to the technical field of satellite remote control information processing, and particularly relates to a method, system, storage medium and electronic device for batch generating remote control instructions of a satellite. The method includes: respectively determining the fixed characters of each four-byte basic instruction code; splicing any four-byte basic instruction code and the fixed characters corresponding to the four-byte basic instruction code to obtain the instruction valid data corresponding to the four-byte basic instruction code, performing exclusive OR and parity check on the instruction valid data corresponding to the four-byte basic instruction code, generating two-byte parity check codes corresponding to the four-byte basic instruction code, and performing splicing to obtain the valid test instruction corresponding to the four-byte basic instruction code until the valid test instructions corresponding to each four-byte basic instruction code are obtained. It can batch generate valid test instructions, greatly improving the efficiency of instruction generation and also solving the problem of instruction version control caused by frequent changes in the technical state.

The present application relates to a kind of program-controlled resistance card and its program-controlled resistor smooth control method, device, wherein the method includes obtaining the resistance card coding combination corresponding to current resistance value and target resistance value;Difference mask is calculated by exclusive or operation, and the relay set to be changed is identified;Based on the strategy of greedy algorithm, in the form of successive single-step switching, the relay that makes instantaneous resistance value closest to target value is selected from the set identified by difference mask and is operated;Switching and state updating are iteratively executed until difference mask is zero;Finally, switching completion signal is output.The device includes state acquisition, difference analysis, switching decision and driving execution module, and through the orderly single-step relay switching control, smooth transition in the resistance value change process is realized, the extreme state such as open circuit or short circuit is effectively avoided, the switching precision and system reliability are significantly improved, and it is suitable for precision test measurement and automation control field.

The invention discloses an error correction coding method and device of a memory bank, electronic equipment and a storage medium, and relates to the technical field of error correction coding in a memory data reading and transmission process. According to the method, a 12-bit first check bit is generated based on a 12-bit first data bit and a reconstructed parity check matrix, and the reconstructed parity check matrix unifies the data column weight of the first data bit as 6 and the check column weight as 1; arranging the first data bits and the first check bits according to an alternating sequence to generate interleaving code words; splitting the interleaved code word into a second data bit and a second check bit, and calculating according to the second data bit and the reconstructed parity check matrix to obtain a third check bit; performing XOR operation on the second check bit and the third check bit to obtain a syndrome; and according to the syndrome and a preset combined syndrome rule table, performing a correction operation to obtain a corrected first data bit, thereby solving the problem of errors of multiple adjacent bit data in a data transmission process, and reducing the complexity and delay of a coding and decoding module.

The application relates to the technical field of manufacturing data processing, and discloses a production business data processing system for a discrete manufacturing workshop, which comprises the following modules: an asynchronous data acquisition module which collects asynchronous event pulse sequences of discrete execution nodes; a mapping transformation module which establishes an addressing mapping relationship between an event source and a memory logic bit plane and generates an original differential bit map; a bit map filtering module which uses the self-reflection principle of exclusive or logic to pair up logical flip signals, filters out the jitter interference of signal edges to generate a net value differential bit plane; and a state synchronization processing module which implements in-situ flip update of a state global bit map through address offset addressing according to a bit identifier. Through the bit map differential synchronization mechanism, the application realizes asynchronous state update without transaction lock constraint, alleviates the calculation blockage caused by high-frequency pulse impact, and enhances the real-time performance and stability of system data throughput.

The invention provides a method and a system for realizing AES (Advanced Encryption Standard) based on an FPGA (Field Programmable Gate Array), and relates to the field of channel transmission encryption and decryption, the method comprises the following steps: a plaintext is subjected to byte replacement, row shift, column mixing and round key addition circulation (N-1) rounds based on the FPGA, the Nth round is subjected to byte replacement, row shift and round key addition to obtain a ciphertext, and the number N of circulation rounds is designed according to the length of a key. The byte replacement comprises the following steps of: storing a byte lookup table by using an RAM (Random Access Memory) in an FPGA chip, and mapping a new byte in the lookup table according to each byte of the state equation to replace an original byte; the row shifting comprises the step of respectively circularly shifting the second row, the third row and the fourth row of the 4 * 4 state equation leftwards by 1, 2 and 3 bytes; column mixing comprises the following steps: left-multiplying a matrix of the state equation by a fixed matrix; the round key addition comprises the steps that the state equation and the round key are subjected to bitwise exclusive OR, a new state equation is obtained, and the round key is obtained through key expansion. According to the invention, the AES can be realized on the FPGA with fewer logic resources.

The embodiment of the invention provides a program compiling method and device.The method comprises the steps that a target source code is obtained, the target source code is compiled into a first intermediate representation, and a first instruction in the first intermediate representation has the capacity of storing first target data to a first target address in an encrypted memory of a trusted execution environment; adding a second intermediate representation to the first intermediate representation, the second intermediate representation being used for applying an XOR operation to the first target data through a randomly generated first random number to obtain first modified data, and storing the first random number to a target area in the encrypted memory; the first modification data replaces the first target data based on the first instruction; and generating a target machine code based on the first intermediate representation after the second intermediate representation is added.

The present invention discloses a secure pseudo-random number generator and method for high throughput of FPGA. The solution of the present invention is based on FPGA, and designs a 12-round permutation function and its module. In each round, a series of linear and non-linear operations are performed to fully scramble the input data; a round constant generator of a non-linear feedback shift register is designed, and exclusive OR operations are performed with data at specific positions; a counter and a logic circuit are set to optimize the processing of round constants to increase non-linear changes; a time threshold mechanism is set to re-seed operations regularly. The present invention significantly reduces and saves hardware resources, while also improving data randomness and anti-attack capabilities, improving the utilization rate of round constant storage resources, realizing high-throughput, efficient, and highly random pseudo-random number generation, achieving a balance between security and performance, improving efficiency, unpredictability, and hardware resource utilization rate, ensuring randomness and security during long-term operation.

The invention relates to a gating signal adjusting method, electronic equipment, a storage medium and a product, and the method comprises the steps: generating a target leading output signal based on a read enable signal; the target preamble output signal is a preamble output signal of which the data strobe signal DQS period number captured in an effective window reaches a DQS period number threshold value; based on the target leading output signal, respectively performing gating fine tuning on a leading gating path and a trailing gating path through a logic circuit to obtain a leading gating signal and a trailing gating signal; the rising edge of the leading gate control signal is aligned with the first rising edge of a leading section of the DQS, and the rising edge of the trailing gate control signal is aligned with the last rising edge of a trailing section of the DQS; and performing exclusive-or operation on the leading gate control signal and the trailing gate control signal to obtain a target gate control signal.

The invention relates to a key detection jitter removal implementation method. A key detection jitter removal system is constructed; according to the constructed key detection jitter removal system, a counting controller, a counter, a judgment module and a control module are connected in sequence, the counting controller is used for carrying out XOR operation on a key input signal and a jitter removal output signal, the counter is used for outputting a count value, and the judgment module is used for judging whether the count reaches a threshold value or not; the control module is used for negating the de-jitter output signal or keeping the de-jitter output signal; setting a signal and a de-jitter method; and inputting the key input into the key detection and jitter removal system, thereby realizing key detection and jitter removal. According to the simple key detection jitter removal method realized by adopting the FPGA, the jitter when the key is pressed down can be eliminated, the jitter when the key is lifted can also be eliminated, and the configuration is flexible. And meanwhile, the jitter detection time can be flexibly controlled by configuring a counter value.

The present invention provides an SRAM PUF key extraction method based on correlation judgment, comprising: an initial registration phase: powering on the SRAM, configuring and initializing variables; calculating the exclusive OR of a data block and its cyclic shifts of different points to obtain the number of cyclic shift points and the number of negatively correlated bits when the maximum negative correlation occurs; selecting N valid data blocks whose maximum negatively correlated bit numbers are greater than a set threshold; using N bits of hidden random numbers to control whether the valid data blocks are cyclically shifted according to the number of their maximum negatively correlated cyclic shift points; linearly encoding a randomly generated PUF output random number; performing an exclusive OR operation on the encoding result and the hidden random number to obtain auxiliary data; a reconstruction phase: powering on the SRAM, initializing variables, and obtaining a valid data block based on the auxiliary data selection; restoring an approximate random number of the hidden random number using the valid data block and the auxiliary data; performing an exclusive OR operation on the approximate random number and the auxiliary data to obtain a codeword before error correction; and performing linear encoding on the codeword to correct errors and restore the PUF output random number.

A communication device has a control section that generates a code word obtained by encoding information bits using an extended polar code that applies a stop of polarization achieved by addition of an XOR (Exclusive OR) operation and deletion based on the XOR operation, and a transmission section that transmits the code word to another communication device.

The invention discloses a data processing method and device, equipment and a storage medium, and relates to the technical field of data security storage, in the method, on one hand, in the encoding process, a first check block is considered, that is, not only is group division performed on a first sub-data block, but also group division is performed on the first check block, on the other hand, when a third check block is generated, group division is performed on a second sub-data block; for one of the second check blocks, the intermediate data block subjected to the exclusive-or operation with the second check block is not obtained based on the first check block corresponding to the second check block. On the basis of the two aspects, at least part of the finally obtained third check blocks comprise the first check blocks, and the first check blocks and the second check blocks obtained on the basis of the same coding function are not included in the same third check blocks. Therefore, when a single data block and a single check block are recovered, all the first sub-data blocks and all the second sub-data blocks do not need to be read, so that bandwidth consumption can be reduced, and the problem that in some technologies, the recovery bandwidth consumption of the check block is large can be solved.

A test device for a memory device includes a first exclusive OR (XOR) gate configured to output a first operation signal by performing an XOR operation between a clock signal and an output signal output from the memory device, an oscillator configured to output an oscillation signal, and an output circuit configured to determine a period of the oscillation signal. The output circuit may be configured to count a number of rising edges of the oscillation signal while the first operation signal is maintained at a high level, and determine an access time of the memory device based on the counted number of the rising edges, and a period of the oscillation signal.

The invention discloses a high-throughput true random number generator based on MUX latches, which comprises an entropy source circuit, a sampling circuit and a post-processing circuit, and is characterized in that the entropy source circuit comprises two groups of MUX latch circuits, and each group of MUX latch circuits comprises i-level MUX latch units; the D flip-flop is used for sampling the output in each stage of MUX latch unit; the post-treatment consists of an exclusive or chain. According to the method, the jitter and the metastable state are extracted at the same time under low hardware overhead, the high throughput rate is output, and good randomness and robustness are achieved.

The present invention discloses an encrypted computer system based on double memory exclusive OR and a bus encryption method. The system includes a processor CPU, an encryption controller CC, a key memory K, an encrypted data memory M, an unencrypted data memory N, and other peripherals O; wherein, the key memory K and the encrypted data memory M are respectively connected to the address bus of the CPU through the encryption controller CC; the data bus of the key memory K is connected to the data bus of the CPU through the encryption controller CC; the data bus of the key memory K and the data bus of the encrypted data memory M are connected to the data bus of the CPU through the relay of the encryption controller CC; the encryption controller CC sets the address space of the key memory K and its connection mode with the data bus of the CPU according to its own state; in the initial state, the addresses of the memory K and the memory M are set to be different; in the running state, the key memory K and the encrypted data memory M are set to have the same memory address range.

The invention belongs to the field of quantum security multi-party computing, and discloses a verifiable quantum security multi-party XOR protocol based on super-dense coding. According to the preprocessing stage, for n participants Pj and two classical bits held by each participant, P0 obtains specific aggregation information of the classical bits of each participant through a super-dense coding means under the condition that only n quantum bits are transmitted, and meanwhile it is ensured that P0 cannot obtain the part, which is not authorized to check, of the bits held by each participant, so that the P0 is not allowed to check the part of the classical bits of each participant; through the method, the communication overhead in multi-party computing is greatly reduced. In the calculation stage, real input is hidden by using the secret key and the auxiliary value generated in the preprocessing stage, and exclusive-or operation is carried out under the condition that privacy input is not leaked. The protocol does not need the participation of a trusted third party, the trust dependence is eliminated, and decentralized security is realized; quantum state input is supported, and future quantum computing threats are defended; whether someone maliciously tampers the calculated value or not in the exclusive OR seeking process can be verified, and the method is suitable for sensitive scenes such as privacy calculation and conjoint analysis.

An error correction decoding device is configured to decode a multi-valued modulation symbol having a dimension of D and a number of bits per dimension of M (M is an integer of 2 or more) from each of D (D is an integer of 1 or more) pulse amplitude modulation symbols. An error correction decoding device is provided with: a soft decision unit (1) that acquires each pulse amplitude modulation symbol from a communication symbol sequence in which D pulse amplitude modulation symbols are arranged, calculates, on the basis of each pulse amplitude modulation symbol, a positive or negative first hard decision bit indicating the logarithmic posterior probability ratio of each of M bits included in a multi-valued modulation symbol, and outputs the calculated first hard decision bit to a second hard decision bit that indicates the logarithmic posterior probability ratio of each of the M bits included in the multi-valued modulation symbol; calculating an absolute value of each logarithmic posterior probability ratio as a first reliability; and an exclusive-OR calculation unit (2) that calculates the exclusive-OR of the D * M first hard decision bits calculated by the soft decision unit (1). Furthermore, the error correction decoding device is provided with: a reliability selection unit (3) which compares the D * M first reliability degrees calculated by the soft decision unit (1) with each other, selects one first reliability degree from among the D * M first reliability degrees on the basis of the result of the comparison, and outputs the one first reliability degree as a second reliability degree; and a soft decision error correction decoding unit (4) that performs soft decision error correction decoding on the result of the exclusive OR operation performed by the exclusive OR operation unit (2) and the second reliability.

An error correction decoding device includes processing circuitry configured to; acquire each of the pulse amplitude modulation symbols from a communication symbol sequence, calculate a first hard decision bit indicating positive and negative of a log posterior probability ratio of each of M bits, and calculate an absolute value of each of log posterior probability ratios as a first reliability; operate an exclusive OR of D×M first hard decision bits having been calculated; perform comparison of D×M first reliabilities having been calculated with each other, select one first reliability from the D×M first reliabilities on a basis of a result of the comparison, and output the one first reliability as a second reliability; and perform soft decision error correction decoding on an operation result of the exclusive OR and the second reliability.

A system and method for a secret-sharing encoding and decoding using exclusive OR (XOR) operations. A first apparatus includes a data splitting circuit to receive a secret and generate first, second, third, and fourth secret segments based on the secret and a secret share encoding circuit to generate first, second, third, and fourth secret shares by application of XOR operations to the first, second, third, and fourth secret segments. A second apparatus includes a secret share decoding circuit to receive first, second, third, and fourth secret shares and generate first, second, third, and fourth secret segments by application of an XOR operation to share encoded data of the first, second, third, and fourth secret shares, and a data aggregating circuit to: receive the first, second, third, and fourth secret segments; and recreate a secret by combining the first, second, third, and fourth secret segments.