The invention provides a
Verilog HDL code automatic generation method based on a constant multiplier
directed graph, belongs to the technical field of computers, solves the problem that a traditional constant multiplier optimization method is difficult to cope with large-scale scene calculation, and comprises the steps that 1, adjacent matrix modeling is conducted on
directed graph sets {DAG1 and DAG2} corresponding to constant sets {c1, c2,...}, and a matrix set MatrixList is obtained; step 2, splitting the
matrix group MatrixList into a left matrix MatrixL and a right matrix MatrixR; 3, the bit width Width of an input
signal x, the left matrix MatrixL and the right matrix MatrixR are input into
Verilog HDL to generate a model to obtain corresponding
Verilog HDL codes, constant multiplication under the optimal resource condition is achieved, constant multiplication comprises SCM, MCM, TmSCM and TmMCM, SCM is single constant multiplication, MCM is multi-constant multiplication, TmSCM is
time division multiplexing single constant multiplication, and TmMCM is
time division multiplexing multi-constant multiplication.