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2 results about "Matrix entry" patented technology

Dimension of Matrix. The dimensions of a matrix refer to the number of rows and columns of a given matrix. By convention the dimension of a a matrix are given by number of rows • number of columns One way that some people remember that the notation for matrix dimensions is rows by columns (Rather than columns by rows) is by recalling a once popular-soda:

A data processing method, device and electronic equipment

The embodiment of the application provides a data processing method, device and electronic equipment, which can reconstruct a matrix of any data type and size into a legal input of a matrix operation unit, thereby expanding the business scenario of the matrix operation unit and improving the operation efficiency. The method comprises the following steps: obtaining a first matrix. The number of bits occupied by each element in the first matrix is greater than the requirement of the matrix operation unit on input data. The first matrix is split into a plurality of sub-matrices. Wherein, the element of the i-th row and the j-th column of the first matrix is split by a bit to form the element of the i-th row and the j-th column of each sub-matrix, i is less than or equal to the number of rows of the first matrix, and j is less than or equal to the number of columns of the first matrix. The number of bits occupied by each element in the sub-matrix is less than or equal to the requirement of the matrix operation unit on input data. The plurality of sub-matrices are input into the matrix operation unit.
Owner:HUAWEI TECH CO LTD

Verilog HDL code automatic generation method based on constant multiplier directed graph

The invention provides a Verilog HDL code automatic generation method based on a constant multiplier directed graph, belongs to the technical field of computers, solves the problem that a traditional constant multiplier optimization method is difficult to cope with large-scale scene calculation, and comprises the steps that 1, adjacent matrix modeling is conducted on directed graph sets {DAG1 and DAG2} corresponding to constant sets {c1, c2,...}, and a matrix set MatrixList is obtained; step 2, splitting the matrix group MatrixList into a left matrix MatrixL and a right matrix MatrixR; 3, the bit width Width of an input signal x, the left matrix MatrixL and the right matrix MatrixR are input into Verilog HDL to generate a model to obtain corresponding Verilog HDL codes, constant multiplication under the optimal resource condition is achieved, constant multiplication comprises SCM, MCM, TmSCM and TmMCM, SCM is single constant multiplication, MCM is multi-constant multiplication, TmSCM is time division multiplexing single constant multiplication, and TmMCM is time division multiplexing multi-constant multiplication.
Owner:HARBIN INST OF TECH