107 results about "Generator matrix" patented technology

The invention discloses a malicious instruction detection method and system fusing self-supervised learning and a knowledge graph. The method comprises the steps of obtaining user instruction data and compliance labels, constructing an adversarial sample generation matrix, and generating an adversarial sample library through hierarchical variation and compliance correction; inputting the original instruction and the adversarial sample into a multi-modal detection model, wherein the model comprises a dual-channel encoder and a dynamic knowledge graph module; through a self-supervised comparison loss function optimization model, positive samples need to meet semantic and attack feature similarity threshold requirements, and negative samples are violation instructions; inputting a to-be-detected instruction into the trained model, extracting features, performing multi-hop reasoning on the features and the knowledge graph, and calculating a risk score; and when a malicious instruction is detected, generating a disposal strategy and updating the knowledge graph node. Through fusion of self-supervised learning and the dynamic knowledge graph, accurate detection is realized, the generalization ability and robustness of the model are enhanced, and the detection precision is improved.

The embodiment of the invention provides a coding and decoding method and device and a storage medium, relates to the technical field of communication, and can reduce the storage space requirement of coding. The method comprises the steps that a parity check matrix is determined, the dimension of the parity check matrix is determined based on the dimension of a binary extension matrix, the binary extension matrix is obtained by hashing an index matrix based on a lifting factor, and the lifting factor is determined based on the order of a binary basic matrix, an information bit sequence and a non-binary low-density parity check code NB-LDPC code; and according to the parity check matrix or a generation matrix corresponding to the parity check matrix, performing NB-LDPC coding on the information bit sequence to obtain a coding sequence.

Provided are an encoding method and apparatus, a decoding method and apparatus, and a storage medium. The encoding method comprises: determining a parity check matrix, wherein the dimension of the parity check matrix is determined on the basis of the dimension of a binary extended matrix, the binary extended matrix is obtained by hashing an exponential matrix on the basis of a lifting factor, and the lifting factor is determined on the basis of a binary fundamental matrix, an information bit sequence, and the order of a non-binary low density parity check code (NB-LDPC); and performing NB-LDPC encoding on the information bit sequence on the basis of the parity check matrix or a generator matrix corresponding to the parity check matrix, to obtain an encoding sequence.

Approaches in accordance with various embodiments provide for the processing of sparse matrices for mathematical and programmatic operations. In particular, various embodiments utilize a tiling approach that divides a sparse matrix into submatrices, many of which will include only zero-value entities. These empty tiles can be ignored, and only the tiles with non-zero entries processed, which reduces resource and time requirements for the processing. An indexing approach can be used for each entity that is a combination of the tile identifier and an offset value, which enables the values to be multiplied correctly against, for example, values of a dense matrix. The tiles can be processed in parallel and the results accumulated to generate a matrix product. The matrix product can then be passed to the next step in a process or operation, such as to a next layer in a deep neural network.

The invention discloses an inventory management system based on order data, and relates to the technical field of intelligent warehousing, and the system comprises a priority evaluation module which calculates the allocation weight and the inventory allocation priority score between warehouses based on an inventory gap list, and generates a QUBO matrix; and the inventory allocation module is used for carrying out global optimal solution search by adopting a quantum annealing algorithm based on the QUBO matrix, carrying out decoding through a coding rule, generating an initial inventory allocation instruction set, carrying out optimization by adopting an MIL, generating an optimal inventory allocation instruction and executing the optimal inventory allocation instruction. According to the method, global optimal solution search is carried out by adopting a quantum annealing algorithm, and secondary optimization is carried out in combination with MILP, so that the overall cost minimization is realized on the premise that the generated allocation instruction meets complex business constraints.

The invention relates to the technical field of pseudo-random binary sequence design, in particular to a parallel PRBS generation method and system for testing a multi-protocol high-speed serial transceiver, and the method comprises the steps: setting demand parameters of a pseudo-random binary sequence for testing the multi-protocol high-speed serial transceiver, and enabling the demand parameters to comprise an order, a bit number and a feedback polynomial; constructing a generator matrix for describing state transition of the linear feedback shift register according to the feedback polynomial; according to the bit number of the pseudo-random binary sequence, generating a mapping matrix of the pseudo-random binary sequence through the exponentiation of the generated matrix; based on the mapping matrix and the current beat linear feedback shift register state, outputting a pseudo-random binary sequence meeting the requirement parameters for testing the multi-protocol high-speed serial transceiver. According to the method, parallel generation of any PRBS can be supported, the PRBS parallel implementation logic configuration is simple, the hardware implementation complexity is low, the PRBS output throughput rate is high, and the design requirements of multi-protocol high-speed SerDes can be met.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

The application discloses a processing method and device for encoding and decoding. A sending end obtains basic parameters of an RM code and a plurality of information bits to be processed, determines a bit index set according to a predefined superposition ratio, a superposition mode and the basic parameters, encodes the plurality of information bits to be processed according to a preset encoding mode and the bit index set, and obtains a coded codeword. The preset encoding mode is determined by a Plotkin recursive structure or a corresponding generating matrix of a preset partial superposition. The coded codeword is modulated, the modulated signal is sent to a receiving end through a channel, so that the receiving end performs channel decoding on demodulated information through a preset decoding algorithm and outputs.

The present disclosure relates to a method, a computing device, a computing system, and a storage medium for generating an operator for tensor operations. The method includes: parsing input information for generating a matrix sequence; generating symbolic representation information for operations based on the generated matrix sequence and an input symbolic vector; converting the generated symbolic representation information into abstract syntax tree information or intermediate representation information; and generating assembly code for an operator for tensor operations based on basic description information included in the generated abstract syntax tree information and intermediate representation information. The present disclosure can make full use of the hardware performance of each processor, and can efficiently generate an operator library for high-performance tensor operations for a GPU.

The invention provides a visible light communication sending method, a receiving method and a visible light communication device, and the sending method comprises the steps: obtaining input information, and carrying out the filling processing of redundant bits when the information bit length of the input information is smaller than a preset required length; when the information bit length of the input information exceeds a preset required length, grouping the input information; grouping the generation matrix of the input information, and respectively storing the first row of data of each group in different addresses of a grouping register; the first row of data is shifted once in each clock cycle, information bits and check bits are generated, and LDPC codes are obtained; modulating the LDPC code to obtain a first modulation signal; performing digital-to-analog conversion on the first modulation signal to obtain a first analog voltage signal; sending the first analog voltage signal to an LED linear driving circuit to obtain a visible light signal; and sending the visible light signal to an optical signal receiving end. The transmission speed of visible light communication is improved, and the visible light communication process is more reliable.

The invention belongs to the technical field of telecommunication, and discloses a two-dimensional RS code encoding and decoding method for streaming media data transmission. The method comprises the following steps: dynamically setting a coding parameter set based on network state data and application service data; constructing a finite field I and a finite field II based on the coding parameter set; constructing a Vandermonde matrix inverse matrix set based on the finite field 2; constructing an RS code generation matrix based on the finite field I, the finite field II and the Vandermonde matrix inverse matrix set; performing two-dimensional coding on the K original data packets based on an RS code generation matrix and a Vandermonde matrix inverse matrix set to generate R redundant data packets; the receiving end carries out decoding according to the received original data packets and the redundant data packets, and if the number of the received data packets is K, the K original data packets are directly recovered; if the V redundant data packets and the K-V original data packets are received, decoding recovery operation is carried out; according to the invention, accurate error correction and controllable fault tolerance of streaming media data transmission are realized.

The present invention discloses an order data-based inventory management system, which relates to the field of intelligent warehousing technology. The system includes a priority assessment module that calculates transfer weights and inventory transfer priority scores between warehouses based on an inventory gap list and generates a QUBO matrix. An inventory transfer module uses a quantum annealing algorithm to search for a global optimal solution based on the QUBO matrix, decodes the solution using encoding rules, generates an initial inventory transfer instruction set, and simultaneously optimizes the system using MILP to generate and execute the optimal inventory transfer instructions. By using a quantum annealing algorithm to search for a global optimal solution and combining it with MILP for secondary optimization, the present invention ensures that the generated transfer instructions minimize overall costs while meeting complex business constraints.

The present invention relates to the field of electronic communication technologies, and more specifically, to a method for generating quasi-cyclic hyperelliptic codes. The method includes: S1. Selecting a hyperelliptic curve according to given coding parameters; S2. Generating a divisor on the corresponding curve according to the given coding parameters; S3. Calculating a compact generator matrix by using the hyperelliptic curve and the divisor. The present invention can generate quasi-cyclic codes or cyclic codes of any length by using hyperelliptic curves, and obtain the algebraic geometric expression form of the generated quasi-cyclic codes and the expression form of the compact generator matrix. The present invention establishes a connection between hyperelliptic curves and quasi-cyclic codes, and solves part of the problems of representing quasi-cyclic codes and cyclic codes in algebraic geometric forms. The hyperelliptic quasi-cyclic codes generated by the present invention have a clear algebraic geometric structure, and this structure can be used for decoding methods unique to algebraic geometric codes such as list decoding, thereby improving the error correction ability of channel coding and reducing the storage space of the coding matrix.

An error correction circuit for a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates parity data based on main data using an error correction code represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device, generates different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when there is one in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page.

A coding method and apparatus are provided to provide a uniform coding method for ultra short codes. The method is as follows: obtaining, by a transmit end, to-be-coded information bits; performing, by the transmit end, PC-polar coding on the to-be-coded information bits based on first constructor parameters, to obtain a coded bit sequence; and sending the coded bit sequence, where a check equation of the first constructor parameters include a first element representing a check-required information bit position and a second element representing a check bit position, the first element corresponds to a first vector in a generator matrix for PC-polar codes, the second element corresponds to a second vector in the generator matrix, and if a first Hamming weight of the first vector is the same as a second Hamming weight of the second vector, a third Hamming weight of an addition modulo 2 vector is greater than the first Hamming weight and greater than the second Hamming weight, or if the first Hamming weight is different from the second Hamming weight, the third Hamming weight is greater than a smaller one of the first Hamming weight and the second Hamming weight.

The application discloses a data encryption method, and belongs to the technical field of text encryption. First, the text data is converted into binary code and split into odd and even bit sequences, and corresponding matrices are constructed respectively; the odd and even shift matrices are obtained by generating matrix row / column state bits, calculating shift amount and performing cyclic shift; then the rows and columns of the shift matrix are converted into decimal numerical vectors, combined with fractal offset key vectors for encryption, and four types of encryption matrices of odd row, odd column, even row and even column are generated; the same type of matrices are subjected to XOR processing, and the confusion value is generated based on the odd part and the even part related value, so that the mixed enhanced encryption matrix is obtained; finally, the two types of enhanced matrices are restored into sequences and reorganized according to the odd and even bits, and the ciphertext is output. Through the multilevel processing of bit splitting, matrix shifting, fractal key encryption and XOR confusion, the complexity and anti-cracking ability of data encryption are significantly improved, and the safety of data transmission and storage is ensured.

The embodiment of the invention provides a data coding method, which comprises the following steps: acquiring a target matrix which is a check matrix or a generator matrix and is a binary matrix representing data units of a finite field 2a on a polynomial ring, the polynomial corresponding to the polynomial ring is an irreducible polynomial of which the highest number of times is not greater than a; according to the target matrix, encoding a data block to obtain an encoding result; wherein the coding result is used as a redundant data block of the data block; or the coding result is a recovery result of the data block of the node where the coding result is located. In the embodiment of the invention, one irreducible polynomial can be selected as the polynomial corresponding to the polynomial ring, so that the data unit of the finite field 2a can be converted to the corresponding polynomial ring to be expressed, and then the exclusive or operation equivalent to the multiplication operation can be carried out through the data expressed on the basis of the polynomial ring. And the calculation overhead is reduced.

The invention provides a scrambling code generation method and device, equipment, a medium and a product, and relates to the technical field of communication, and the method comprises the steps: obtaining a target scrambling code length, selecting the first n rows in a pre-constructed first scrambling code generation matrix as a second scrambling code generation matrix based on the target scrambling code length, and enabling n to be equal to the target scrambling code length; generating a scrambling code calculation result based on the second scrambling code generation matrix and the initialization value of each register; wherein each row of the first scrambling code generation matrix reflects the corresponding relation between each bit of scrambling code and the initialization value of the register. The method does not need to wait for a plurality of clock cycles to generate the multi-digit scrambling code, and can improve the scrambling code generation efficiency.

A memory device and an operating method of operating the memory device are provided. The method includes: obtaining, by a memory controller, channel selection information indicating positions of data bits and shaping parity bits; generating, by the memory controller, an alignment vector by aligning the data bits and the shaped parity bits having an arbitrary value based on the channel selection information; generating, by the memory controller, second LLR information of the target vector based on the first LLR information related to the alignment vector; determining, by the memory controller, a value of a shaped parity based on the target vector and the second LLR information; performing, by the memory controller, an update operation on the shaped parity based on the determined value; and generating, by the memory controller after performing the update operation, a codeword with respect to the input data based on a first matrix multiplication calculation of the target vector and the first generated matrix.

A coding method and apparatus are provided. The method includes: coding an information bit by using a preset generator matrix of a systematic (U|U+V)-code to obtain a codeword of a systematic code. The preset generator matrix of the systematic (U|U+V)-code includes a first identity sub-matrix of a U code and a second identity sub-matrix of a V code. A plurality of elements in a same column as the first identity sub-matrix are all 0. A plurality of elements in a same column as the second identity sub-matrix are all 0.

The application relates to the field of high-performance computing and computing power optimization, and relates to a method for accelerating triangular matrix multiplication based on an atlas 800 platform, which comprises the following steps: cutting a result matrix into multiple task blocks, and presetting an equal division strategy based on the multiple task blocks; generating a mask matrix on a vector calculation unit, and storing the mask matrix back to a global memory; reading the matrix and the mask matrix from the global memory, implementing triangular masking of the matrix by using the vector calculation unit, and obtaining a triangular matrix A after triangular masking; based on the triangular matrix A after triangular masking, calling a cube calculation unit to complete matrix multiplication operation of all the task blocks according to the preset equal division strategy, and obtaining a result matrix. The mix method combining the vector calculation unit and the cube calculation unit is used to complete the triangular matrix multiplication, the calculation efficiency of the triangular matrix multiplication on the NPU is improved, the computing power of the Huawei atlas 800 NPU can be fully utilized, the triangular matrix multiplication calculation is accelerated, and computing power support is provided for the fields of deep learning and scientific calculation.

In accordance with an example aspect of the present disclosure, data is encoded or decoded using a polar code, where a generation matrix of the polar code includes rows of a polar transformation matrix formula (I), where is an N * N-bit inversion matrix, where N = 2n is a non-negative integer, and where formula (II) is an n-fold Kronecker product of formula (III), where N = 2n is a non-negative integer. The index set of the rows forming the polarization transformation matrix of the generating matrix is set A.

Disclosed are a method for generating matrix index information for a target matrix including a sparse matrix, and a method for processing a matrix by using matrix index information. The disclosed matrix index information generation method comprises the steps of: identifying the presence or absence of a non-zero element in each row or column of a target matrix, and generating a first bitstring including information on the presence or absence of the non-zero element in each row or column of the target matrix.

The present invention provides an encoding and decoding method for the distributed multi - user key sharing problem under strong privacy conditions. The method includes the following steps: Step 1: Initialize an N×(∑ k∈[K] R k +N) generating matrix V according to the access structure and the key information rate array; Step 2: Obtain the corresponding K(K - 1) row index sets according to the access structure and the key information rate array, and extract K sub - matrices from the generating matrix V by these sets. The strong privacy condition is equivalent to the full rank of each sub - matrix; Step 3: Calculate the determinants according to each sub - matrix, multiply them to obtain a polynomial, find a set of feasible solutions that make the polynomial not equal to 0, then set the remaining variables in the generating matrix V to 0, then extract the decoding method from the generating matrix V, and finally perform Gaussian elimination on the generating matrix V to obtain the encoding method. The method of the present invention can be applied to any access structure and can achieve the optimal key information rate.

This application provides a Gaussian elimination method and apparatus with look-ahead operation, comprising: acquiring a first input vector and a second input vector for inputting a target double-column elimination unit within one clock cycle; when the target double-column elimination unit is a first-level double-column elimination unit, the two input vectors are read from the generator matrix; when the target double-column elimination unit is a subsequent-level double-column elimination unit, the two input vectors are the output of the previous-level double-column elimination unit; calculating candidate vectors based on the two input vectors according to the current initialization state of the target double-column elimination unit; determining the output of the target double-column elimination unit based on the first input vector, the second input vector, and / or the candidate vectors according to the current initialization state of the target double-column elimination unit, and updating the initialization state of the target double-column elimination unit. This method enables the processing of two columns of data from the generator matrix using a double-column elimination unit within one clock cycle, reducing processing time and resource consumption, and improving processing efficiency.

This invention relates to an erasure coding method and system based on two-layer optimization. The method includes: obtaining storage parameters of the data to be stored; constructing an initial generator matrix structure and a reference table for characterizing the bit-level characteristics of elements; constructing a two-layer optimization model and using the two-layer optimization model to collaboratively optimize the initial generator matrix structure; the two-layer optimization model includes: an upper-layer optimization model configured to adjust the structural distribution of the generator matrix; and a lower-layer optimization model configured to schedule the bit-level operation paths after the generator matrix expansion based on the reference table and calculate the actual bit-level computational overhead; feeding back the bit-level computational overhead of the lower-layer optimization model to the upper-layer optimization model; and encoding the data to be stored based on the comprehensive evaluation result of the algebraic characteristics and the bit-level computational overhead. This invention achieves the collaborative unification of the generator matrix structure and XOR scheduling optimization through the two-layer optimization model, improving the coding rationality, practicality, and throughput.

The present invention discloses a puncturing method and system based on recursive list decoding of RM codes. The method includes the following steps: S1. Determine a puncturing order set based on the column weights of RM codes; S2. Select a puncturing index from the puncturing order set to obtain a puncturing set F, puncture the bit positions of the puncturing indexes in the puncturing set F, and set the log-likelihood ratio at the puncturing positions to zero; S3. Input the punctured information bits and the unpunctured information bits into the decoder in the original order; S4. Decode the RM code through the decoder using a recursive structure, and select the one with the minimum path metric value from the decoding paths as the output result. The present invention selects the puncturing order according to the column weights of the generating matrix G of RM codes, and has better error performance, higher information transmission capacity, and higher information transmission efficiency in the case of a large number of puncturing.

The present invention proposes a method for constructing a locally recoverable code, which includes the following steps: initializing parameters; constructing and partitioning a Vandermonde matrix; constructing a summation matrix L; constructing a generator matrix G; and obtaining the construction result of the locally recoverable code. The present invention deploys a local check block, a global check block linearly associated with it, and an original data block in each cluster. This achieves the advantage of only needing to read other nodes in a cluster when recovering a node in the cluster, thus avoiding cross-cluster bandwidth. Furthermore, the generator matrix is ​​constructed by constructing a compression matrix and then a summation matrix, so that the generated local check block can be represented as a linear combination of the global check block and the original data block in the same cluster. This avoids the defect of needing to read all original data blocks when repairing the global check block, effectively improving data recovery efficiency.

This application relates to a decoding path determination method, apparatus, computer device, and storage medium. The method includes: constructing a symbol-based equivalent directed graph based on a polar code generator matrix; obtaining at least two initial symbol synchronization sets based on the equivalent directed graph; optimizing each initial symbol synchronization set based on frozen symbols in each initial symbol synchronization set and information symbols in a preset set to obtain an optimized symbol synchronization set; and determining the target decoding path based on the optimized symbol synchronization set. This method optimizes the symbol enumeration order, improves path evaluation at each decoding level, and further optimizes the enumeration order of symbols in the optimized symbol synchronization set, resulting in a more accurate final target decoding path.

Methods, systems, and devices for wireless communication are described. A device may generate a set of shaped bits based on a plurality of information bit sequences, each information bit sequence of the plurality of information bit sequences being a respective stream of demultiplexed bit sequences, where the set of shaped bits is based on a quasi-cyclic graph code. The device may apply the bit mask sequence to a first information bit sequence of the plurality of information bit sequences to form a mask bit sequence based on the set of shaped bits and a generator matrix, a parity check matrix, or both associated with the quasi-cyclic graph code, and the device may transmit a message including the mask bit sequence.