69 results about "Generator matrix" patented technology

Approaches in accordance with various embodiments provide for the processing of sparse matrices for mathematical and programmatic operations. In particular, various embodiments utilize a tiling approach that divides a sparse matrix into submatrices, many of which will include only zero-value entities. These empty tiles can be ignored, and only the tiles with non-zero entries processed, which reduces resource and time requirements for the processing. An indexing approach can be used for each entity that is a combination of the tile identifier and an offset value, which enables the values to be multiplied correctly against, for example, values of a dense matrix. The tiles can be processed in parallel and the results accumulated to generate a matrix product. The matrix product can then be passed to the next step in a process or operation, such as to a next layer in a deep neural network.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

The application discloses a processing method and device for encoding and decoding. A sending end obtains basic parameters of an RM code and a plurality of information bits to be processed, determines a bit index set according to a predefined superposition ratio, a superposition mode and the basic parameters, encodes the plurality of information bits to be processed according to a preset encoding mode and the bit index set, and obtains a coded codeword. The preset encoding mode is determined by a Plotkin recursive structure or a corresponding generating matrix of a preset partial superposition. The coded codeword is modulated, the modulated signal is sent to a receiving end through a channel, so that the receiving end performs channel decoding on demodulated information through a preset decoding algorithm and outputs.

The invention provides a visible light communication sending method, a receiving method and a visible light communication device, and the sending method comprises the steps: obtaining input information, and carrying out the filling processing of redundant bits when the information bit length of the input information is smaller than a preset required length; when the information bit length of the input information exceeds a preset required length, grouping the input information; grouping the generation matrix of the input information, and respectively storing the first row of data of each group in different addresses of a grouping register; the first row of data is shifted once in each clock cycle, information bits and check bits are generated, and LDPC codes are obtained; modulating the LDPC code to obtain a first modulation signal; performing digital-to-analog conversion on the first modulation signal to obtain a first analog voltage signal; sending the first analog voltage signal to an LED linear driving circuit to obtain a visible light signal; and sending the visible light signal to an optical signal receiving end. The transmission speed of visible light communication is improved, and the visible light communication process is more reliable.

The invention belongs to the technical field of telecommunication, and discloses a two-dimensional RS code encoding and decoding method for streaming media data transmission. The method comprises the following steps: dynamically setting a coding parameter set based on network state data and application service data; constructing a finite field I and a finite field II based on the coding parameter set; constructing a Vandermonde matrix inverse matrix set based on the finite field 2; constructing an RS code generation matrix based on the finite field I, the finite field II and the Vandermonde matrix inverse matrix set; performing two-dimensional coding on the K original data packets based on an RS code generation matrix and a Vandermonde matrix inverse matrix set to generate R redundant data packets; the receiving end carries out decoding according to the received original data packets and the redundant data packets, and if the number of the received data packets is K, the K original data packets are directly recovered; if the V redundant data packets and the K-V original data packets are received, decoding recovery operation is carried out; according to the invention, accurate error correction and controllable fault tolerance of streaming media data transmission are realized.

An error correction circuit for a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates parity data based on main data using an error correction code represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device, generates different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when there is one in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page.

The application discloses a data encryption method, and belongs to the technical field of text encryption. First, the text data is converted into binary code and split into odd and even bit sequences, and corresponding matrices are constructed respectively; the odd and even shift matrices are obtained by generating matrix row / column state bits, calculating shift amount and performing cyclic shift; then the rows and columns of the shift matrix are converted into decimal numerical vectors, combined with fractal offset key vectors for encryption, and four types of encryption matrices of odd row, odd column, even row and even column are generated; the same type of matrices are subjected to XOR processing, and the confusion value is generated based on the odd part and the even part related value, so that the mixed enhanced encryption matrix is obtained; finally, the two types of enhanced matrices are restored into sequences and reorganized according to the odd and even bits, and the ciphertext is output. Through the multilevel processing of bit splitting, matrix shifting, fractal key encryption and XOR confusion, the complexity and anti-cracking ability of data encryption are significantly improved, and the safety of data transmission and storage is ensured.

The embodiment of the invention provides a data coding method, which comprises the following steps: acquiring a target matrix which is a check matrix or a generator matrix and is a binary matrix representing data units of a finite field 2a on a polynomial ring, the polynomial corresponding to the polynomial ring is an irreducible polynomial of which the highest number of times is not greater than a; according to the target matrix, encoding a data block to obtain an encoding result; wherein the coding result is used as a redundant data block of the data block; or the coding result is a recovery result of the data block of the node where the coding result is located. In the embodiment of the invention, one irreducible polynomial can be selected as the polynomial corresponding to the polynomial ring, so that the data unit of the finite field 2a can be converted to the corresponding polynomial ring to be expressed, and then the exclusive or operation equivalent to the multiplication operation can be carried out through the data expressed on the basis of the polynomial ring. And the calculation overhead is reduced.

The invention provides a scrambling code generation method and device, equipment, a medium and a product, and relates to the technical field of communication, and the method comprises the steps: obtaining a target scrambling code length, selecting the first n rows in a pre-constructed first scrambling code generation matrix as a second scrambling code generation matrix based on the target scrambling code length, and enabling n to be equal to the target scrambling code length; generating a scrambling code calculation result based on the second scrambling code generation matrix and the initialization value of each register; wherein each row of the first scrambling code generation matrix reflects the corresponding relation between each bit of scrambling code and the initialization value of the register. The method does not need to wait for a plurality of clock cycles to generate the multi-digit scrambling code, and can improve the scrambling code generation efficiency.

A memory device and an operating method of operating the memory device are provided. The method includes: obtaining, by a memory controller, channel selection information indicating positions of data bits and shaping parity bits; generating, by the memory controller, an alignment vector by aligning the data bits and the shaped parity bits having an arbitrary value based on the channel selection information; generating, by the memory controller, second LLR information of the target vector based on the first LLR information related to the alignment vector; determining, by the memory controller, a value of a shaped parity based on the target vector and the second LLR information; performing, by the memory controller, an update operation on the shaped parity based on the determined value; and generating, by the memory controller after performing the update operation, a codeword with respect to the input data based on a first matrix multiplication calculation of the target vector and the first generated matrix.

A coding method and apparatus are provided. The method includes: coding an information bit by using a preset generator matrix of a systematic (U|U+V)-code to obtain a codeword of a systematic code. The preset generator matrix of the systematic (U|U+V)-code includes a first identity sub-matrix of a U code and a second identity sub-matrix of a V code. A plurality of elements in a same column as the first identity sub-matrix are all 0. A plurality of elements in a same column as the second identity sub-matrix are all 0.

The application relates to the field of high-performance computing and computing power optimization, and relates to a method for accelerating triangular matrix multiplication based on an atlas 800 platform, which comprises the following steps: cutting a result matrix into multiple task blocks, and presetting an equal division strategy based on the multiple task blocks; generating a mask matrix on a vector calculation unit, and storing the mask matrix back to a global memory; reading the matrix and the mask matrix from the global memory, implementing triangular masking of the matrix by using the vector calculation unit, and obtaining a triangular matrix A after triangular masking; based on the triangular matrix A after triangular masking, calling a cube calculation unit to complete matrix multiplication operation of all the task blocks according to the preset equal division strategy, and obtaining a result matrix. The mix method combining the vector calculation unit and the cube calculation unit is used to complete the triangular matrix multiplication, the calculation efficiency of the triangular matrix multiplication on the NPU is improved, the computing power of the Huawei atlas 800 NPU can be fully utilized, the triangular matrix multiplication calculation is accelerated, and computing power support is provided for the fields of deep learning and scientific calculation.

In accordance with an example aspect of the present disclosure, data is encoded or decoded using a polar code, where a generation matrix of the polar code includes rows of a polar transformation matrix formula (I), where is an N * N-bit inversion matrix, where N = 2n is a non-negative integer, and where formula (II) is an n-fold Kronecker product of formula (III), where N = 2n is a non-negative integer. The index set of the rows forming the polarization transformation matrix of the generating matrix is set A.

This application provides a Gaussian elimination method and apparatus with look-ahead operation, comprising: acquiring a first input vector and a second input vector for inputting a target double-column elimination unit within one clock cycle; when the target double-column elimination unit is a first-level double-column elimination unit, the two input vectors are read from the generator matrix; when the target double-column elimination unit is a subsequent-level double-column elimination unit, the two input vectors are the output of the previous-level double-column elimination unit; calculating candidate vectors based on the two input vectors according to the current initialization state of the target double-column elimination unit; determining the output of the target double-column elimination unit based on the first input vector, the second input vector, and / or the candidate vectors according to the current initialization state of the target double-column elimination unit, and updating the initialization state of the target double-column elimination unit. This method enables the processing of two columns of data from the generator matrix using a double-column elimination unit within one clock cycle, reducing processing time and resource consumption, and improving processing efficiency.

This invention relates to an erasure coding method and system based on two-layer optimization. The method includes: obtaining storage parameters of the data to be stored; constructing an initial generator matrix structure and a reference table for characterizing the bit-level characteristics of elements; constructing a two-layer optimization model and using the two-layer optimization model to collaboratively optimize the initial generator matrix structure; the two-layer optimization model includes: an upper-layer optimization model configured to adjust the structural distribution of the generator matrix; and a lower-layer optimization model configured to schedule the bit-level operation paths after the generator matrix expansion based on the reference table and calculate the actual bit-level computational overhead; feeding back the bit-level computational overhead of the lower-layer optimization model to the upper-layer optimization model; and encoding the data to be stored based on the comprehensive evaluation result of the algebraic characteristics and the bit-level computational overhead. This invention achieves the collaborative unification of the generator matrix structure and XOR scheduling optimization through the two-layer optimization model, improving the coding rationality, practicality, and throughput.

The present invention proposes a method for constructing a locally recoverable code, which includes the following steps: initializing parameters; constructing and partitioning a Vandermonde matrix; constructing a summation matrix L; constructing a generator matrix G; and obtaining the construction result of the locally recoverable code. The present invention deploys a local check block, a global check block linearly associated with it, and an original data block in each cluster. This achieves the advantage of only needing to read other nodes in a cluster when recovering a node in the cluster, thus avoiding cross-cluster bandwidth. Furthermore, the generator matrix is ​​constructed by constructing a compression matrix and then a summation matrix, so that the generated local check block can be represented as a linear combination of the global check block and the original data block in the same cluster. This avoids the defect of needing to read all original data blocks when repairing the global check block, effectively improving data recovery efficiency.

This application relates to a decoding path determination method, apparatus, computer device, and storage medium. The method includes: constructing a symbol-based equivalent directed graph based on a polar code generator matrix; obtaining at least two initial symbol synchronization sets based on the equivalent directed graph; optimizing each initial symbol synchronization set based on frozen symbols in each initial symbol synchronization set and information symbols in a preset set to obtain an optimized symbol synchronization set; and determining the target decoding path based on the optimized symbol synchronization set. This method optimizes the symbol enumeration order, improves path evaluation at each decoding level, and further optimizes the enumeration order of symbols in the optimized symbol synchronization set, resulting in a more accurate final target decoding path.

Methods, systems, and devices for wireless communication are described. A device may generate a set of shaped bits based on a plurality of information bit sequences, each information bit sequence of the plurality of information bit sequences being a respective stream of demultiplexed bit sequences, where the set of shaped bits is based on a quasi-cyclic graph code. The device may apply the bit mask sequence to a first information bit sequence of the plurality of information bit sequences to form a mask bit sequence based on the set of shaped bits and a generator matrix, a parity check matrix, or both associated with the quasi-cyclic graph code, and the device may transmit a message including the mask bit sequence.

The invention provides a low-delay ECC (Error Correction Code) checking system and method based on a core particle interconnection interface controller, in the system, a sending end comprises an ECC check bit generation module, which is used for generating a 10-bit ECC check code for flit data of a data link layer based on a pre-generated special generation matrix, and inserting the check code as a tail part into a flit format; the receiving end comprises a main data path and an ECC (Error Correction Code) check branch which are arranged in parallel; and the selector selects to output the data of the first synchronous FIFO or the corrected data of the ECC error detection and correction module according to the check state signal. In order to solve the problems of high delay and large area of the ECC checking system of the existing chip particle interconnection interface controller, a check bit generation logic stage number is reduced by optimizing a generation matrix, a main path and ECC branch parallel processing structure is adopted at a receiving end, and a uniform bit width adaptation mechanism is combined, so that single-cycle checking generation and two-cycle error correction at the high frequency of 1.5 GHz are realized; and the delay and the hardware overhead are obviously reduced.

A coding circuit includes an encoder circuit that generates parity by applying input data to a parity generating matrix and generate input codeword by concatenating the input data and the parity, and a decoder circuit that detects and corrects an out-of-boundary 2-bit error using syndromes. The out-of-boundary 2-bit error corresponds to two 1-bit errors occurred at two symbols respectively among a plurality of symbols included in output codeword, and the syndromes are generated by applying the output codeword to the parity generating matrix.

The embodiment of the invention discloses a large model training method, device and equipment based on a causal attention lossless acceleration algorithm. The large model training method comprises the steps of obtaining training data to be trained; based on the training data to be trained, generating a Query matrix and a Key matrix; on the basis of a preset number of blocks, the Query matrix and the Key matrix are blocked, and a sub-matrix network is obtained; calculating the sub-blocks in the sub-matrix network according to a preset linear combination rule according to a preset number of structured matrix multiplication to obtain a multiplication result; performing mask multiplication operation on the multiplication result to obtain a mask result; performing addition operation on the multiplication result and the mask result to obtain a mask attention matrix; and based on the mask attention matrix, training to obtain a target large model.

A system encoder 300 reliably transmits a source data block (SDB) 311, configured for an outer transform matrix U and an inner transform matrix L. The inner encoder 301 receives the SDB and generates an output constraint block (OCB) 312, which is an image of the SDB under the inverse of a submatrix of the inner transform matrix. The outer encoder 302 receives a fixed data block (FDB) 313 and the OCB, and generates a transform output block (TOB) 315, which is an image of a transform input block (TIB) 314 under the outer transform matrix. The TIB transparently contains the FDB in its subblocks, and the TOB transparently contains the OCB in its subblocks. The inner encoder receives the TOB and generates a transmitted code block (TCB), which transparently contains the SDB in its subblocks.

A computer-implemented method generates a conversion matrix for mapping an output of a second machine learning model to an expected output of a first machine learning model. A set of example data is iteratively fed to the first machine learning model to create a set of first outputs and to the second machine learning model to create a set of second outputs. For each output of the set of first outputs and a corresponding output of the set of second outputs, a matrix is generated based on an optimization technique that maps the output of the second machine learning model to the output of the first machine learning model. Each of the generated matrices is summed to create an initial conversion matrix. Finally, each column of the initial conversion matrix is normalized to generate the conversion matrix.

A system, method, and computer program product for efficient node embedding for use in predictive models are described. The method includes receiving graph data associated with a graph including a plurality of nodes associated with a plurality of entities and a plurality of edges associated with interactions between the entities. The method further includes generating a plurality of node inlays of the plurality of nodes, and generating a matrix based on each positive node pair and the plurality of node inlays. The method also includes decomposing the matrix to provide a left unitary matrix, a diagonal matrix, and a right unitary matrix. The method also includes determining a plurality of updated node embedding of the plurality of nodes based on the left unitary matrix and the diagonal matrix. The method also includes transmitting the plurality of updated node inlays for input into a machine learning model to generate a prediction.

The application provides a multi-code rate LDPC encoder based on Verilog under the CCSDS standard and a coding method, belongs to the technical field of information coding, solves the problems of waste of storage space of the LDPC code encoder and high consumption of storage generation matrix resources of the encoder, and the LDPC encoder comprises a control module, a storage module, a cyclic shift module, a check bit calculation module and a code word register module; the application realizes the design and construction of the multi-code rate LDPC code encoder, improves the flexibility of the LDPC code encoder, is more conducive to the realization of coding in practical application, meanwhile, the application can save the storage space of the LDPC code encoder, save storage resources, and is conducive to the realization of the satellite encoder in the deep space environment.

The present application relates to a communication method and apparatus, and a readable storage medium. The method comprises: a sending end acquiring an information bit sequence, and using a generator matrix corresponding to a parity-check matrix of an LDPC code to encode the information bit sequence to obtain a codeword sequence, wherein the code length of the LDPC code is less than or equal to 36, and the girth of a Tanner graph corresponding to the parity-check matrix of the LDPC code is greater than or equal to 6; and sending the codeword sequence. By using the present application, the decoding success rate of the system can be improved, and thus the decoding performance and the transmission reliability are improved. The present application supports IEEE series protocols, such as IEEE 802.11bn / UHR protocol, IEEE 802.15 / UWB protocol, IEEE 802.11bf / sensing protocol or integrated millimeter wave / IMMW protocol. The present application can also support a spark link / nearlink standard protocol.

The invention belongs to the technical field of data chain communication channel coding and decoding, and provides an LDPC high-parallel coding method and system for frequency hopping communication based on MSK modulation, which can effectively realize data dimension reduction of a check matrix by splitting the check matrix into a first matrix and a second matrix. The computing power consumption in the encoding process can be reduced to adapt to the parallel encoding requirement of a low-computing-power compiler; a check bit generation matrix and a target unit matrix are spliced to obtain a target generation matrix, and parallel multiplication is performed on the target generation matrix and an information vector, so that high-speed coding of the information vector can be realized while information bit data of the information vector is reserved; the check bit generation matrix is divided into a plurality of cyclic dense matrixes with the size of M / 4 * M / 4, and then the cyclic dense matrixes and the information vectors are subjected to parallel multiplication and accumulation processing, so that the dimensionality of calculation data in the target check bit vector acquisition process can be effectively reduced, and the parallel calculation speed and the data throughput rate in the encoding process can be improved.

The embodiment of the application discloses a network coding method and device, the method comprises the following steps: selecting a data packet group from a plurality of to-be-sent data packets, and generating coded data packets by generating a matrix to code the data packets, and then sending the coded data packets to a receiving end, wherein, since the generating matrix has been reduced from a multiple domain to a binary vector domain, the calculation amount of the generating matrix is reduced, the coding and decoding complexity is reduced, and the time delay of data transmission is reduced.

A Polar code encoding and decoding method, the encoding process is: dividing a signal sequence, performing CRC cyclic redundancy encoding; calculating the channel reliability of each polarized channel, selecting the K polarized channels with the highest channel reliability as information bits, and the remaining polarized channels as frozen bits, sequentially placing information bits in the indexes corresponding to the information bits, and placing frozen bits in the indexes corresponding to the frozen bits to obtain a sequence u, multiplying u with a generator matrix of a Polar code to obtain an encoded sequence, and performing 2FSK modulation; the decoding process is: performing 2FSK non-coherent demodulation on the received signal, and decoding according to the obtained log-likelihood ratio (LLR) value. The present application can realize encoding and decoding of Polar codes with any code length based on 2FSK modulation, solve the problems of large attenuation, weak anti-noise performance of a low-frequency wireless communication system, and difficulty of applying Polar codes in the low-frequency wireless communication system, and has high system adaptability and good encoding and decoding effect under low signal-to-noise ratio conditions.

This application provides a decoding method and apparatus. First, the received sequence and generator matrix are preprocessed. Then, error patterns are guessed from the information bits and codeword sequences. Finally, the guessed error patterns are post-processed by comparing Euclidean distances based on checksums. The optimal decoded sequence is output as the decoding result. This application reduces the algorithm's complexity while maintaining effective decoding performance. Furthermore, by setting a maximum number of iterations, blind lookups are prevented, reducing the number of queries during the decoding process and effectively lowering the decoding complexity.