142 results about "Generator matrix" patented technology

The invention discloses a malicious instruction detection method and system fusing self-supervised learning and a knowledge graph. The method comprises the steps of obtaining user instruction data and compliance labels, constructing an adversarial sample generation matrix, and generating an adversarial sample library through hierarchical variation and compliance correction; inputting the original instruction and the adversarial sample into a multi-modal detection model, wherein the model comprises a dual-channel encoder and a dynamic knowledge graph module; through a self-supervised comparison loss function optimization model, positive samples need to meet semantic and attack feature similarity threshold requirements, and negative samples are violation instructions; inputting a to-be-detected instruction into the trained model, extracting features, performing multi-hop reasoning on the features and the knowledge graph, and calculating a risk score; and when a malicious instruction is detected, generating a disposal strategy and updating the knowledge graph node. Through fusion of self-supervised learning and the dynamic knowledge graph, accurate detection is realized, the generalization ability and robustness of the model are enhanced, and the detection precision is improved.

The embodiment of the invention provides a coding and decoding method and device and a storage medium, relates to the technical field of communication, and can reduce the storage space requirement of coding. The method comprises the steps that a parity check matrix is determined, the dimension of the parity check matrix is determined based on the dimension of a binary extension matrix, the binary extension matrix is obtained by hashing an index matrix based on a lifting factor, and the lifting factor is determined based on the order of a binary basic matrix, an information bit sequence and a non-binary low-density parity check code NB-LDPC code; and according to the parity check matrix or a generation matrix corresponding to the parity check matrix, performing NB-LDPC coding on the information bit sequence to obtain a coding sequence.

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial sub-matrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

Provided are an encoding method and apparatus, a decoding method and apparatus, and a storage medium. The encoding method comprises: determining a parity check matrix, wherein the dimension of the parity check matrix is determined on the basis of the dimension of a binary extended matrix, the binary extended matrix is obtained by hashing an exponential matrix on the basis of a lifting factor, and the lifting factor is determined on the basis of a binary fundamental matrix, an information bit sequence, and the order of a non-binary low density parity check code (NB-LDPC); and performing NB-LDPC encoding on the information bit sequence on the basis of the parity check matrix or a generator matrix corresponding to the parity check matrix, to obtain an encoding sequence.

The invention provides an erasure code data updating method and system of a distributed hybrid storage system. The erasure code data updating method comprises the steps of constructing a generation matrix; judging whether the effective data of the performance layer form a complete erasure code strip or not; if yes, reading a whole-strip data block of a performance layer, calculating and generating a new erasure code check block, writing the data block and the check block into a capacity layer in a one-time coverage manner, and repairing by adopting a whole-strip updating consistency repairing strategy after a fault occurs; and if not, reading the data to be updated of the performance layer and the old data blocks and all the check blocks at the corresponding positions of the capacity layer, writing the calculated new erasure code check blocks and new data blocks into the capacity layer according to a certain sequence, and repairing by adopting a non-full stripe updating consistency repair strategy after the fault occurs. According to the method, extra I / O operation required for maintaining new and old version data on the HDD is avoided, the utilization rate of storage resources is improved, and it is ensured that consistency and integrity can be quickly and efficiently recovered when write-in fails and possible data is lost due to superposition.

The invention provides a Verilog-based multi-code-rate LDPC (Low Density Parity Check) encoder under a CCSDS (Consultative Committee for Space Data System) standard and an encoding method, belongs to the technical field of information encoding, and solves the problems that the storage space of the LDPC encoder is wasted and the consumption of matrix resources stored and generated by the encoder is high. The LDPC encoder comprises a control module, a storage module, a cyclic shift module, a check bit calculation module and a code word register module. According to the multi-code-rate LDPC code encoder, the flexibility of the LDPC code encoder is improved by achieving design and construction of the multi-code-rate LDPC code encoder, encoding can be achieved in practical application more easily, meanwhile, the storage space of the LDPC code encoder can be saved, storage resources can be saved, and implementation of a satellite encoder in a deep space environment is facilitated.

Approaches in accordance with various embodiments provide for the processing of sparse matrices for mathematical and programmatic operations. In particular, various embodiments utilize a tiling approach that divides a sparse matrix into submatrices, many of which will include only zero-value entities. These empty tiles can be ignored, and only the tiles with non-zero entries processed, which reduces resource and time requirements for the processing. An indexing approach can be used for each entity that is a combination of the tile identifier and an offset value, which enables the values to be multiplied correctly against, for example, values of a dense matrix. The tiles can be processed in parallel and the results accumulated to generate a matrix product. The matrix product can then be passed to the next step in a process or operation, such as to a next layer in a deep neural network.

The invention relates to the technical field of communication, in particular to a non-sparse LDPC code high-speed parallel GPU encoder and an encoding method. The method comprises the following steps of: improving the utilization rate of the whole computing resource, and adopting inter-frame and intra-frame parallelism degrees. In order to greatly improve the instruction execution efficiency, information bits at the same positions of multiple frames distributed to the same thread block are packaged and stored in a register without sign shaping or sign long integer according to bits, and updating is carried out in the check bit updating process. In order to improve the memory access efficiency of the shared memory of the generated matrix, a storage space which is twice the length of a check bit is distributed for the shared memory of the generated matrix, and the number of times of remainder and division operations which are not good at the GPU is reduced. The LDPC encoder provided by the invention can be developed through a high-level programming language, has very high flexibility and expandability, and can adapt to the development requirements of software and virtualization of a satellite ground station system in the future.

One embodiment sets forth a technique for performing matrix operations. The technique includes traversing a tree structure to access one or more non-empty regions within a matrix. The tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. The first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. The second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. The technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.

The invention provides a security physical layer dynamic elastic polarization code coding method suitable for a non-degraded channel, which comprises the following steps of: firstly, carrying out channel polarization according to an original polarization code, generating a permutation matrix and a position vector based on a shared key, and obtaining a secret generation matrix based on the permutation matrix and the position vector; dividing the secret generation matrix into two sub-matrixes according to a channel polarization result; and taking the shared key as the input of a secure hash function, outputting a hash value of the shared key, taking the obtained hash value as a frozen bit, multiplying the frozen bit and plaintext information by a submatrix to obtain two row vectors, and finally transmitting an orientation vector XOR result as a ciphertext. And the legal receiver adopts the inverse process of the above process to recover the plaintext with the help of the shared key. According to the method, column confusion and random vector insertion modes are adopted, the code word structure of the original polarization code is destroyed, the safety is improved, the hash value of the shared key is used as the frozen bit, key leakage is avoided, and the method has high confidentiality.

The invention discloses an inventory management system based on order data, and relates to the technical field of intelligent warehousing, and the system comprises a priority evaluation module which calculates the allocation weight and the inventory allocation priority score between warehouses based on an inventory gap list, and generates a QUBO matrix; and the inventory allocation module is used for carrying out global optimal solution search by adopting a quantum annealing algorithm based on the QUBO matrix, carrying out decoding through a coding rule, generating an initial inventory allocation instruction set, carrying out optimization by adopting an MIL, generating an optimal inventory allocation instruction and executing the optimal inventory allocation instruction. According to the method, global optimal solution search is carried out by adopting a quantum annealing algorithm, and secondary optimization is carried out in combination with MILP, so that the overall cost minimization is realized on the premise that the generated allocation instruction meets complex business constraints.

The invention relates to the technical field of pseudo-random binary sequence design, in particular to a parallel PRBS generation method and system for testing a multi-protocol high-speed serial transceiver, and the method comprises the steps: setting demand parameters of a pseudo-random binary sequence for testing the multi-protocol high-speed serial transceiver, and enabling the demand parameters to comprise an order, a bit number and a feedback polynomial; constructing a generator matrix for describing state transition of the linear feedback shift register according to the feedback polynomial; according to the bit number of the pseudo-random binary sequence, generating a mapping matrix of the pseudo-random binary sequence through the exponentiation of the generated matrix; based on the mapping matrix and the current beat linear feedback shift register state, outputting a pseudo-random binary sequence meeting the requirement parameters for testing the multi-protocol high-speed serial transceiver. According to the method, parallel generation of any PRBS can be supported, the PRBS parallel implementation logic configuration is simple, the hardware implementation complexity is low, the PRBS output throughput rate is high, and the design requirements of multi-protocol high-speed SerDes can be met.

The invention discloses a coding and decoding processing method and device, and the method comprises the steps: a transmitting end obtains a basic parameter of an RM code and a plurality of to-be-processed information bits, determines a bit index set according to a predefined superposition proportion, a superposition mode and the basic parameter, carries out the coding of the to-be-processed information bits according to a preset coding mode and the bit index set, and carries out the decoding of the to-be-processed information bits. The preset coding mode is determined by a preset partially superposed Plotkin recursive structure or a corresponding generation matrix, modulating the coded code word, and sending the modulated signal to a receiving end through a channel, so that the receiving end performs channel decoding on the demodulated information through a preset decoding algorithm and outputs the demodulated information.

A semiconductor chip for correcting an aligned error comprises a memory array is provided. The semiconductor chip includes a transceiver circuit and an Error Correction Code (ECC) circuit. The ECC circuit is configured to receive target data to be encoded, encode the target data by multiplying a generator matrix of a previously generated ECC by the target data, store the encoded target data in the memory array, check a data transformed from the encoded target data, and generate an error corrected data by correcting only a single error of the transformed data and an adjacent error that does not exceed a first value boundary of a predetermined number of bits by using a parity check matrix of the ECC, and output the error corrected data.

A method is provided that includes performing, by a processor in response to a vector matrix multiply instruction, multiplying an m×n matrix (A matrix) and a n×p matrix (B matrix) to generate elements of an m×p matrix (R matrix), and storing the elements of the R matrix in a storage location specified by the vector matrix multiply instruction.

The application discloses a processing method and device for encoding and decoding. A sending end obtains basic parameters of an RM code and a plurality of information bits to be processed, determines a bit index set according to a predefined superposition ratio, a superposition mode and the basic parameters, encodes the plurality of information bits to be processed according to a preset encoding mode and the bit index set, and obtains a coded codeword. The preset encoding mode is determined by a Plotkin recursive structure or a corresponding generating matrix of a preset partial superposition. The coded codeword is modulated, the modulated signal is sent to a receiving end through a channel, so that the receiving end performs channel decoding on demodulated information through a preset decoding algorithm and outputs.

The present disclosure relates to a method, a computing device, a computing system, and a storage medium for generating an operator for tensor operations. The method includes: parsing input information for generating a matrix sequence; generating symbolic representation information for operations based on the generated matrix sequence and an input symbolic vector; converting the generated symbolic representation information into abstract syntax tree information or intermediate representation information; and generating assembly code for an operator for tensor operations based on basic description information included in the generated abstract syntax tree information and intermediate representation information. The present disclosure can make full use of the hardware performance of each processor, and can efficiently generate an operator library for high-performance tensor operations for a GPU.

The invention provides a visible light communication sending method, a receiving method and a visible light communication device, and the sending method comprises the steps: obtaining input information, and carrying out the filling processing of redundant bits when the information bit length of the input information is smaller than a preset required length; when the information bit length of the input information exceeds a preset required length, grouping the input information; grouping the generation matrix of the input information, and respectively storing the first row of data of each group in different addresses of a grouping register; the first row of data is shifted once in each clock cycle, information bits and check bits are generated, and LDPC codes are obtained; modulating the LDPC code to obtain a first modulation signal; performing digital-to-analog conversion on the first modulation signal to obtain a first analog voltage signal; sending the first analog voltage signal to an LED linear driving circuit to obtain a visible light signal; and sending the visible light signal to an optical signal receiving end. The transmission speed of visible light communication is improved, and the visible light communication process is more reliable.

The invention belongs to the technical field of telecommunication, and discloses a two-dimensional RS code encoding and decoding method for streaming media data transmission. The method comprises the following steps: dynamically setting a coding parameter set based on network state data and application service data; constructing a finite field I and a finite field II based on the coding parameter set; constructing a Vandermonde matrix inverse matrix set based on the finite field 2; constructing an RS code generation matrix based on the finite field I, the finite field II and the Vandermonde matrix inverse matrix set; performing two-dimensional coding on the K original data packets based on an RS code generation matrix and a Vandermonde matrix inverse matrix set to generate R redundant data packets; the receiving end carries out decoding according to the received original data packets and the redundant data packets, and if the number of the received data packets is K, the K original data packets are directly recovered; if the V redundant data packets and the K-V original data packets are received, decoding recovery operation is carried out; according to the invention, accurate error correction and controllable fault tolerance of streaming media data transmission are realized.

The present invention discloses an order data-based inventory management system, which relates to the field of intelligent warehousing technology. The system includes a priority assessment module that calculates transfer weights and inventory transfer priority scores between warehouses based on an inventory gap list and generates a QUBO matrix. An inventory transfer module uses a quantum annealing algorithm to search for a global optimal solution based on the QUBO matrix, decodes the solution using encoding rules, generates an initial inventory transfer instruction set, and simultaneously optimizes the system using MILP to generate and execute the optimal inventory transfer instructions. By using a quantum annealing algorithm to search for a global optimal solution and combining it with MILP for secondary optimization, the present invention ensures that the generated transfer instructions minimize overall costs while meeting complex business constraints.

One embodiment sets forth a technique for performing matrix operations. The technique includes traversing a tree structure to access one or more non-empty regions within a matrix. The tree structure includes a first plurality of nodes and a second plurality of nodes corresponding to non-empty regions in the matrix. The first plurality of nodes includes a first node representing a first region and one or more second nodes that are children of the first node and represent second region(s) with an equal size formed within the first region. The second plurality of nodes include a third node representing a third region and one or more fourth nodes that are children of the third node and represent fourth region(s) with substantially equal numbers of non-zero matrix values formed within the third region. The technique also includes performing matrix operation(s) based on the non-empty region(s) to generate a matrix operation result.

A channel coding method and processing device, a communication method and device. The channel coding method includes: using a QC-LDPC code generator matrix or a check matrix to perform channel coding or channel decoding on a code stream, wherein the code rate of the generator matrix or the check matrix is ​​1 / 6, 1 / 4 or 1 / 3. The method can be used in low signal-to-noise ratio and long-distance transmission environments.

The present invention relates to the field of electronic communication technologies, and more specifically, to a method for generating quasi-cyclic hyperelliptic codes. The method includes: S1. Selecting a hyperelliptic curve according to given coding parameters; S2. Generating a divisor on the corresponding curve according to the given coding parameters; S3. Calculating a compact generator matrix by using the hyperelliptic curve and the divisor. The present invention can generate quasi-cyclic codes or cyclic codes of any length by using hyperelliptic curves, and obtain the algebraic geometric expression form of the generated quasi-cyclic codes and the expression form of the compact generator matrix. The present invention establishes a connection between hyperelliptic curves and quasi-cyclic codes, and solves part of the problems of representing quasi-cyclic codes and cyclic codes in algebraic geometric forms. The hyperelliptic quasi-cyclic codes generated by the present invention have a clear algebraic geometric structure, and this structure can be used for decoding methods unique to algebraic geometric codes such as list decoding, thereby improving the error correction ability of channel coding and reducing the storage space of the coding matrix.

An error correction circuit for a semiconductor memory device includes an error correction code (ECC) encoder and an ECC decoder. The ECC encoder generates parity data based on main data using an error correction code represented by a generator matrix, and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page as a read codeword based on an address provided from outside the semiconductor memory device, generates different syndromes based on the read codeword and a parity check matrix, the parity check matrix being based on the ECC, and applies the different syndromes to the main data in the read codeword to correct a single bit error when there is one in the main data, or to correct two bit errors when two bit errors occur in two adjacent memory cells in the target page.

A coding method and apparatus are provided to provide a uniform coding method for ultra short codes. The method is as follows: obtaining, by a transmit end, to-be-coded information bits; performing, by the transmit end, PC-polar coding on the to-be-coded information bits based on first constructor parameters, to obtain a coded bit sequence; and sending the coded bit sequence, where a check equation of the first constructor parameters include a first element representing a check-required information bit position and a second element representing a check bit position, the first element corresponds to a first vector in a generator matrix for PC-polar codes, the second element corresponds to a second vector in the generator matrix, and if a first Hamming weight of the first vector is the same as a second Hamming weight of the second vector, a third Hamming weight of an addition modulo 2 vector is greater than the first Hamming weight and greater than the second Hamming weight, or if the first Hamming weight is different from the second Hamming weight, the third Hamming weight is greater than a smaller one of the first Hamming weight and the second Hamming weight.

The application discloses a data encryption method, and belongs to the technical field of text encryption. First, the text data is converted into binary code and split into odd and even bit sequences, and corresponding matrices are constructed respectively; the odd and even shift matrices are obtained by generating matrix row / column state bits, calculating shift amount and performing cyclic shift; then the rows and columns of the shift matrix are converted into decimal numerical vectors, combined with fractal offset key vectors for encryption, and four types of encryption matrices of odd row, odd column, even row and even column are generated; the same type of matrices are subjected to XOR processing, and the confusion value is generated based on the odd part and the even part related value, so that the mixed enhanced encryption matrix is obtained; finally, the two types of enhanced matrices are restored into sequences and reorganized according to the odd and even bits, and the ciphertext is output. Through the multilevel processing of bit splitting, matrix shifting, fractal key encryption and XOR confusion, the complexity and anti-cracking ability of data encryption are significantly improved, and the safety of data transmission and storage is ensured.

The embodiment of the invention provides a data coding method, which comprises the following steps: acquiring a target matrix which is a check matrix or a generator matrix and is a binary matrix representing data units of a finite field 2a on a polynomial ring, the polynomial corresponding to the polynomial ring is an irreducible polynomial of which the highest number of times is not greater than a; according to the target matrix, encoding a data block to obtain an encoding result; wherein the coding result is used as a redundant data block of the data block; or the coding result is a recovery result of the data block of the node where the coding result is located. In the embodiment of the invention, one irreducible polynomial can be selected as the polynomial corresponding to the polynomial ring, so that the data unit of the finite field 2a can be converted to the corresponding polynomial ring to be expressed, and then the exclusive or operation equivalent to the multiplication operation can be carried out through the data expressed on the basis of the polynomial ring. And the calculation overhead is reduced.

The invention provides a scrambling code generation method and device, equipment, a medium and a product, and relates to the technical field of communication, and the method comprises the steps: obtaining a target scrambling code length, selecting the first n rows in a pre-constructed first scrambling code generation matrix as a second scrambling code generation matrix based on the target scrambling code length, and enabling n to be equal to the target scrambling code length; generating a scrambling code calculation result based on the second scrambling code generation matrix and the initialization value of each register; wherein each row of the first scrambling code generation matrix reflects the corresponding relation between each bit of scrambling code and the initialization value of the register. The method does not need to wait for a plurality of clock cycles to generate the multi-digit scrambling code, and can improve the scrambling code generation efficiency.

The invention provides a bit interleaving chirp spread spectrum modulation method, device and equipment based on an LDPC (Low Density Parity Check) code, and relates to the technical field of Internet communication, and the method comprises the steps: coding original information through the LDPC code, and obtaining an initial code word; the LDPC code comprises a generation matrix and a check matrix; performing diagonal matrix interleaving and CSS modulation on the initial code word in sequence to generate intermediate information; and inputting the intermediate information to a preset channel, sequentially performing demodulation and de-interleaving, and performing LDPC decoding to obtain target information. According to the invention, the LDPC code is utilized to increase the check bit for error correction, so that the limitation that the communication service quality of the LoRa physical layer is sharply reduced in a complex and dynamic channel environment is made up, the reliability of information transmission is enhanced, and high-throughput and high-reliability network transmission is formed.

The invention provides a construction method of a local recoverable code. The construction method comprises the following implementation steps of: initializing parameters; constructing a Vandermonde matrix and dividing the Vandermonde matrix; constructing an addition matrix L; constructing a generation matrix G; and obtaining a construction result of the local recoverable code. According to the method, one local check block and the global check block and the original data block which are linearly related to the local check block are deployed in each cluster, so that the advantage that only other nodes in the cluster need to be read when one node in one cluster is recovered is realized, and cross-cluster bandwidth is avoided; and the generation matrix is constructed in a mode of constructing the compression matrix and then constructing the addition matrix, so that the generated local check block can be expressed as a linear combination of the global check block and the original data block in the same cluster, the defect that all the original data blocks need to be read when the global check block is repaired is avoided, and the data recovery efficiency is effectively improved.