39 results about "Generator matrix" patented technology

Approaches in accordance with various embodiments provide for the processing of sparse matrices for mathematical and programmatic operations. In particular, various embodiments utilize a tiling approach that divides a sparse matrix into submatrices, many of which will include only zero-value entities. These empty tiles can be ignored, and only the tiles with non-zero entries processed, which reduces resource and time requirements for the processing. An indexing approach can be used for each entity that is a combination of the tile identifier and an offset value, which enables the values to be multiplied correctly against, for example, values of a dense matrix. The tiles can be processed in parallel and the results accumulated to generate a matrix product. The matrix product can then be passed to the next step in a process or operation, such as to a next layer in a deep neural network.

The application discloses a data encryption method, and belongs to the technical field of text encryption. First, the text data is converted into binary code and split into odd and even bit sequences, and corresponding matrices are constructed respectively; the odd and even shift matrices are obtained by generating matrix row / column state bits, calculating shift amount and performing cyclic shift; then the rows and columns of the shift matrix are converted into decimal numerical vectors, combined with fractal offset key vectors for encryption, and four types of encryption matrices of odd row, odd column, even row and even column are generated; the same type of matrices are subjected to XOR processing, and the confusion value is generated based on the odd part and the even part related value, so that the mixed enhanced encryption matrix is obtained; finally, the two types of enhanced matrices are restored into sequences and reorganized according to the odd and even bits, and the ciphertext is output. Through the multilevel processing of bit splitting, matrix shifting, fractal key encryption and XOR confusion, the complexity and anti-cracking ability of data encryption are significantly improved, and the safety of data transmission and storage is ensured.

The invention provides a scrambling code generation method and device, equipment, a medium and a product, and relates to the technical field of communication, and the method comprises the steps: obtaining a target scrambling code length, selecting the first n rows in a pre-constructed first scrambling code generation matrix as a second scrambling code generation matrix based on the target scrambling code length, and enabling n to be equal to the target scrambling code length; generating a scrambling code calculation result based on the second scrambling code generation matrix and the initialization value of each register; wherein each row of the first scrambling code generation matrix reflects the corresponding relation between each bit of scrambling code and the initialization value of the register. The method does not need to wait for a plurality of clock cycles to generate the multi-digit scrambling code, and can improve the scrambling code generation efficiency.

A memory device and an operating method of operating the memory device are provided. The method includes: obtaining, by a memory controller, channel selection information indicating positions of data bits and shaping parity bits; generating, by the memory controller, an alignment vector by aligning the data bits and the shaped parity bits having an arbitrary value based on the channel selection information; generating, by the memory controller, second LLR information of the target vector based on the first LLR information related to the alignment vector; determining, by the memory controller, a value of a shaped parity based on the target vector and the second LLR information; performing, by the memory controller, an update operation on the shaped parity based on the determined value; and generating, by the memory controller after performing the update operation, a codeword with respect to the input data based on a first matrix multiplication calculation of the target vector and the first generated matrix.

A coding method and apparatus are provided. The method includes: coding an information bit by using a preset generator matrix of a systematic (U|U+V)-code to obtain a codeword of a systematic code. The preset generator matrix of the systematic (U|U+V)-code includes a first identity sub-matrix of a U code and a second identity sub-matrix of a V code. A plurality of elements in a same column as the first identity sub-matrix are all 0. A plurality of elements in a same column as the second identity sub-matrix are all 0.

The application relates to the field of high-performance computing and computing power optimization, and relates to a method for accelerating triangular matrix multiplication based on an atlas 800 platform, which comprises the following steps: cutting a result matrix into multiple task blocks, and presetting an equal division strategy based on the multiple task blocks; generating a mask matrix on a vector calculation unit, and storing the mask matrix back to a global memory; reading the matrix and the mask matrix from the global memory, implementing triangular masking of the matrix by using the vector calculation unit, and obtaining a triangular matrix A after triangular masking; based on the triangular matrix A after triangular masking, calling a cube calculation unit to complete matrix multiplication operation of all the task blocks according to the preset equal division strategy, and obtaining a result matrix. The mix method combining the vector calculation unit and the cube calculation unit is used to complete the triangular matrix multiplication, the calculation efficiency of the triangular matrix multiplication on the NPU is improved, the computing power of the Huawei atlas 800 NPU can be fully utilized, the triangular matrix multiplication calculation is accelerated, and computing power support is provided for the fields of deep learning and scientific calculation.

In accordance with an example aspect of the present disclosure, data is encoded or decoded using a polar code, where a generation matrix of the polar code includes rows of a polar transformation matrix formula (I), where is an N * N-bit inversion matrix, where N = 2n is a non-negative integer, and where formula (II) is an n-fold Kronecker product of formula (III), where N = 2n is a non-negative integer. The index set of the rows forming the polarization transformation matrix of the generating matrix is set A.

This application provides a Gaussian elimination method and apparatus with look-ahead operation, comprising: acquiring a first input vector and a second input vector for inputting a target double-column elimination unit within one clock cycle; when the target double-column elimination unit is a first-level double-column elimination unit, the two input vectors are read from the generator matrix; when the target double-column elimination unit is a subsequent-level double-column elimination unit, the two input vectors are the output of the previous-level double-column elimination unit; calculating candidate vectors based on the two input vectors according to the current initialization state of the target double-column elimination unit; determining the output of the target double-column elimination unit based on the first input vector, the second input vector, and / or the candidate vectors according to the current initialization state of the target double-column elimination unit, and updating the initialization state of the target double-column elimination unit. This method enables the processing of two columns of data from the generator matrix using a double-column elimination unit within one clock cycle, reducing processing time and resource consumption, and improving processing efficiency.

This invention relates to an erasure coding method and system based on two-layer optimization. The method includes: obtaining storage parameters of the data to be stored; constructing an initial generator matrix structure and a reference table for characterizing the bit-level characteristics of elements; constructing a two-layer optimization model and using the two-layer optimization model to collaboratively optimize the initial generator matrix structure; the two-layer optimization model includes: an upper-layer optimization model configured to adjust the structural distribution of the generator matrix; and a lower-layer optimization model configured to schedule the bit-level operation paths after the generator matrix expansion based on the reference table and calculate the actual bit-level computational overhead; feeding back the bit-level computational overhead of the lower-layer optimization model to the upper-layer optimization model; and encoding the data to be stored based on the comprehensive evaluation result of the algebraic characteristics and the bit-level computational overhead. This invention achieves the collaborative unification of the generator matrix structure and XOR scheduling optimization through the two-layer optimization model, improving the coding rationality, practicality, and throughput.

This application relates to a decoding path determination method, apparatus, computer device, and storage medium. The method includes: constructing a symbol-based equivalent directed graph based on a polar code generator matrix; obtaining at least two initial symbol synchronization sets based on the equivalent directed graph; optimizing each initial symbol synchronization set based on frozen symbols in each initial symbol synchronization set and information symbols in a preset set to obtain an optimized symbol synchronization set; and determining the target decoding path based on the optimized symbol synchronization set. This method optimizes the symbol enumeration order, improves path evaluation at each decoding level, and further optimizes the enumeration order of symbols in the optimized symbol synchronization set, resulting in a more accurate final target decoding path.

The invention provides a low-delay ECC (Error Correction Code) checking system and method based on a core particle interconnection interface controller, in the system, a sending end comprises an ECC check bit generation module, which is used for generating a 10-bit ECC check code for flit data of a data link layer based on a pre-generated special generation matrix, and inserting the check code as a tail part into a flit format; the receiving end comprises a main data path and an ECC (Error Correction Code) check branch which are arranged in parallel; and the selector selects to output the data of the first synchronous FIFO or the corrected data of the ECC error detection and correction module according to the check state signal. In order to solve the problems of high delay and large area of the ECC checking system of the existing chip particle interconnection interface controller, a check bit generation logic stage number is reduced by optimizing a generation matrix, a main path and ECC branch parallel processing structure is adopted at a receiving end, and a uniform bit width adaptation mechanism is combined, so that single-cycle checking generation and two-cycle error correction at the high frequency of 1.5 GHz are realized; and the delay and the hardware overhead are obviously reduced.

The embodiment of the invention discloses a large model training method, device and equipment based on a causal attention lossless acceleration algorithm. The large model training method comprises the steps of obtaining training data to be trained; based on the training data to be trained, generating a Query matrix and a Key matrix; on the basis of a preset number of blocks, the Query matrix and the Key matrix are blocked, and a sub-matrix network is obtained; calculating the sub-blocks in the sub-matrix network according to a preset linear combination rule according to a preset number of structured matrix multiplication to obtain a multiplication result; performing mask multiplication operation on the multiplication result to obtain a mask result; performing addition operation on the multiplication result and the mask result to obtain a mask attention matrix; and based on the mask attention matrix, training to obtain a target large model.

A computer-implemented method generates a conversion matrix for mapping an output of a second machine learning model to an expected output of a first machine learning model. A set of example data is iteratively fed to the first machine learning model to create a set of first outputs and to the second machine learning model to create a set of second outputs. For each output of the set of first outputs and a corresponding output of the set of second outputs, a matrix is generated based on an optimization technique that maps the output of the second machine learning model to the output of the first machine learning model. Each of the generated matrices is summed to create an initial conversion matrix. Finally, each column of the initial conversion matrix is normalized to generate the conversion matrix.

The application provides a multi-code rate LDPC encoder based on Verilog under the CCSDS standard and a coding method, belongs to the technical field of information coding, solves the problems of waste of storage space of the LDPC code encoder and high consumption of storage generation matrix resources of the encoder, and the LDPC encoder comprises a control module, a storage module, a cyclic shift module, a check bit calculation module and a code word register module; the application realizes the design and construction of the multi-code rate LDPC code encoder, improves the flexibility of the LDPC code encoder, is more conducive to the realization of coding in practical application, meanwhile, the application can save the storage space of the LDPC code encoder, save storage resources, and is conducive to the realization of the satellite encoder in the deep space environment.

The invention belongs to the technical field of data chain communication channel coding and decoding, and provides an LDPC high-parallel coding method and system for frequency hopping communication based on MSK modulation, which can effectively realize data dimension reduction of a check matrix by splitting the check matrix into a first matrix and a second matrix. The computing power consumption in the encoding process can be reduced to adapt to the parallel encoding requirement of a low-computing-power compiler; a check bit generation matrix and a target unit matrix are spliced to obtain a target generation matrix, and parallel multiplication is performed on the target generation matrix and an information vector, so that high-speed coding of the information vector can be realized while information bit data of the information vector is reserved; the check bit generation matrix is divided into a plurality of cyclic dense matrixes with the size of M / 4 * M / 4, and then the cyclic dense matrixes and the information vectors are subjected to parallel multiplication and accumulation processing, so that the dimensionality of calculation data in the target check bit vector acquisition process can be effectively reduced, and the parallel calculation speed and the data throughput rate in the encoding process can be improved.

The embodiment of the application discloses a network coding method and device, the method comprises the following steps: selecting a data packet group from a plurality of to-be-sent data packets, and generating coded data packets by generating a matrix to code the data packets, and then sending the coded data packets to a receiving end, wherein, since the generating matrix has been reduced from a multiple domain to a binary vector domain, the calculation amount of the generating matrix is reduced, the coding and decoding complexity is reduced, and the time delay of data transmission is reduced.

A Polar code encoding and decoding method, the encoding process is: dividing a signal sequence, performing CRC cyclic redundancy encoding; calculating the channel reliability of each polarized channel, selecting the K polarized channels with the highest channel reliability as information bits, and the remaining polarized channels as frozen bits, sequentially placing information bits in the indexes corresponding to the information bits, and placing frozen bits in the indexes corresponding to the frozen bits to obtain a sequence u, multiplying u with a generator matrix of a Polar code to obtain an encoded sequence, and performing 2FSK modulation; the decoding process is: performing 2FSK non-coherent demodulation on the received signal, and decoding according to the obtained log-likelihood ratio (LLR) value. The present application can realize encoding and decoding of Polar codes with any code length based on 2FSK modulation, solve the problems of large attenuation, weak anti-noise performance of a low-frequency wireless communication system, and difficulty of applying Polar codes in the low-frequency wireless communication system, and has high system adaptability and good encoding and decoding effect under low signal-to-noise ratio conditions.

This application provides a decoding method and apparatus. First, the received sequence and generator matrix are preprocessed. Then, error patterns are guessed from the information bits and codeword sequences. Finally, the guessed error patterns are post-processed by comparing Euclidean distances based on checksums. The optimal decoded sequence is output as the decoding result. This application reduces the algorithm's complexity while maintaining effective decoding performance. Furthermore, by setting a maximum number of iterations, blind lookups are prevented, reducing the number of queries during the decoding process and effectively lowering the decoding complexity.

The application provides a dynamic encoding method of a secure polar code based on double-sequence mixing, which comprises the following steps: determining the encoding length N, a shared key k and an agreed number by both parties; encrypting the shared key k by using an encryption algorithm to obtain two pseudo-random sequences by a sending end and a receiving end, and determining a mixed random sequence r according to the agreed number and the two pseudo-random sequences; constructing a bit scrambler and a generation matrix G according to the encoding length N by the sending end, and sequentially inputting a to-be-sent information m and the mixed random sequence r into the bit scrambler, the generation matrix G and a BPSK modulator to obtain a sending code word A; after the sending code word A is transmitted through a wireless channel, a signal B is received by the receiving end, and the signal B and the mixed random sequence r are input into a decoder to obtain original information. The application adopts the stream key technology to mix and encrypt to generate the random sequence, and realizes the changeable code length at the encoding level; and the secret encoding mode is used to realize the channel encoding and decoding which can meet the security requirements.

The invention relates to a sparse matrix data generation method and system based on a graph neural network. The method comprises the steps of obtaining a sparse structure of a to-be-generated sparse matrix; obtaining a target numerical value feature vector, and mapping the target numerical value feature vector into a modulation parameter through a condition encoder; performing message passing by using a graph neural network based on the sparse structure and the modulation parameters to obtain potential characterization of nodes and / or edges; generating an edge weight aligned with the sparse structure according to the potential representation, and applying a structure keeping constraint to the generated edge weight to enable the edge weight to be consistent with the sparse structure; and performing symmetric and / or positive qualitative processing based on the generated edge weight to obtain a generated matrix. According to the method, numerical value characteristic controllability and symmetric positive definite guarantee are achieved on the premise that the structure is kept, batch generation is supported, the reliability of sparse matrix data generation is improved, and the method is suitable for data enhancement and solver performance evaluation in scientific calculation and engineering simulation scenes.

The present application provides a communication method, a communication apparatus, a computer-readable storage medium, a chip, and a computer program product. The communication method comprises: determining a log-likelihood ratio (LLR) vector associated with a received vector; taking absolute values of at least some elements in the LLR vector and then sorting same; dividing elements in a systematic bit vector into a plurality of groups according to an ascending order of sorting results, wherein the systematic bit vector comprises first to k-th elements in the received vector, and k is an integer greater than or equal to 1; determining a flipping order of bits in each group among the plurality of groups as being non-increasing; based on the flipping order, flipping the bits in each group to obtain a plurality of flipped systematic bit vectors; determining a plurality of codeword vectors on the basis of the plurality of flipped systematic bit vectors and a generator matrix; and from among the plurality of codeword vectors, selecting, as a decoding result of the received vector, a first codeword vector having the smallest Euclidean distance from the LLR vector. The method of the present application can be regarded as a decoding method combining the advantages of OSD and GRAND, is an efficient GRAND method that reduces the flip range by means of LLR sorting, and can also be regarded as a Gaussian-elimination-free OSD.

This specification provides a decoding method and apparatus through one or more embodiments, comprising: performing hard-decision decoding on a received sequence to obtain a hard-decision decoded sequence; performing a permutation process on a generator matrix to obtain a permuted generator matrix; and, in response to the failure to meet a preset decoding termination condition, selecting a target error pattern based on a preset set of error patterns, and generating a decoding result corresponding to the current decoding iteration based on the target error pattern, the hard-decision decoded sequence, and the permuted generator matrix. The decoding method of this embodiment can guarantee decoding performance and reduce decoding complexity.

The application discloses an implementation method for reducing the density of a QC-LDPC code generation matrix, and comprises QC_LDPC code check matrix full rank condition generation matrix solving, QC-LDPC code check matrix non-full rank condition generation matrix solving and density optimization, and a QC_LDPC code encoding process. The application solves the problem of high density of the existing QC-LDPC code generation matrix and existence of optimization space.

The application provides a scrambling code generation method, device, equipment, medium and product, and relates to the technical field of communication. The method comprises the following steps: obtaining a target scrambling code length; selecting the first n rows in a pre-constructed first scrambling code generation matrix as a second scrambling code generation matrix based on the target scrambling code length, wherein n is equal to the target scrambling code length; and generating a scrambling code calculation result based on the second scrambling code generation matrix and the initialization values of the registers. Each row of the first scrambling code generation matrix reflects the corresponding relationship between each bit of the scrambling code and the initialization values of the registers. The application can generate a multi-bit scrambling code without waiting for multiple clock cycles, and can improve the scrambling code generation efficiency.

The invention relates to the technical field of energy storage, in particular to a distributed electric heating hybrid energy storage aggregation method capable of coordinately adjusting accuracy and synchronism, which comprises the steps of modeling distributed electric heating hybrid energy storage units, performing Zone-top approximation based on a uniform generator matrix, and aggregating the distributed electric heating hybrid energy storage units. The unified generator matrix is composed of a power constraint generator column vector and an energy constraint generator column vector, cluster aggregation feasible regions are subjected to linear synthesis, a synchronization index RSI and an accuracy index EI are adopted to measure the difference between Zone-top and a single resource original feasible region, an aggregation result is output, and a scheduling instruction is decomposed; according to the method, a Zone-top approximation and synchronism-accuracy double-index collaborative optimization mechanism is introduced, so that the problems of high calculation complexity, poor model compatibility and asynchronous dynamic response in the prior art are systematically solved.

This invention discloses a method for imputing missing values ​​in scRNA-seq data based on nonnegative matrix factorization, belonging to the technical field of deep learning and data imputation methods. This invention solves the problem of low accuracy in imputing missing values ​​in single-cell RNA sequencing data using existing methods. The main technical solution of this invention is as follows: Step 1: Filter cells based on gene data to obtain RNA sequencing data of the remaining cells after filtering; normalize, screen genes, and perform logarithmic transformation on the RNA sequencing data of the remaining cells after filtering to generate matrix X; Step 2: Decompose matrix X to obtain a feature matrix and a coefficient matrix; Step 3: Construct an input matrix for an autoencoder based on the feature matrix, use the input matrix as the input of the autoencoder, and output the imputed feature matrix through the autoencoder; Step 4: Perform decomposition, logarithmic reduction, and inverse normalization on the imputed feature matrix in sequence to obtain the imputed result. This invention can be applied to RNA sequencing data imputation.

This invention discloses a method, system, and device for generating binary linear complementary code pairs based on Belov codes, belonging to the interdisciplinary field of error correction codes and information security. The method includes: obtaining initial Belov code parameters; selecting Belov code construction parameters; calculating equivalent SS code parameters; constructing an SS code generation matrix; constructing a Belov code generation matrix; constructing linear complementary code pairs based on the Belov code generation matrix, performing column swapping and cyclic row shifting operations on the information bit matrix; verifying the invertibility condition; and outputting the generation matrix of the linear complementary code pairs to configure a data security protection system. This invention solves the problems of limited parameter range, high minimum distance requirements, and insufficient construction flexibility in existing binary linear complementary code pair construction methods.

Provided are a decoding device and a method for performing class most reliable base (MRB) decoding on a code of which the length is in the range of the dimension is in the range of the range of the length, and a method for performing class MRB decoding on a code of which the dimension is in the range of the range of the length. The decoding device is configured to receive a sequence of one or more channel observations. Then, the decoding device ranks (102) one or more reliability values in a descending order, where each reliability value corresponds to the channel observations of the receive sequence. The decoding device determines (103) a class MRB base of the code from the sorted reliability values. The class MRB basis is defined by a number of independent locations obtained from the ranking. The decoding device further constructs (105) a generator matrix according to an ordering determined by the class MRB bases by Gaussian elimination performed on a sub-matrix (104) of the first matrix. The first matrix is derived based on a simplified stepped generation matrix of the code. The decoding device then performs decoding according to the constructed generator matrix (106). Since a partial unit matrix may be obtained from the simplified stepped shape of the generator matrix by row and / or column permutation, limited Gaussian elimination may be performed on a matrix of a size smaller than the complete size of the generator matrix of the code, thereby reducing computational complexity.

A method for generating a cryptographic key, which is executed by a computer processor, wherein steps of generating matrices in accordance with a McEliece cryptosystem are carried out. The computer processor then further executes at least two of the following three combination steps: combining one random encoding matrix with the merged permutation, coding and transformation matrix to form an encoded permutation, coding and transformation matrix; combining another random encoding matrix with the permutation cancellation matrix to form an encoded permutation cancellation matrix; and combining another random encoding matrix with the transformation cancellation matrix to form an encoded transformation cancellation matrix.

The application provides a decoding determination method and device, electronic equipment and a storage medium. The method comprises: determining the reliability metric of a received reception sequence y to determine an information sequence z; generating an information bit window corresponding to the information sequence z according to a preset generation criterion; sorting a pre-acquired initial generation matrix G according to a permutation function to determine a system generation matrix G1, and determining a hard decision decoding; obtaining an error pattern e according to an error pattern generation rule, and flipping the system bit in the codeword information sequence according to the error pattern e to determine K new system bit; obtaining a binary bit sequence according to the system generation matrix G1 and the hard decision codeword sequence determined according to the new system bit; in response to the hard decision codeword sequence being legal, determining the candidate minimum Euclidean distance of the information bit window, determining the optimal hard decision codeword sequence under the information bit window corresponding to the minimum Euclidean distance, and determining the optimal decoding according to the optimal hard decision codeword sequence.