44 results about "Cyclic code" patented technology

In an aspect, digital communication coding methods (or simply coding methods) are provided, said methods comprising providing families of quasi-cyclic low-density parity check, LDPC, codes each represented by a single equation. Said single equation is derived from a geometry whose nature implies good error correcting properties for each of the LDPC codes and allows quasi-cyclic parity check matrices to be constructed for geometric LDPC codes of exceedingly long length, up to and exceeding four hundred thousand bits. The construction of such check matrices is not possible by any other known method. The LDPC codes have different lengths and different rates and the families of LDPC codes are provided with a guarantee of minimum distance. The geometric and quasi-cyclic properties of the LDPC codes allow low complexity decoding with very low frame error rates. Systems, computing systems and computer programs suitable to perform such coding methods are also provided.

Provided is a communication system based on end-to-end data encryption. The system includes a domain controller, an actuator, and a sensor. The sensor is configured to sense vehicle state information and transmit the vehicle state information as sensed to the domain controller through an end-to-end communication protection protocol; and the domain controller is configured to acquire a control instruction based on the vehicle state information as received, and transmit a corresponding control instruction to a corresponding actuator through the end-to-end communication protection protocol. The end-to-end communication protection protocol is additionally provided with a cyclic code that is variable and configured to encrypt information for communication.

The invention relates to a device for detecting the tracking capability of a digital image processor, belongs to the technical field of image processing, and solves the problems of limited efficiency and accuracy of a data processing and arbitration system and poor data synchronism in the existing related technologies for detecting the tracking capability of optical measurement equipment. The system comprises a multi-target image source board card which generates a multi-target image with superposition information, transmits the multi-target image to an upper computer and a detected digital image processor, and outputs the superposition information to a tracking capability arbiter; the tracking capability arbiter is used for resolving a cyclic code and a target miss distance in the collected superposed information, judging the tracking capability of the digital image processor according to a resolving result, obtaining arbitration information and sending the arbitration information to the upper computer; and the upper computer is used for integrating and visually displaying the multi-target image and the arbitration information. The efficiency and accuracy of data processing and arbitration are improved, the stability and reliability of the detection device are improved, and meanwhile data transmission is complete and accurate.

The invention provides an encoding control method and device based on long-period cyclic traversal. The method comprises the following steps: generating a cyclic encoding sequence according to initial scanning parameters based on an n-bit binary encoder; wherein the cyclic coding sequence comprises 2n different decimal elements; performing end-to-end cyclic arrangement operation on the cyclic coding sequence to obtain a new cyclic coding sequence; each element in the new cyclic coding sequence corresponds to a binary significant bit, continuous n coding states of the binary significant bit are the same, and adjacent n coding states are alternately changed; and state switching of a plurality of execution components of the actuator is adjusted according to the new cyclic coding sequence, and the actuator is controlled to perform cyclic traversal scanning according to the new cyclic coding sequence. According to the method, the function of circular traversal scanning is achieved, the requirement of the system for the state switching completion response time of the actuator is lowered, and the higher traversal scanning speed can be achieved.

Systems, apparatuses and methods provide technology that identifies a codeword associated with a fluid cooling system and a network system, generates a status update with the network system, embeds the codeword as a repeating cyclic codeword in a message containing the status update, transmits the message from the network system to the fluid cooling system over a data link, receives the message at the fluid cooling system, and determines, with the fluid cooling system, whether interference is inserted into the message based on the repeating cyclic codeword in the message.

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

The invention discloses a decoder used for a cyclic code and having cyclic equivalence and a decoding method, and relates to the technical field of communication and machine learning. The method comprises the following steps: acquiring a to-be-decoded cyclic code word, and preprocessing the code word; the method comprises the following steps: constructing a decoding model based on cyclic equivalence of a cyclic code, setting initial parameters of the decoding model, initializing a parameter matrix of the decoding model according to a representative row determined in a Tanner graph, preprocessing an input code word according to the parameter matrix to obtain an embedded matrix, associating the embedded matrix and the parameter matrix with periodicity of the cyclic code, and decoding the cyclic code. Training the decoding model to obtain an optimized decoding model; the optimized decoding model is used to decode a to-be-decoded code word to obtain a preliminary decoding result; and post-processing the preliminary decoding result to obtain a final decoding result. The decoder provided by the invention not only improves the decoding efficiency, but also shows more excellent performance when processing long code words and complex networks.

The present invention relates to the field of electronic communication technologies, and more specifically, to a method for generating quasi-cyclic hyperelliptic codes. The method includes: S1. Selecting a hyperelliptic curve according to given coding parameters; S2. Generating a divisor on the corresponding curve according to the given coding parameters; S3. Calculating a compact generator matrix by using the hyperelliptic curve and the divisor. The present invention can generate quasi-cyclic codes or cyclic codes of any length by using hyperelliptic curves, and obtain the algebraic geometric expression form of the generated quasi-cyclic codes and the expression form of the compact generator matrix. The present invention establishes a connection between hyperelliptic curves and quasi-cyclic codes, and solves part of the problems of representing quasi-cyclic codes and cyclic codes in algebraic geometric forms. The hyperelliptic quasi-cyclic codes generated by the present invention have a clear algebraic geometric structure, and this structure can be used for decoding methods unique to algebraic geometric codes such as list decoding, thereby improving the error correction ability of channel coding and reducing the storage space of the coding matrix.

The invention discloses a color three-dimensional image zero-watermark processing method based on eight-element matrix factorization, which comprises the following steps of: firstly, cutting square invariant feature region images at the centers of left and right viewpoints of a three-dimensional image, and carrying out non-subsampled dual-tree complex wavelet transform on the invariant feature region images in different channels; averaging the four low-frequency sub-bands obtained by each channel image to obtain a low-frequency mean sub-band, then performing block scrambling on the low-frequency mean sub-band from each channel, selecting a part of sub-blocks to construct an octuple matrix, and performing real number field octuple singular value decomposition on the octuple matrix; obtaining a maximum singular value matrix and then binarizing the maximum singular value matrix to obtain a robust binary feature matrix; and finally, carrying out XOR on the binary watermark which is scrambled and encrypted by the four-wing chaotic system and the cyclic code and the robust binary feature matrix to obtain a zero-watermark image. Before watermark authentication, a KAZE matching algorithm is used to correct left and right viewpoints of a to-be-authenticated stereo image. The method has relatively high robustness on common non-geometric attacks and geometric attacks.

The present disclosure relates to a fault detection method and device, and a computer storage medium, and relates to the technical field of big data or artificial intelligence. The fault detection method comprises: acquiring a plurality of log data, wherein each piece of log data has a position identifier and a data category, and the position identifiers of the plurality of log data reflect the time sequence relationship of the plurality of log data; performing a cyclic code encoding operation according to the position identifier and the data category of each piece of log data to obtain a cyclic code of each piece of log data, wherein the cyclic code comprises a position code corresponding to the position identifier and a category code corresponding to the data category; and determining fault positioning information by using a sequence model according to the cyclic codes of the plurality of log data. According to the present disclosure, rapid and accurate fault detection can be achieved.

The application belongs to the technical field of integrated circuit hardware security, and discloses a dynamic key encryption device and method based on a key check code, which comprises a dynamic key generation module, a trigger signal generation module and a dynamic key check module, an initial key signal is input into the dynamic key generation module, the dynamic key generation module outputs a dynamic key signal to the dynamic key check module, the dynamic key check module acquires an original circuit signal from an original circuit and outputs an encrypted circuit signal to the original circuit, the trigger signal generation module acquires an original circuit state machine signal from the original circuit and outputs a trigger signal to the dynamic key generation module and the dynamic key check module; the application constrains and expands the bit width of an original key by using a check bit, avoids the situation that a solver directly solves one code in a cyclic code and causes the key to be directly cracked, increases the solving space of the solver, and delays the cracking speed of reverse engineering.

The invention relates to the technical field of automatic coding, in particular to a one-object-one-code system-oriented unique code automatic coding method and device, and the method comprises the steps: determining a matched character space according to a unique code character demand parameter and an actual application parameter required by a user, screening out a matched target sub-character space, and carrying out the automatic coding of a unique code. Carrying out cyclic coding operation on current space parameters, parameters of all characters used for constructing a character space and unique code character demand parameters to obtain a character cyclic coding result, obtaining time, an actual application scene and actual use time in combination with corresponding characters, and analyzing to obtain a unique code required by a user; the uniqueness of the unique code is guaranteed from the source, the coding length is reduced, the density of the formed unique code is reduced, and the definition of the jet-printed unique code is guaranteed, so that the scanning accuracy and efficiency of the unique code are improved, and the safety management and control of full-link traceability (traceability) of articles / products based on the jet-printed unique code are improved.

The invention discloses a verifiable secret sharing method based on a cyclic code. The method comprises the following steps: a distributor selects security parameters of a threshold secret sharing scheme; a distributor selects cyclic codes of different dimensions and publicly generates a polynomial; constructing a secret polynomial based on the cyclic code in combination with the shared secret; the distributor selects a polynomial of the cyclic code based on the secret polynomial; each user randomly selects a sub-secret and publishes the sub-secret; the distributor executes a secret distribution algorithm to calculate and obtain a general solution X meeting the congruence equation set, and the X is disclosed; after the users in the authorization subsets are verified through a verification equation constructed based on primitive elements, a unique polynomial is obtained through Lagrange interpolation; and a unique polynomial is obtained by combining the generated polynomial with interpolation, and a secret polynomial is obtained through calculation so as to recover and obtain the shared secret. The method supports the repeated use of the sub-secrets when the user joins in and quits from the scene in real time.

A method for cyclic code encoding includes: generating, based on a first symbol sequence related to a first part of symbols in the K payload symbols, a first parity sequence corresponding to the first symbol sequence; generating, based on a second symbol sequence related to a second part of symbols in the K payload symbols, a second parity sequence corresponding to the second symbol sequence, where the first part of symbols are different from the second part of symbols; and generating the (N−K) parity symbols based on the first parity sequence and the second parity sequence.

The invention relates to a friendly quasi-cyclic LDPC (Low Density Parity Check) code high-speed decoder message storage structure realized by an FPGA (Field Programmable Gate Array), which comprises a message quantization coding module, the output end of the message quantization coding module is electrically connected with a multi-mode message splicing engine module, and the output end of the multi-mode message splicing engine module is electrically connected with a layered reconfigurable storage control module. According to the method, firstly, traditional fixed quantization is improved into dynamic precision adjustment of signal-to-noise ratio self-adaption, fine quantization is kept in a critical judgment area, then, a hierarchical storage organization method is put forward, the access efficiency is improved through address compression and conflict arbitration, and finally, a resource conversion mechanism is established, so that storage optimization benefits are directly converted into parallel processing capacity, and the storage optimization efficiency is improved. The whole system realizes seamless cooperation among the modules through a special handshake signal, improves the resource utilization rate and energy efficiency ratio of the FPGA on the premise of ensuring decoding performance, and is suitable for high-speed mobile communication and other application scenes with strict requirements on real-time performance.

This invention discloses a mapping-guided fuzzing method for loop code, applied in the field of software testing. The method includes: continuously mutating test cases, inputting them into a test case queue, sending them to the program under test (CUPT) with instrumented loop code structures, and outputting a coverage statistics table when the fuzzing termination condition is met; training a deep learning model and back-calculating the weighted distance sum to construct and output a mapping relationship between the byte sequences of test cases and the coverage of the loop code structure; based on the mapping relationship, assigning mutation probabilities to the corresponding byte sequences in the test cases corresponding to the loop code structure coverage and performing mutations to generate child test cases, which are then used as input to the CUPT for fuzzing until the fuzzing termination condition is met, and outputting a fuzzing report. This method mutates the byte sequences of test cases based on mapping relationships, enabling the targeted generation of test cases that improve the coverage of loop code results.

An underground slurry communication transmission method belongs to the technical field of petroleum drilling engineering, adopts a cyclic PN sequence for information transmission, and comprises the following steps: 1) generating a group of cyclic PN sequences; (2) at a transmitting end, signals collected underground are mapped to a cyclic PN sequence through a mapping rule, an underground valve is controlled through the cyclic PN sequence to generate pulses, and the pulses are transmitted through a mud medium; and 3) at a receiving end, constructing a cyclic PN sequence receiving system, performing synchronization through a detection means in a matrix form to obtain synchronous bias, performing cyclic correlation operation on a signal and the converted cyclic PN sequence, and resolving information sent by a transmitting end. According to the invention, the cyclic PN sequence is adopted to replace the traditional Marry coding, the defect of low information rate of the traditional coding mode is overcome, and the cyclic PN code can effectively reduce the error rate in the signal transmission process; in the synchronization process, a detection means in a matrix form is adopted, the synchronization accuracy is improved, and it is ensured that underground signals can be accurately and efficiently transmitted back to the ground.

The present invention discloses a method and system for constructing a quasi-cyclic LDPC code based on a position function, wherein the method comprises: determining an expansion factor L and a cyclic shift value matrix size γ×ρ of the quasi-cyclic LDPC code according to code parameters of the quasi-cyclic LDPC code to be constructed; defining a position function f(i, j); constructing a cyclic shift value matrix with a size of L×L according to the expansion factor L and the position function f(i, j); screening ρ columns from a matrix P according to a ρ value and the matrix to obtain a cyclic shift value matrix P1 with a size of L×ρ; screening γ rows from the matrix P1 according to a γ value and the matrix P1 to obtain a cyclic shift value matrix P2 with a size of γ×ρ; replacing the 1-1 element in the matrix P2 with an all-zero matrix with a size of L×L, and replacing the other elements p i,j Replaced by the corresponding cyclic shift matrix I(p i,j ), a parity check matrix H of size γL × ρL is obtained. The quasi-cyclic LDPC code defined by this parity check matrix is ​​the desired quasi-cyclic LDPC code. The present invention primarily solves the problems of high complexity and difficulty in constructing quasi-cyclic LDPC codes in the prior art.

The invention relates to a method for encoding at least one block of source data, generating at least one codeword of size, where an integer expansion factor, said method implementing a step of encoding (53) said source data using a parity matrix of size. According to the invention, the parity matrix is obtained (52) from a modified basis matrix of size by replacing each element of the modified basis matrix of size with an expansion matrix of size, the modified basis matrix being represented in Form (I). The extension matrix includes at least two row blocks, each row block including the same number of rows, each row block including a diagonal matrix.

The embodiment of the invention provides a data processing method. The method can be applied to a first communication device. A first communication device may acquire a first FEC codeword transmitted by a second communication device. The first communication device does not decode the first FEC codeword according to a traditional FEC decoding mode, but decodes the first FEC codeword according to a first distribution relation. Wherein the first distribution relation is used for indicating the distribution relation between the first error correction capability and the first error detection capability for processing the first FEC code word. The first error correction capability indicates that the maximum error symbol number in the cyclic code codeword can be corrected, and the first error detection capability indicates that the maximum error symbol number in the cyclic code codeword can be detected. In other words, in the embodiment of the invention, the error correction capability and the error detection capability for decoding the cyclic code word can be flexibly allocated, so that the performance provided by the FEC technology can meet requirements.

Provided in the embodiments of the present application is a data processing method. The method may be applied to a first communication apparatus. The first communication apparatus may acquire a first FEC codeword which is sent by a second communication apparatus. The first communication apparatus does not decode the first FEC codeword in a traditional FEC decoding manner, but decodes the first FEC codeword on the basis of a first allocation relationship, wherein the first allocation relationship is used for indicating an allocation relationship between a first error correction capability and first error detection capability for processing of the first FEC codeword. The first error correction capability indicates the maximum number of error symbols that can be corrected in a cyclic code codeword, and the first error detection capability indicates the maximum number of error symbols that can be detected in the cyclic code codeword. In other words, in the embodiments of the present application, an error correction capability and error detection capability for decoding cyclic code codewords can be flexibly allocated, thereby enabling the performance provided by an FEC technique to meet requirements.

The invention provides an MDS symbol code matching construction method based on a single cyclic code, and belongs to the technical field of coding theories. According to the invention, the code length of a single cyclic code is selected; generating a polynomial according to the selected code length, and selecting a root of the polynomial; and solving an equation set corresponding to the selected code length and root, and excluding specific code words to construct three types of different MDS symbol codes. According to the method, the MDS symbol pair code can be effectively designed under the condition that the code length is fixed, and the MDS symbol pair code has a relatively large minimum symbol pair distance; and meanwhile, under the condition of the same minimum pair distance, a longer code length can be achieved through design, so that the fault tolerance and the repair efficiency are improved.

The application discloses a cyclic code test data generation method based on deep learning fuzzy testing, comprising the following steps: guiding the selection of cyclic code seed data with high uncertainty by using the output uncertainty of cyclic code on a deep learning model; designing nine kinds of mutation rules to realize the mutation of cyclic code of different types; analyzing the correlation degree of each neuron and the error decision logic of the deep learning model; taking the maximum neuron coverage rate and the number of error behaviors as the joint optimization target, modeling the optimization target, taking the derivative of the target function as the gradient, selecting the mutation rule to mutate the seed, and using the gradient to iteratively mutate; realizing the mutation of the selected cyclic code seed data to complete the generation of cyclic code test data. The application uses the classification output probability of cyclic code on a deep learning model and related neuron information to design an optimization target, so as to effectively guide the mutation of cyclic code.

The invention discloses a coding and decoding method and system based on cyclic code error correction. The method comprises the following steps: selecting a union of a corresponding circle coset based on the code length of a cyclic code; constructing a corresponding generator polynomial according to the coset of the sub-circle cosets; the sending end converts a signal to be transmitted into a code word based on the generator polynomial, and transmits the code word to a receiving end through a satellite channel; receiving data by a receiving end, and obtaining a syndrome according to the generator polynomial; and judging whether the syndrome is zero or not, if not, entering an error correction process, and if yes, directly decoding to obtain a transmission signal. According to the method, the special cyclic code and the BM algorithm are combined, the error correction amount of the signal after transmission interference is improved through the construction of the special cyclic code, the error correction efficiency is improved by adopting the BM algorithm, and high-efficiency and high-quality error correction is performed on the transmission data; and the constructed cyclic code ensures the reliability of the data in a long-distance and high-noise environment through efficient error correction capability.

The invention discloses a two-stage embedded ciphertext domain reversible information hiding method, and belongs to the technical field of information hiding. A pixel prediction redundant space is improved by improving a median edge detector (PMED), embedding and share segmentation of initial information by a task distributor are realized in combination with polynomial secret sharing, secondary embedding is performed in a ciphertext share by using a (7, 4) cyclic code, and the problems of low embedding capacity and limited application scenarios of a traditional scheme are solved. Experimental results show that the method has good performance in the aspects of embedding rate, safety, reversibility, calculation complexity and the like.

The invention relates to a parallel decoding method and device for a quasi-cyclic LDPC (Low Density Parity Check) code based on FPGA (Field Programmable Gate Array). The method comprises the following steps: determining the size and code length of a quasi-cyclic submatrix and the degree of parallelism of parallel processing node updating; sequentially storing data updated by the nodes in the iteration process into the RAM unit by taking the parallelism degree as the block size; the depth of each RAM unit is obtained by dividing the size of the quasi-cyclic submatrix by the degree of parallelism, and the number of the RAM units is obtained by dividing the code length by the size of the quasi-cyclic submatrix; information to be decoded is extracted through interception and recombination, and iterative decoding is carried out with the degree of parallelism; and stopping iteration when the number of iterations reaches the maximum number or verification is passed, and outputting a decoding result. By adopting the method, the decoding applicability can be improved.

The embodiment of the invention provides a decoding verification method and device, a storage medium and an electronic device. The method comprises the following steps: determining the number of different sign bits of code word sign bits of an original code word after Mth decoding iteration and code word sign bits of the original code word after Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; and under the condition that the first number is smaller than a preset verification threshold value, decoding verification is performed on the code word information of the Nth decoding iteration. Through the embodiment of the invention, the problem of high chip power consumption of a decoding algorithm of the quasi-cyclic LDPC code in the related technology can be solved, and the effect of saving the decoding power consumption of the quasi-cyclic LDPC code is achieved.

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

The present invention relates to a digital image processor tracking capability detection device, which belongs to the field of image processing technology and solves the problems of limited efficiency and accuracy of data processing and arbitration systems and poor data synchronization in existing technologies related to the tracking capability detection of optical measurement equipment. The present invention includes: a multi-target image source board, which generates multi-target images with superimposed information, and transmits them to a host computer and a digital image processor to be detected, respectively, and outputs the superimposed information to a tracking capability arbitrator; the tracking capability arbitrator solves the cyclic code and target miss distance in the collected superimposed information, judges the tracking capability of the digital image processor based on the solution result, obtains arbitration information and sends it to the host computer; the host computer integrates and visualizes the multi-target images and arbitration information. The present invention improves the efficiency and accuracy of data processing and arbitration, improves the stability and reliability of the detection device, and at the same time, the data transmission is complete and accurate.