28 results about "Cyclic code" patented technology

Provided is a communication system based on end-to-end data encryption. The system includes a domain controller, an actuator, and a sensor. The sensor is configured to sense vehicle state information and transmit the vehicle state information as sensed to the domain controller through an end-to-end communication protection protocol; and the domain controller is configured to acquire a control instruction based on the vehicle state information as received, and transmit a corresponding control instruction to a corresponding actuator through the end-to-end communication protection protocol. The end-to-end communication protection protocol is additionally provided with a cyclic code that is variable and configured to encrypt information for communication.

Systems, apparatuses and methods provide technology that identifies a codeword associated with a fluid cooling system and a network system, generates a status update with the network system, embeds the codeword as a repeating cyclic codeword in a message containing the status update, transmits the message from the network system to the fluid cooling system over a data link, receives the message at the fluid cooling system, and determines, with the fluid cooling system, whether interference is inserted into the message based on the repeating cyclic codeword in the message.

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

The invention discloses a color three-dimensional image zero-watermark processing method based on eight-element matrix factorization, which comprises the following steps of: firstly, cutting square invariant feature region images at the centers of left and right viewpoints of a three-dimensional image, and carrying out non-subsampled dual-tree complex wavelet transform on the invariant feature region images in different channels; averaging the four low-frequency sub-bands obtained by each channel image to obtain a low-frequency mean sub-band, then performing block scrambling on the low-frequency mean sub-band from each channel, selecting a part of sub-blocks to construct an octuple matrix, and performing real number field octuple singular value decomposition on the octuple matrix; obtaining a maximum singular value matrix and then binarizing the maximum singular value matrix to obtain a robust binary feature matrix; and finally, carrying out XOR on the binary watermark which is scrambled and encrypted by the four-wing chaotic system and the cyclic code and the robust binary feature matrix to obtain a zero-watermark image. Before watermark authentication, a KAZE matching algorithm is used to correct left and right viewpoints of a to-be-authenticated stereo image. The method has relatively high robustness on common non-geometric attacks and geometric attacks.

The present disclosure relates to a fault detection method and device, and a computer storage medium, and relates to the technical field of big data or artificial intelligence. The fault detection method comprises: acquiring a plurality of log data, wherein each piece of log data has a position identifier and a data category, and the position identifiers of the plurality of log data reflect the time sequence relationship of the plurality of log data; performing a cyclic code encoding operation according to the position identifier and the data category of each piece of log data to obtain a cyclic code of each piece of log data, wherein the cyclic code comprises a position code corresponding to the position identifier and a category code corresponding to the data category; and determining fault positioning information by using a sequence model according to the cyclic codes of the plurality of log data. According to the present disclosure, rapid and accurate fault detection can be achieved.

The application belongs to the technical field of integrated circuit hardware security, and discloses a dynamic key encryption device and method based on a key check code, which comprises a dynamic key generation module, a trigger signal generation module and a dynamic key check module, an initial key signal is input into the dynamic key generation module, the dynamic key generation module outputs a dynamic key signal to the dynamic key check module, the dynamic key check module acquires an original circuit signal from an original circuit and outputs an encrypted circuit signal to the original circuit, the trigger signal generation module acquires an original circuit state machine signal from the original circuit and outputs a trigger signal to the dynamic key generation module and the dynamic key check module; the application constrains and expands the bit width of an original key by using a check bit, avoids the situation that a solver directly solves one code in a cyclic code and causes the key to be directly cracked, increases the solving space of the solver, and delays the cracking speed of reverse engineering.

The invention relates to the technical field of automatic coding, in particular to a one-object-one-code system-oriented unique code automatic coding method and device, and the method comprises the steps: determining a matched character space according to a unique code character demand parameter and an actual application parameter required by a user, screening out a matched target sub-character space, and carrying out the automatic coding of a unique code. Carrying out cyclic coding operation on current space parameters, parameters of all characters used for constructing a character space and unique code character demand parameters to obtain a character cyclic coding result, obtaining time, an actual application scene and actual use time in combination with corresponding characters, and analyzing to obtain a unique code required by a user; the uniqueness of the unique code is guaranteed from the source, the coding length is reduced, the density of the formed unique code is reduced, and the definition of the jet-printed unique code is guaranteed, so that the scanning accuracy and efficiency of the unique code are improved, and the safety management and control of full-link traceability (traceability) of articles / products based on the jet-printed unique code are improved.

The invention discloses a verifiable secret sharing method based on a cyclic code. The method comprises the following steps: a distributor selects security parameters of a threshold secret sharing scheme; a distributor selects cyclic codes of different dimensions and publicly generates a polynomial; constructing a secret polynomial based on the cyclic code in combination with the shared secret; the distributor selects a polynomial of the cyclic code based on the secret polynomial; each user randomly selects a sub-secret and publishes the sub-secret; the distributor executes a secret distribution algorithm to calculate and obtain a general solution X meeting the congruence equation set, and the X is disclosed; after the users in the authorization subsets are verified through a verification equation constructed based on primitive elements, a unique polynomial is obtained through Lagrange interpolation; and a unique polynomial is obtained by combining the generated polynomial with interpolation, and a secret polynomial is obtained through calculation so as to recover and obtain the shared secret. The method supports the repeated use of the sub-secrets when the user joins in and quits from the scene in real time.

The invention relates to a friendly quasi-cyclic LDPC (Low Density Parity Check) code high-speed decoder message storage structure realized by an FPGA (Field Programmable Gate Array), which comprises a message quantization coding module, the output end of the message quantization coding module is electrically connected with a multi-mode message splicing engine module, and the output end of the multi-mode message splicing engine module is electrically connected with a layered reconfigurable storage control module. According to the method, firstly, traditional fixed quantization is improved into dynamic precision adjustment of signal-to-noise ratio self-adaption, fine quantization is kept in a critical judgment area, then, a hierarchical storage organization method is put forward, the access efficiency is improved through address compression and conflict arbitration, and finally, a resource conversion mechanism is established, so that storage optimization benefits are directly converted into parallel processing capacity, and the storage optimization efficiency is improved. The whole system realizes seamless cooperation among the modules through a special handshake signal, improves the resource utilization rate and energy efficiency ratio of the FPGA on the premise of ensuring decoding performance, and is suitable for high-speed mobile communication and other application scenes with strict requirements on real-time performance.

This invention discloses a mapping-guided fuzzing method for loop code, applied in the field of software testing. The method includes: continuously mutating test cases, inputting them into a test case queue, sending them to the program under test (CUPT) with instrumented loop code structures, and outputting a coverage statistics table when the fuzzing termination condition is met; training a deep learning model and back-calculating the weighted distance sum to construct and output a mapping relationship between the byte sequences of test cases and the coverage of the loop code structure; based on the mapping relationship, assigning mutation probabilities to the corresponding byte sequences in the test cases corresponding to the loop code structure coverage and performing mutations to generate child test cases, which are then used as input to the CUPT for fuzzing until the fuzzing termination condition is met, and outputting a fuzzing report. This method mutates the byte sequences of test cases based on mapping relationships, enabling the targeted generation of test cases that improve the coverage of loop code results.

An underground slurry communication transmission method belongs to the technical field of petroleum drilling engineering, adopts a cyclic PN sequence for information transmission, and comprises the following steps: 1) generating a group of cyclic PN sequences; (2) at a transmitting end, signals collected underground are mapped to a cyclic PN sequence through a mapping rule, an underground valve is controlled through the cyclic PN sequence to generate pulses, and the pulses are transmitted through a mud medium; and 3) at a receiving end, constructing a cyclic PN sequence receiving system, performing synchronization through a detection means in a matrix form to obtain synchronous bias, performing cyclic correlation operation on a signal and the converted cyclic PN sequence, and resolving information sent by a transmitting end. According to the invention, the cyclic PN sequence is adopted to replace the traditional Marry coding, the defect of low information rate of the traditional coding mode is overcome, and the cyclic PN code can effectively reduce the error rate in the signal transmission process; in the synchronization process, a detection means in a matrix form is adopted, the synchronization accuracy is improved, and it is ensured that underground signals can be accurately and efficiently transmitted back to the ground.

The present invention discloses a method and system for constructing a quasi-cyclic LDPC code based on a position function, wherein the method comprises: determining an expansion factor L and a cyclic shift value matrix size γ×ρ of the quasi-cyclic LDPC code according to code parameters of the quasi-cyclic LDPC code to be constructed; defining a position function f(i, j); constructing a cyclic shift value matrix with a size of L×L according to the expansion factor L and the position function f(i, j); screening ρ columns from a matrix P according to a ρ value and the matrix to obtain a cyclic shift value matrix P1 with a size of L×ρ; screening γ rows from the matrix P1 according to a γ value and the matrix P1 to obtain a cyclic shift value matrix P2 with a size of γ×ρ; replacing the 1-1 element in the matrix P2 with an all-zero matrix with a size of L×L, and replacing the other elements p i,j Replaced by the corresponding cyclic shift matrix I(p i,j ), a parity check matrix H of size γL × ρL is obtained. The quasi-cyclic LDPC code defined by this parity check matrix is ​​the desired quasi-cyclic LDPC code. The present invention primarily solves the problems of high complexity and difficulty in constructing quasi-cyclic LDPC codes in the prior art.

The invention relates to a method for encoding at least one block of source data, generating at least one codeword of size, where an integer expansion factor, said method implementing a step of encoding (53) said source data using a parity matrix of size. According to the invention, the parity matrix is obtained (52) from a modified basis matrix of size by replacing each element of the modified basis matrix of size with an expansion matrix of size, the modified basis matrix being represented in Form (I). The extension matrix includes at least two row blocks, each row block including the same number of rows, each row block including a diagonal matrix.

The application discloses a cyclic code test data generation method based on deep learning fuzzy testing, comprising the following steps: guiding the selection of cyclic code seed data with high uncertainty by using the output uncertainty of cyclic code on a deep learning model; designing nine kinds of mutation rules to realize the mutation of cyclic code of different types; analyzing the correlation degree of each neuron and the error decision logic of the deep learning model; taking the maximum neuron coverage rate and the number of error behaviors as the joint optimization target, modeling the optimization target, taking the derivative of the target function as the gradient, selecting the mutation rule to mutate the seed, and using the gradient to iteratively mutate; realizing the mutation of the selected cyclic code seed data to complete the generation of cyclic code test data. The application uses the classification output probability of cyclic code on a deep learning model and related neuron information to design an optimization target, so as to effectively guide the mutation of cyclic code.

The invention discloses a two-stage embedded ciphertext domain reversible information hiding method, and belongs to the technical field of information hiding. A pixel prediction redundant space is improved by improving a median edge detector (PMED), embedding and share segmentation of initial information by a task distributor are realized in combination with polynomial secret sharing, secondary embedding is performed in a ciphertext share by using a (7, 4) cyclic code, and the problems of low embedding capacity and limited application scenarios of a traditional scheme are solved. Experimental results show that the method has good performance in the aspects of embedding rate, safety, reversibility, calculation complexity and the like.

The invention relates to a parallel decoding method and device for a quasi-cyclic LDPC (Low Density Parity Check) code based on FPGA (Field Programmable Gate Array). The method comprises the following steps: determining the size and code length of a quasi-cyclic submatrix and the degree of parallelism of parallel processing node updating; sequentially storing data updated by the nodes in the iteration process into the RAM unit by taking the parallelism degree as the block size; the depth of each RAM unit is obtained by dividing the size of the quasi-cyclic submatrix by the degree of parallelism, and the number of the RAM units is obtained by dividing the code length by the size of the quasi-cyclic submatrix; information to be decoded is extracted through interception and recombination, and iterative decoding is carried out with the degree of parallelism; and stopping iteration when the number of iterations reaches the maximum number or verification is passed, and outputting a decoding result. By adopting the method, the decoding applicability can be improved.

The embodiment of the invention provides a decoding verification method and device, a storage medium and an electronic device. The method comprises the following steps: determining the number of different sign bits of code word sign bits of an original code word after Mth decoding iteration and code word sign bits of the original code word after Nth decoding iteration as a first number; wherein M is an integer greater than or equal to 2, N is an integer greater than 2, and M is less than N; and under the condition that the first number is smaller than a preset verification threshold value, decoding verification is performed on the code word information of the Nth decoding iteration. Through the embodiment of the invention, the problem of high chip power consumption of a decoding algorithm of the quasi-cyclic LDPC code in the related technology can be solved, and the effect of saving the decoding power consumption of the quasi-cyclic LDPC code is achieved.

A method, computer program product, and computing system for generating first encoded data by performing a first encoding of data included within each of a plurality of memory dies of a memory module using an exclusive-or (XOR) encoding process. Second encoded data is generated by performing a second encoding of the data included within each of the plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on the data included within each of the plurality of memory dies of the memory module using the first encoded data, the second encoded data, an XOR decoding process, and a cyclic code error correction process.

The present disclosure provides a processing method for loop code, relates to the technical field of artificial intelligence, and particularly relates to the chip technical field and the storage technical field. A specific implementation scheme is as follows: in response to determining that a total data amount of a plurality of variables of a loop code block is greater than an available storage space capacity of a local storage unit, storing a plurality of target variables in the plurality of variables to a global storage unit, wherein the loop code block comprises a plurality of code segments; in response to determining that a first code segment in the plurality of code segments is executed, a first target variable of the first code segment in the plurality of target variables is stored in the global storage unit, and there is an idle first cache space in the local storage unit, storing the first target variable of the first code segment to the idle first cache space, so as to execute the first code segment based on the first target variable in the first cache space in the execution process of the loop code block. The present disclosure also provides an apparatus for loop code, an electronic device and a storage medium.

The invention discloses a TDCS-OFDM covert communication method and equipment, and relates to the technical field of communication. The method comprises the following steps: sampling an electromagnetic environment to generate a primary function; carrying out coding interleaving on transform domain communication system TDCS information needing to be communicated; modulating the coded and interleaved TDCS data by using cyclic code shift keying (CCSK) to generate a frequency domain TDCS signal loaded on a first subcarrier, the first subcarrier being a subcarrier within an available spectral range determined based on a primary function; carrying out coding interleaving on orthogonal frequency division multiplexing (OFDM) information needing to be communicated; performing quadrature amplitude modulation on the coded and interleaved OFDM information to generate a frequency domain OFDM signal loaded on a second subcarrier, wherein the second subcarrier is in an available spectral range and is different from the first subcarrier; and sequentially performing frequency domain synthesis, inverse fast Fourier transform and cyclic prefix addition on the frequency domain TDCS signal and the frequency domain OFDM signal to form a TDCS-OFDM signal. According to the invention, the communication rate and the anti-interception capability of covert communication are improved.

A method, computer program product, and computing system for generating first encoded data by performing a first encoding on data included within each of a plurality of memory dies of a memory module using an XOR encoding process. Second encoded data is generated by performing second encoding on data included within each of a plurality of memory dies of the memory module and the first encoded data using a cyclic code encoding process. Error correction is performed on data included within each of a plurality of memory dies of the memory module using the first encoded data, the second encoded data, the XOR decoding process, and the cyclic code error correction process.

The invention discloses a multi-rate network data transmission method and system based on a permutation method, and belongs to the technical field of channel coding. The method comprises the steps that a basis matrix is designed according to an expansion factor of the quasi-cyclic LDPC code, elements of the basis matrix are generated by a position function, and the position function is defined as a mathematical function on an integer pair set; row and column permutation optimization is carried out on the basis matrix and comprises row permutation optimization and column permutation optimization, and row and column permutation aims at maximizing girth and minimizing the shortest ring number; based on the optimized basis matrix, generating a check matrix of the multi-rate quasi-cyclic LDPC code, and encoding and decoding data; and realizing data transmission according to the dynamic adaptation of the code rate. According to the method, multi-rate switching is supported through the unified basis matrix template, so that the storage overhead is reduced; linear complexity coding is realized by using a quasi-cyclic structure, and hardware implementation is friendly; the row and column permutation optimization ensures the girth maximization, and the decoding performance is improved; and the requirements of low time delay and high reliability are met.

The application provides a fast target recognition method based on an optoelectronic hybrid neural network, and solves the problem of low information acquisition efficiency of a target recognition system, and comprises the following steps: an optical network is designed to realize cyclic coding single-pixel detection, and an electrical network is simultaneously constructed to decode the single-pixel detection signal and acquire object information; a data set used for training the hybrid neural network is selected according to an application scene; the optoelectronic hybrid neural network is trained by using the acquired data set; a cyclic coding mask obtained by training is processed, and a single-pixel detection system based on the coding mode is built; object information is collected by a single-pixel detector after being modulated by the cyclic coding mask; and finally, the pre-trained electrical neural network is used to recognize the object information from the detection signal. The application cooperatively uses the cyclic coding single-pixel detection method and the artificial intelligence technology, and can realize accurate prediction of the category of a high-speed moving object to be detected in a special waveband and a weak light environment.

This invention relates to the generation of a set of raised quasi-cyclic LDPC codes. Methods for generating codes, methods for encoding and decoding data, and encoders and decoders for performing encoding and decoding are disclosed. In an embodiment, the method for raising subcodes from a base code for encoding and decoding data includes determining a single combination of a cycle size, a raising function, and a label base matrix (PCM) based on information length and coding rate using data stored in a raising table. The raising table is defined during the code generation phase. The method also includes calculating multiple shifts for the subcodes. Each shift is calculated by applying the raising function to the label base matrix (PCM) using an index defined with the cycle size, and the resulting subPCM is used to encode or decode data.

The invention discloses a polygonal quasi-cyclic LDPC code coding method and device based on a finite field, and the method comprises the steps: determining a basis matrix according to a target code parameter, the basis matrix at least comprises a non-zero element with an element value greater than 1, and is used for indicating that a polygonal cyclic square matrix with the row-column weight greater than 1 needs to be constructed; generating an initial matrix based on the finite field, and mapping elements of the initial matrix into cyclic shift values; carrying out composite operation on the shift values by taking the basis matrix as guidance, and distributing the plurality of shift values to specific positions; and finally, according to the allocated shift value set and the expansion factor, a final polygonal quasi-cyclic LDPC code check matrix is constructed. According to the method, a polygonal structure is integrated into a quasi-cyclic framework, the ring distribution of code words is effectively optimized while the advantage that low-coding-complexity hardware is easy to implement is kept, and compared with a traditional single-side quasi-cyclic LDPC code coding method, the error flat layer is remarkably reduced, and the decoding convergence speed is higher.

The invention relates to a method for encoding at least one block of source data, generating at least one codeword of size, where an integer expansion factor, said method implementing a step of encoding (53) the source data using a parity check matrix of size. According to the invention, the parity check matrix is obtained (52) from a basis matrix represented in the form of (I) by replacing each element of a size basis matrix with an expansion matrix of size. The extension matrix comprises at least two consecutive row blocks, each row block comprising a different number of rows, the number being equal to a prime number or a square of a prime number, each row block comprising at least one instance of a diagonal matrix.

The invention relates to a rate compatible LDPC (Low Density Parity Check) code construction and quasi-cyclic expansion method based on sequential deletion, belonging to the technical field of atmosphere laser communication, the method adopts a progressive edge growth algorithm to construct a quasi-cyclic LDPC code with good sparseness and large girth in the initial stage, and then utilizes statistics and ascending sorting of variable node degrees to construct a quasi-cyclic LDPC code with good sparseness and large girth. Deleting the variable nodes with lower degrees in sequence to realize dynamic adjustment of the original code rate; next, carrying out structure adjustment and reconstruction on the deleted check matrix, and forming a rate compatible LDPC code by redistributing a connection relation of deleted nodes and optimizing row weight distribution; according to the method, on the premise that the original code rate is not changed, through combination of sequential deletion and quasi-cyclic expansion, the multi-code-rate requirement is flexibly met, meanwhile, the error correction performance and hardware friendliness are kept to the maximum extent, and the method is suitable for high-reliability communication scenes such as deep space communication and satellite links.