19results about "Burst error correction" patented technology

Enhanced reliable communications systems, methods, computer program products, and integrated circuits include streaming codes for partial burst and guardspaces and synergized compression. An FEC encoder can generate two or more types of parity symbols to address partial burst and guardspace losses. An FEC encoder can utilize information from a data compressor to make frame splitting, parity symbol generation, and / or packetizing decisions. A data compressor can use information from an FEC encoder to make data compression decisions. Aspects of an FEC encoder and / or data compressor can be trained using machine learning, including reinforcement learning. Multimodal operation provides flexibility for dynamically reacting to changing communication conditions.

An integrated circuit includes an ECC encoder circuit configured to operate an H matrix on transmission data, to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity to detect and correct an error in the reception data. A data portion of the H matrix is divided into N groups, and each of the N groups includes a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group. The group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted.

The application discloses an encoder, an encoding method and a chip, relates to the technical field of encoding, and discloses the following technical scheme: in the scene of large bandwidth and high parallelism input, a feedback loop in the encoder cannot produce a technical defect that cannot converge in time sequence. The encoder comprises a feedforward module, which is used for receiving to-be-encoded data with a parallelism of n symbols per beat, and calculating a single-beat polynomial corresponding to a current beat in a finite field according to symbols in the to-be-encoded data received in the current beat. A feedback module is used for receiving the single-beat polynomial corresponding to the current beat output by the feedforward module, and calculating a second polynomial in a finite field according to the single-beat polynomial corresponding to the current beat and a first polynomial representing symbols received in historical beats, wherein the second polynomial is used for determining a target polynomial representing to-be-encoded data, the target polynomial is used for generating a check sequence of the to-be-encoded data, and thus a codeword obtained after the to-be-encoded data is encoded by a forward error correction encoding mode is obtained.

An integrated circuit includes an ECC encoder circuit configured to operate an H matrix on transmission data, to generate a transmission parity to be transmitted together with the transmission data, the transmission parity corresponding to the transmission data; and an ECC decoder circuit configured to operate the H matrix on reception data and a reception parity to detect and correct an error in the reception data. A data portion of the H matrix is divided into N groups, and each of the N groups includes a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within a corresponding group. The group matrix portion is used by k group matrices that circulate in the N groups, and each time the k group matrices circulate one round, positions of the k group matrices inserted in groups are shifted.

Techniques for an optical receiver are disclosed. The optical receiver may include an optical digital signal processing (ODSP) device. The ODSP device may include: a photodiode operable to convert an optical signal into an electrical signal; a digital signal processor operable to generate a digital signal based on the electrical signal; a quantization component operable to generate a quantized output signal based on the digital signal; and a processing device. The processing device is operable to: measure one or more signal statistics of the digital signal; and identifying one or more quantization thresholds, wherein the one or more quantization thresholds are calculated based on the one or more signal statistics.

Described herein are systems, methods, and other techniques for performing forward error correction in a communication system. A set of data blocks to be transmitted over a wireless channel are received. Rows of a flexible matrix are formed using the set of data blocks based on arrival times of the set of data blocks, each of the rows corresponding to a different time window. A set of random parity blocks are computed by performing row-wise parity operations on the flexible matrix. A set of burst parity blocks are computed by performing column-wise parity operations on the flexible matrix in accordance with a burst parity computation scheme. The set of data blocks, the set of random parity blocks, and the set of burst parity blocks are transmitted over the wireless channel to a receiver.

This application discloses an encoder, an encoding method, and a chip, relating to the field of encoding technologies. A feedback circuit in the encoder is designed to avoid timing convergence issues when the encoder operates in large-bandwidth and high-parallelism input scenarios. The encoder includes: a feedforward module, configured to receive to-be-encoded data with a parallelism of n symbols per cycle, and perform calculation in a finite field based on a symbol of the to-be-encoded data received in a current cycle, to obtain a single-cycle polynomial corresponding to the current cycle; and a feedback module, configured to receive the single-cycle polynomial corresponding to the current cycle output by the feedforward module, and perform calculation in the finite field based on the single-cycle polynomial corresponding to the current cycle and a first polynomial indicating a symbol received in a historical cycle, to obtain a second polynomial, where the second polynomial is used to determine a target polynomial indicating the to-be-encoded data, and the target polynomial is used to generate a check sequence of the to-be-encoded data, to obtain a codeword obtained by encoding the to-be-encoded data based on a forward error correction encoding scheme.

The present disclosure relates to systems and methods for FGPA-based burst-error performance and optimization of regular and irregular SD-LDPC codes for 50G-PON / 100G-PON and beyond. In particular, the burst-error performance of the regular low-density parity-check (LDPC) code is evaluated and the irregular LDPC code that has been considered for ITU-T's 50G-PON standard via experimental measurements in FPGA. By using intra codeword interleaving and parity-check matrix rearrangement, it is demonstrated that the BER performance can be improved under ˜44-ns-duration burst errors for 50 Gb / s / 100 Gb / s upstream signals.

Enhanced reliable communications systems, methods, computer program products, and integrated circuits include streaming codes for partial burst and guardspaces and synergized compression. An FEC encoder can generate two or more types of parity symbols to address partial burst and guardspace losses. An FEC encoder can utilize information from a data compressor to make frame splitting, parity symbol generation, and / or packetizing decisions. A data compressor can use information from an FEC encoder to make data compression decisions. Aspects of an FEC encoder and / or data compressor can be trained using machine learning, including reinforcement learning. Multimodal operation provides flexibility for dynamically reacting to changing communication conditions.

Described herein are systems, methods, and other techniques for performing forward error correction in a communication system. A set of data blocks to be transmitted over a wireless channel are received. Rows of a flexible matrix are formed using the set of data blocks based on arrival times of the set of data blocks, each of the rows corresponding to a different time window. A set of random parity blocks are computed by performing row-wise parity operations on the flexible matrix. A set of burst parity blocks are computed by performing column-wise parity operations on the flexible matrix in accordance with a burst parity computation scheme. The set of data blocks, the set of random parity blocks, and the set of burst parity blocks are transmitted over the wireless channel to a receiver.

An error correction circuit, including an error correction code (ECC) encoder configured to generate parity data corresponding to main data based on a parity generation matrix, and to output a codeword including the main data and the parity data to a plurality of memory devices; and an ECC decoder configured to: read the codeword from the plurality of memory devices, generate a syndrome corresponding to the codeword based on a parity check matrix, detect an error pattern based on the syndrome, generate a plurality of estimation syndromes corresponding to the error pattern using a plurality of partial submatrices included in the parity check matrix, and correct an error included in the read codeword based on a result of a comparison between the syndrome and the plurality of estimation syndromes.

The application discloses an error capturing circuit and decoding method based on an asymmetric quantum cyclic burst error code. The error capturing circuit can quickly locate error positions by cyclically shifting error accompanying formula, and can correct any burst X error and Z error in the range of decoding length of codeword design. The decoding method based on the asymmetric quantum cyclic burst error code and the error capturing circuit can respectively correct Z error and X error, optimizes decoding performance, fully considers degenerate characteristics in decoding to fully exert the decoding limit of quantum coding theory, and realizes correction of more quantum burst errors under the same code rate.

Described herein are systems, methods, and other techniques for performing forward error correction in a communication system. A set of data blocks to be transmitted over a wireless channel are received. Rows of a flexible matrix are formed using the set of data blocks based on arrival times of the set of data blocks, each of the rows corresponding to a different time window. A set of random parity blocks are computed by performing row-wise parity operations on the flexible matrix. A set of burst parity blocks are computed by performing column-wise parity operations on the flexible matrix in accordance with a burst parity computation scheme. The set of data blocks, the set of random parity blocks, and the set of burst parity blocks are transmitted over the wireless channel to a receiver.

An error correction code (ECC) decoder includes a syndrome generator and a burst error corrector. The syndrome generator generates global syndrome data and local syndrome data using input data and a parity check matrix based on a constacyclic code. The burst error corrector corrects a correctable error included in the input data using the global syndrome data and the local syndrome data. The input data includes a plurality of data bits arranged along a first direction and a second direction. The ECC decoder simultaneously corrects a single burst error and a multi-bit error. The single burst error occurs on two or more symbols arranged along the first direction in the input data, and each symbol includes two or more data bits. The multi-bit error randomly occurs on two or more data bits in the input data.

Described herein are systems, methods, and other techniques for performing forward error correction in a communication system. A set of parity blocks are computed based on a set of data blocks. A set of parity tags are generated for the set of data blocks. The blocks and parity tags are transmitted over the wireless channel from a transmitter to a receiver. A subset of the blocks and parity tags are received at the receiver, the subset including a first and second blocks from the first and second parity groups. A unique positional identifier and a parity position number are determined for the second block based on a parity tag for the second block. A length of the first parity group is computed. It is determined that a missing block from the first parity group has not been received based on the length of the first parity group.

The invention relates to a memory system and an integrated circuit including an ECC circuit. In one embodiment, an integrated circuit includes: an ECC encoder circuit configured to perform an H-matrix operation on transfer data to generate a transfer parity to be transferred with the transfer data, the transfer parity corresponding to the transfer data; and an ECC decoder circuit configured to perform an H-matrix operation on the received data and the received parity to detect and correct errors in the received data. The data portions of the H matrix are divided into N groups, and each of the N groups includes a group matrix portion for distinguishing groups and a non-group matrix portion for distinguishing bits within the corresponding group. The group matrix portion is used by k cyclic group matrices in the N groups, and the positions of the k group matrices inserted into the group are shifted each cycle of the k group matrices.

Described herein are systems, methods, and other techniques for performing forward error correction in a communication system. A set of parity blocks are computed based on a set of data blocks. A set of parity tags are generated for the set of data blocks. The blocks and parity tags are transmitted over the wireless channel from a transmitter to a receiver. A subset of the blocks and parity tags are received at the receiver, the subset including a first and second blocks from the first and second parity groups. A unique positional identifier and a parity position number are determined for the second block based on a parity tag for the second block. A length of the first parity group is computed. It is determined that a missing block from the first parity group has not been received based on the length of the first parity group.

Described herein are systems, methods, and other techniques for performing forward error correction in a communication system. A set of data blocks to be transmitted over a wireless channel are received. Rows of a flexible matrix are formed using the set of data blocks based on arrival times of the set of data blocks, each of the rows corresponding to a different time window. A set of random parity blocks are computed by performing row-wise parity operations on the flexible matrix. A set of burst parity blocks are computed by performing column-wise parity operations on the flexible matrix in accordance with a burst parity computation scheme. The set of data blocks, the set of random parity blocks, and the set of burst parity blocks are transmitted over the wireless channel to a receiver.