This application discloses an
encoder, an encoding method, and a
chip, relating to the field of encoding technologies. A feedback circuit in the
encoder is designed to avoid timing convergence issues when the
encoder operates in large-bandwidth and high-parallelism input scenarios. The encoder includes: a feedforward module, configured to receive to-be-encoded data with a parallelism of n symbols per cycle, and perform calculation in a finite
field based on a symbol of the to-be-encoded data received in a
current cycle, to obtain a single-cycle polynomial corresponding to the
current cycle; and a feedback module, configured to receive the single-cycle polynomial corresponding to the
current cycle output by the feedforward module, and perform calculation in the finite
field based on the single-cycle polynomial corresponding to the current cycle and a first polynomial indicating a symbol received in a historical cycle, to obtain a second polynomial, where the second polynomial is used to determine a target polynomial indicating the to-be-encoded data, and the target polynomial is used to generate a check sequence of the to-be-encoded data, to obtain a codeword obtained by encoding the to-be-encoded data based on a
forward error correction encoding scheme.