260 results about "Burst error" patented technology

Techniques for detecting and correcting burst errors in data bytes formed in a two-level block code structure. A second level decoder uses block level check bytes to detect columns in a two-level block code structure that contain error bytes. The second level decoder generates erasure pointers that identify columns in the two-level block structure effected by burst errors. A first level decoder then uses codeword check bytes to correct all of the bytes in the columns identified by the erasure pointers. The first level decoder is freed to use all of the codeword check bytes only for error byte value calculations. The first level decoder does not need to use any of the codeword check bytes for error location calculations, because the erasure pointers generated by the second level decoder provide all of the necessary error locations. This techniques doubles the error correction capability of the first level decoder.

A data communication apparatus determines whether the error type is a burst error or not based on an error occurrence state of the data received from a data transmitting apparatus and transmits error type-basis error information. The data communication apparatus receives the error type-basis error information and sets the redundancy degree of an FEC processing section based on the error rate of the errors other than a burst error.

Electromagnetic signals for transmitting television and other information more robustly have amplitudes modulated in accordance with a digital signal generated by convolutional interleaving and trellis coding of segments of successive data fields, each of which segments contains a prescribed number of bytes. In improvements of these signals, respective fractional portions of a Reed-Solomon forward-error-correction codeword are transmitted in respective ones of a plurality of the segments of the successive data fields. The respective ones of the plurality of segments are separated from each other within the successive data fields, such that their individual bytes do not interleave with each other after the convolutional interleaving and trellis coding are completed.

A digital phase lock loop circuit including an error generation circuit for generating at least three error signals and a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals. By using at least three error signals, as opposed to just one, the drift in the sampling phase of the recovered clock is easily detected and corrected to reduce burst errors and to improve loss of lock (LOL) performance.

The errors that may occur in transmitted numerical data on a channel affected by burst errors, are corrected via the operations of: ordering the numerical data in blocks each comprising a definite number of data packets; generating for each block a respective set of error-correction packets comprising a respective number of correction packets, the respective number identifying a level of redundancy for correcting the errors; and modifying dynamically the level of redundancy according to the characteristics of the bursts and of the correct-reception intervals between two bursts. Preferential application is on local networks, such as W-LANs for use in the domestic environments.

A disk drive using a read/write channel including an iteration decoder for performing iterative decoding processing is disclosed. The iteration decoder has an RLL error detector for detecting a burst error portion from an LLR group output from the channel decoder, and an LLR adjuster. The LLR adjuster makes adjustment by reducing the value of the LLR group corresponding to the detected burst error portion.

Error bursts are detected and corrected in a communication system using shortened cyclic codes, such as shortened Fire codes. Data is loaded into a first error syndrome register and a second error syndrome register. The data in the registers may be evaluated to determine if the data bits contain a correctable error. Shortened zero bits are shifted into the second error syndrome register. A number of zero bits are shifted into the first error syndrome register to trap an error burst pattern in the data. A determination is made as to the number of zero bits shifted into the second error syndrome register to trap the location of the error burst in the data. Using the number of zero bits shifted into the second error syndrome register and the error burst pattern, the error in the data is located and corrected.

System correcting random and/or burst errors using RS (Reed-Solomon) code, turbo/LDPC (Low Density Parity Check) code and convolutional interleave. A novel approach is presented that combines different coding types within a communication system to perform various types of error correction. This combination of accommodating different coding types may be employed at either end of a communication channel (e.g., at a transmitter end when performing encoding and/or at a receiver end when performing decoding). By combining different coding types within a communication system, the error correcting capabilities of the overall system is significantly improved. The appropriate combination of turbo code and/or LDPC code along with RS code allows for error correction or various error types including random error and burst error (or impulse noise).

A burst error limiting symbol detector system includes a symbol detector circuit responsive to a corrected sample signal for detecting multilevel or multidimensional symbols encoded in the corrected sample signal with reference to a plurality of associated thresholds. A feedback equalizer circuit provides a feedback equalizer signal for cancelling undesired distortion in an input signal. A summing circuit is responsive to the input signal and the feedback equalizer signal to provide the corrected sample signal to the symbol detector circuit. A feedback modification circuit is responsive to the corrected sample being within one of a plurality of valid symbol windows to feed back the detected symbol to the feedback equalizer and is responsive to the corrected sample being within one of plurality of marginal threshold windows to feed back a corresponding intermediate value to the feedback equalizer.

To efficiently transmit frame relay packets between terrestrial frame relay networks (10, 12) over a satellite/wireless network (14), the packets are processed by frame relay processors (16, 18) at both ends of the satellite/wireless network (14). Variable length frame relay packets are segmented into smaller packets called spackets. The system utilizes priority queueing and a scheduler (24) transmits the spackets over the satellite/wireless link. To enhance the quality of the satellite/wireless link, each frame contains a variable number of Reed-Solomon (RS) check bytes used for error correction. Further, several frames are interleaved before transmission over the satellite/wireless link to spread the effect of burst errors over several frames. Additionally, a header compression technique saves bandwidth by compressing a Virtual Circuit (VC) identifier of the frame relay packet into a smaller value and maps the VCs to a value as specified by the size of the compressed VC field.

The present invention relates to a reproducing apparatus which, in a case where a burst error has occurred, corrects an error preceding a synchronization pattern detected thereafter to have less errors. A bit slip judging section81 in a bit slip correcting section 53 calculates a bit slip correction amount and a bit slip correction position on the basis of phase error signals detected by a phase error detecting section 51, synchronization pattern signals detected by a synchronization detecting section 52, reproduced clocks and detected data. A FIFO control section 82 controls a FIFO buffer 83 on the basis of the bit slip correction amount and the bit slip correction position, to perform bit slip correction. As a result, in the case where a burst error has occurred, an error preceding a synchronization pattern detected thereafter is corrected, whereby an error reduction can be implemented. The present invention is applicable to a reproducing apparatus.

The invention discloses an implementation method of a high-speed reed-solomon (RS) codec based on a field programmable gate array (FPGA), comprising FPGA implementation of a high-speed RS (244, 212) coder and FPGA implementation of a high-speed RS (244, 212) decoder. In the invention, the high-speed RS coder is a circuit based on polynomial division, and the high-speed RS decoder is based on three-level pipeline architecture, and dual-clock driving based on clock i_clk and reverse clock i_clk180 is adopted; In addition, based on a common Galois field (GF) multiplying unit, three basic computing units, including a constant coefficient GF multiply-add fused unit, a constant coefficient GF multiplying unit and a dual-clock period controlled GF multiplying unit are provided, thereby greatly improving the computing speed and reducing hardware complexity. The implementation method has the advantages of high supporting throughput rate and strong capacity of correcting burst errors and can be applied to many aspects.

In described embodiments, a Decision Feed Forward Equalizer (DFFE) comprises a hybrid architecture combining features of a Feed Forward Equalizer (FFE) and a Decision Feedback Equalizer (DFE). An exemplary DFFE offers relatively improved noise and crosstalk immunity than an FFE implementation alone, and relatively lower burst error propagation than a DFE implementation alone. The exemplary DFFE is a relatively simple implementation due few or no critical feedback paths, as compared to a DFE implementation alone. The exemplary DFFE allows for a parallel implementation of its DFE elements without an exponential increase in the hardware for higher numbers of taps. The exemplary DFFE allows for cascading, allowing for progressive improvement in BER, at relatively low implementation cost as a solution to achieve multi-tap DFE performance.

The invention discloses a hybrid spread spectrum communication system based on low density parity code (LDPC) encoding and a method thereof. The problems of leakage capture, high leakage capture probability, slow convergence of a phase-locked loop and low decoding performance of the existing synchronous capture method are mainly solved. The system comprises a transmitting part and a receiving part, wherein the transmitting part is used for carrying out pretreatment on original information; the pretreatment data are subjected to frequency hopping treatment and transmitted after being modulated and filtered by a base band; the receiving part is used for obtaining a synchronization point position and a frequency offset value in the received signal through synchronous capture, and intercepting useful data to carry out de-hopping according to the synchronization point position; the base band demodulates and filters; the filtering data are subjected to frequency offset compensation according to the frequency offset value; the data after frequency offset compensation are subjected to dispreading and frequency offset rectification; the frequency offset rectification data are decoded and the decoding result is output. The hybrid spread spectrum communication system has the advantages of being strong in burst error resisting ability, high in real-time synchronization capture speed, high in capture accuracy, high in convergence speed of the phase-locked loop, and good in decoding performance, and can be applied to reliable communication under the condition of very low powder spectral density.

A client for playing a video stream and a method thereof adaptively control the video play in accordance with variable communication environments and the size of the video stream to be transmitted. The client includes a demultiplexer for generating elementary stream (ES) packets by demultiplexing a video stream; a FIFO buffer for temporarily storing the ES packets; a play timing modification unit for reducing a gap of a play time caused by a burst error by modifying time stamps of the ES packets that exist in the FIFO buffer if it is judged that the burst error occurs; and a video decoder for generating an output video by decoding the ES packets of which the time stamps are modified. The client can relatively improve the quality of the video streaming in multimedia communications through a wireless or wire network.

Data to be more robustly transmitted within 8VSB broadcast DTV signals are turbo coded using parallelly concatenated convolutional coding (PCCC) and incorporated within the segments of data fields, the bytes of which are convolutionally interleaved before trellis coding and 8VSB symbol mapping. Packing the PCCC into payload fields of MPEG-2-compatible null data packets and Reed-Solomon coding the packets to generate the segments of data fields, the bytes of which are convolutionally interleaved, conditions legacy DTV receivers to disregard PCCC components not useful to them. Transversal packing turbo-coded Reed-Solomon codewords into the payload fields of MPEG-2-compatible null data packets increases the capability of those turbo-coded Reed-Solomon codewords to overcome burst errors. Repeated transmissions of the transversally packed turbo-coded Reed-Solomon codewords in whole or in part allows them to overcome protracted deep fades encountered during mobile reception of 8VSB DTV signals.

A process and apparatus is described for recovering from optical transmission degradation due to scintillation effects in optical free space. A payload bit stream is encoded into Reed-Solomon codewords. These are fragmented and distributed as interleaved segments over a cell matrix of a SDRAM buffer store which is made large enough to correct a burst error occurring over 20 million consecutive bits. The rate imbalance between conventional read vs. write operations for SDRAM devices, which would otherwise obviate their use in this application by preventing real time operation, is overcome by an address remapping that avoids having to changing page addresses each time SDRAM memory is referenced. The remapping facilitates a more nearly equal allocation of READ overhead and WRITE overhead. An optical communications system employs at both the transmit and receive ends, substantially equivalent SDRAM buffer with address remapping capability.

An error correction algebraic decoder and an associated method correct a combination of a B-byte burst of errors and t-byte random errors in a failed sector, by iteratively adding and removing an erasure (N−B) times until the entire failed sector has been scanned, provided the following inequality is satisfied: (B+2t)≦(R−1), where N denotes the number of bytes, B denotes the length of the burst of errors, t denotes the total number of random errors, and R denotes the number of check bytes in the failed sector. This results in a corrected sector at a decoding latency that is a generally linear function of the number of the check bytes R, as follows: Decoding Latency=5R(N−B).

Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.