41 results about "Turbo coded" patented technology

The invention relates to the technical field of spacecraft satellite-ground communication, and provides a low-earth-orbit satellite communication time delay optimization method and system aiming at the defects that a traditional low-earth-orbit satellite communication satellite system and a satellite communication frame have high time delay and poor real-time communication function. The core of the invention comprises three parts: firstly, an efficient receiving and transmitting end coding and decoding technology: a transmitting end adopts a subblock coding technology of a Turbo code; and a receiving end uses an MAX-Log-MAP algorithm to carry out rapid iterative decoding on the word block code of the Turbo code. And secondly, compressing the user data: carrying out lossless compression on the user data and a satellite communication frame header by using Huffman coding, reducing the transmission data volume, improving the data processing speed, and thus reducing the processing time delay. And finally, simplifying the frame header design: optimizing the frame header of the communication frame so as to reduce the total length of each frame. The method is particularly suitable for communication satellites (the orbit height is less than or equal to 1500km) in a low earth orbit.

The invention discloses an efficient method for realizing Turbo coding by an FPGA (Field Programmable Gate Array), which comprises the following steps of: before data enters a Turbo coding module, firstly introducing a dual-port RAM (Random Access Memory) and a rate grouping processing module, preprocessing and reasonably segmenting the data, saving time delay, reducing hardware resource consumption, better adapting to the Turbo coding module, and greatly compressing the processing and queuing time of the data in a Turbo coder; after Turbo coding is completed, serial-to-parallel processing is carried out on coded data, and it is ensured that the coded data can be continuously and stably output in a serial mode. According to the method, the problems that a traditional Turbo encoder is large in encoding delay and large in resource consumption are solved, the operation complexity is low, and the Turbo code can be applied to a new wireless communication system.

The invention discloses a data processing method and device and relates to the technical field of communication. In the method, under the condition that the code length is relatively short, the transmitting end adopts a Polar code encoding mode to encode, and compared with Turbo code encoding, the encoding performance is improved, so that the subsequent communication performance is improved.

The invention relates to a system and a method for optimizing Turbo coding and decoding by a neural network, and belongs to the technical field of crossing of communication technology and artificial intelligence. The system comprises a PL end which adopts a Turbo decoding IP core, supports dynamic configuration of iteration times and LLR scaling factors, and realizes data throughput through an AXI-Stream interface; at the PS end, a Transform model is deployed, and channel feature extraction is realized; the collaboration layer is used for realizing zero-copy data transmission between the PS and the PL; according to the method, a closed-loop optimization mechanism is formed through an end-to-end process of data input, feature extraction, parameter configuration, decoding execution, result verification and performance circulation; the objective of the invention is to realize jumping of decoding performance by dynamically adjusting decoding parameters for channel parameters, realize efficient interaction of decoding at a PS end and a PL end, improve Turbo decoding throughput and significantly improve system BER performance according to adaptive parameter adjustment.

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

An embodiment of the present application provides a component decoding method for a TURBO code, a decoding method for a TURBO code, and related equipment, including: receiving and demodulating data to be decoded according to a scheduling configuration to obtain decoding input data; and calculating the code rate and modulation order of the decoding input data; calculating an adjustment value for the decoding input data and a bit width shift value of a decoder internal posterior probability branch metric parameter according to the modulation order and code rate of the decoding input data; adjusting the numerical value of the decoding input data by the adjustment value to obtain first decoding input data; component decoding the first decoding input data to obtain a calculation result of the decoder internal posterior probability branch metric; and shifting the calculation result of the decoder internal posterior probability branch metric by the bit width shift value to obtain a component decoding output value. The method has the beneficial effect of improving decoding performance and is applicable to the technical field of TURBO code decoding.

The invention relates to the technical field of decoding, and discloses a three-code-in-one interpretation method and device of a probability domain based on a storage and calculation integrated device, which can configure a three-code-in-one decoding array comprising an LDPC (Low Density Parity Check) decoding array, a Polar decoding array and a Turbo decoding array on the storage and calculation integrated device based on a target probability graph model corresponding to three error correction codes to be interpreted. According to a probability domain operation mode, determining a state value initial probability of each variable node in each target probability graph model, and using the state value initial probability of each variable node in each target probability graph model and the three-code-in-one decoding array to perform unified interpretation on three to-be-interpreted error correction codes so as to obtain an error correction code interpretation result; according to the invention, unified interpretation of the to-be-interpreted LDPC code, the Polar code and the Turbo code is realized, and unified decoding power consumption of the to-be-interpreted LDPC code, the Polar code and the Turbo code can be effectively reduced.

This invention belongs to the field of wireless communication technology and discloses a selection method for a high-spectrum-efficiency R16QAM (Rateless 16QAM) structured bit selector. First, N information bits are encoded using a 1 / 3 code rate Turbo code to obtain a 3N-length coded bit block to be transmitted. Then, the coded bit block is progressively selected in a structured manner according to the symbol transmission order, and finally transmitted and received in a rateless manner. Specifically, bits are extracted from multiple candidate sub-blocks and recombined to generate structured bit sub-blocks. Multiple bit sub-blocks constitute a single bit block, and different bit blocks are progressively generated. This structured "bit sub-block-bit block-progressive bit block" construction method reintegrates the entire coded bit block to be transmitted into a hierarchical structured block, providing the receiver with iteratively demodulated and decoded multi-dimensional correlation observation information.

The invention provides a turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; partitioning the processed data into blocks; wherein the blocks correspond to different storage units; performing multi-path processing on each block based on each storage unit; wherein the processing is interleaving or de-interleaving. According to the method provided by the invention, the parallel processing of the processing data is realized by partitioning the processing data and then performing multi-path processing on each block, so that the processing time is shortened, and the processing efficiency is improved.

Communication systems and methods are disclosed that utilize Probability Amplitude Shaping (PAS) and Trellis Coded Modulation (TCM) to transmit short block-length messages. While capacity-approaching codes, such as Low Density Parity Check (LDPC) codes, Turbo codes, and Polar codes, can achieve data rates approaching the Shannon limit at large block-lengths, the performance of these codes can deteriorate dramatically at short block-lengths. Communication systems configured in accordance with various embodiments of the invention can utilize classical codes to encode short block-length messages to achieve communication rates exceeding Polyanskiy's Random Coding Union bound. In several embodiments, message bits are transmitted using a TCM system in which message bits that have been previously encoded by an error detection code are encoded using a convolutional code (CC). In a number of embodiments, the error detection code and the CC are obtained via a joint optimization with respect to a Frame Error Rate bound.

The invention relates to the technical field of decoding, and discloses a three-code-in-one interpretation method and device of a logarithm domain based on a storage and calculation integrated device, which can configure a three-code-in-one decoding array comprising an LDPC (Low Density Parity Check) decoding array, a Polar decoding array and a Turbo decoding array on the storage and calculation integrated device based on a target probability graph model corresponding to three error correction codes to be interpreted. According to a logarithm domain operation mode, determining an initial logarithm likelihood ratio of each variable node in each target probability graph model, and using the initial logarithm likelihood ratio of each variable node in each target probability graph model and the three-code-in-one decoding array to perform unified interpretation on three to-be-interpreted error correction codes so as to obtain an error correction code interpretation result; according to the invention, unified interpretation of the to-be-interpreted LDPC code, the Polar code and the Turbo code is realized, and unified decoding power consumption of the to-be-interpreted LDPC code, the Polar code and the Turbo code can be effectively reduced.

The application provides a search method and device for secondary permutation polynomial interleaving parameters, and belongs to the technical field of communication. The method comprises the following steps: receiving the data block length N of a communication system as an interleaving length; reducing redundancy candidates by equivalent class parameter compression; generating two candidate sets of parameters; performing permutation combination on the two candidate sets to obtain all parameter candidate pairs, and sequentially performing algebraic metric preliminary screening and S distance fine screening on the candidate parameter pairs to output high-performance interleaving parameters; and configuring the screened optimal QPP interleaving parameters into a Turbo code interleaver of the communication system to perform interleaving processing on actual signals. The application can be used in various communication systems, solves the problems of low search efficiency, large candidate set scale and insufficient local burst error suppression capability of existing QPP interleaving parameters, and effectively reduces the complexity of parameter search and simulation workload.

This application provides a low-storage decoding method, apparatus, electronic device, and storage medium for dual-binary Turbo codes based on damped posterior propagation, belonging to the field of channel data decoding technology. The method includes: receiving an external information channel output sequence and calculating the channel log-likelihood ratio based on the external information channel output sequence; assigning the channel log-likelihood ratio as an initial posterior log-likelihood ratio; iteratively performing decoding operations based on the initial posterior log-likelihood ratio, a first decoder, and a second decoder until the maximum number of iterations is reached to obtain a target posterior log-likelihood ratio; performing symbol and decision operations on the target posterior log-likelihood ratio, and outputting a decoded bit sequence. This application can reduce the storage space occupied during the decoding process.

Techniques to improve the immunity of wireless battery systems by transmitting heavily-coded signals, e.g., using multiple chips of a sequence for each bit of information, to trade data rate for interference or jamming immunity as a response once a noisy environment is identified. The techniques provide the system with a noise immunity operating mode (or high-immunity transmit and receive mode) that can improve resilience to interference or jamming by reducing the data rate. One option for reducing the data rate is by slowing down the transmission bit rate to reduce the occupied transmit bandwidth to minimize the probability of collisions with interfering signals. Another option is though digital coding methods using Forward Error Correction such as Convolutional Coding, Reed-Solomon Coding and Turbo coding. A third option is with RF spread spectrum techniques such as Direct Sequence Spread Spectrum (DSSS) or Frequency Hopped Spread Spectrum (FHSS).

The invention provides an OFDM (Orthogonal Frequency Division Multiplexing) waveform design method suitable for covered wire transmission, which comprises the steps of CRC (Cyclic Redundancy Check) check, Turbo coding / rate matching, serial-to-parallel conversion, constellation mapping, OFDM modulation and framing, and utilizes a mode of combining an OFDM transmission technology with high spectrum utilization rate with 16QAM (Quadrature Amplitude Modulation) and 4QAM modulation technologies with high information transmission rate. Compared with a traditional single-carrier frequency domain equalization technology and a PAM constellation mapping mode of covered line transmission, the frequency spectrum utilization rate and the data transmission rate are improved; meanwhile, compared with the traditional grid coding, the Turbo coding further improves the coding gain; the insertion of the CP-UW pilot signals can reduce the difficulty of subsequent receiving end signal processing and improve the channel estimation precision, so that distortion and attenuation signals introduced by covered wire long-distance transmission can be recovered more accurately, large-bandwidth and long-distance communication in a covered wire communication environment is realized, and audio and video transmission services can be supported.

The invention discloses a vehicle-mounted information terminal loading integration design method, belongs to the technical field of vehicle-mounted communication systems, and aims to solve the problems of equipment redundancy, protocol splitting, low operation efficiency, resource waste and the like of a traditional communication vehicle. Through physical architecture reconstruction and protocol deep fusion, the following innovative schemes are provided: in the aspect of physical layer optimization, a single vehicle-mounted information terminal is connected with an Ethernet switch, heterogeneous equipment such as satellites, microwaves, scattering and radio stations are uniformly accessed, and the number of hardware is greatly reduced; in the aspect of innovation of a protocol layer, an improved SIP (Session Initiation Protocol) newly adds an equipment fingerprint code and a dynamic QoS (Quality of Service) parameter, so that multi-equipment dynamic binding of service voice is realized; the layered encapsulation protocol supports dynamic switching of Turbo codes / LDPC codes, and the video transmission bandwidth is greatly reduced; and in the aspect of intelligent resource management, based on a mixed priority arbitration algorithm, the high-priority resource preemption success rate is greatly improved.

The invention belongs to the technical field of wireless communication, and discloses a selection method of a high-spectrum-efficiency R16QAM (Radio 16QAM) structured bit selector, which comprises the following steps of: firstly, coding an information bit with the length of N through a Turbo code with a 1 / 3 code rate to obtain a to-be-transmitted coded bit block with the length of 3N, and then, carrying out structured progressive selection on the coded bit block according to a symbol transmission sequence to obtain a coded bit block with the length of 3N; and then sending and receiving in a rateless manner. Specifically, bits are extracted from a plurality of candidate sub-blocks and recombined to generate structured bit sub-blocks, a plurality of bit sub-blocks form a bit block, and then different bit blocks are generated progressively. According to the construction method of the structured'bit sub-block-bit block-progressive bit block ', the whole coding bit block to be transmitted is re-integrated into a hierarchical structured block, and multi-dimensional related observation information capable of iteratively demodulating and decoding is provided for a receiving end.

The invention relates to blind identification of Turbo codes in a non-cooperative communication environment, and provides a random interleaving mode identification method based on interleaving Turbo codes. The method comprises the following steps: firstly, realizing interleaving mode identification of an outer interleaver and an inner interleaver on the basis of a Turbo code coding system added with the outer interleaver; secondly, an LD-based identification scheme is proposed for the first time in the scene, and a KL divergence-based scheme is further proposed to identify the interleaver in the system, so that compared with the LD-based scheme, the influence of variance is considered, and the performance is further improved; moreover, aiming at the condition that only one RSC code is successfully recovered, a scheme of secondary identification after forward updating is adopted, so that the identification accuracy is further improved. The random interleaving mode identification of the interleaved Turbo code under the low signal-to-noise ratio is realized.

The application relates to the technical field of communication, and discloses a Turbo code log domain decoding method and device based on a memory-computing integrated device, which can create a unified driving vector, an external confidence updating column vector corresponding to each undirected edge and an external log-likelihood ratio updating column vector corresponding to each variable node according to a probability graph model corresponding to Turbo code to be decoded, and configure an external confidence updating array and an external log-likelihood ratio updating array in the memory-computing integrated device according to each external confidence updating column vector and the external log-likelihood ratio updating column vector, drive the external confidence updating array and the external log-likelihood ratio updating array to respectively perform external confidence and external log-likelihood ratio operation and updating based on the unified driving vector until Turbo decoding is completed, so that original bit information corresponding to the Turbo code to be decoded is obtained. The application can significantly reduce hardware resource consumption and power consumption while retaining excellent error correction capability of the Turbo code.

The application relates to the technical field of communication, and discloses a Turbo code probability domain decoding method and device based on a memory-computing integrated device, which is applied to a decoding end. The application can construct an extended check matrix and a probability graph model, configure a memory-computing integrated device subarray and a driving vector corresponding to each undirected edge according to the extended check matrix, the probability graph model and a probability domain operation mode, and transfer a state value of each variable node to a confidence degree of each check node connected through an undirected edge based on the memory-computing integrated device subarray, the driving vector corresponding to each undirected edge and each variable node, so as to decode a Turbo code to be decoded and obtain corresponding original bit information. The application can store part of static variables involved in Turbo decoding into a memory-computing integrated device based on a probability domain, and transfer part of digital operations to the memory-computing integrated device, so as to perform operations by using the storage and computing performance of the memory-computing integrated device. While the excellent error correction capability of the Turbo code is reserved, the hardware resource consumption and power consumption of the Turbo code are significantly reduced.

The invention provides a rapid implementation method of a high-performance low-bit-rate Turbo code IP core, which comprises the following steps of: splitting overall data in a segmented and parallel manner, providing a hardware architecture foundation for parallel operation, further splitting sub-blocks by sliding window processing, reducing single block storage requirements, completing core probability calculation by measurement calculation, and taking output extrinsic information as input of parallel interleaving, so as to achieve the purpose of parallel interleaving. And parallel interleaving is carried out to realize transmission of external information between the two component decoders until iteration is terminated. According to the method, the time delay is reduced, the throughput is improved, the occupation of storage resources is reduced, hardware is easy to implement, the decoding correctness is ensured, and the error rate requirement of an LTE communication system is met.

The invention relates to the technical field of communication, and discloses a Turbo code logarithm domain decoding method and device based on a storage and calculation integrated device, which can create a unified drive vector, an external confidence update column vector corresponding to each undirected edge and an external logarithm likelihood ratio update column vector corresponding to each variable node according to a probability graph model corresponding to a Turbo code to be decoded. According to each external confidence coefficient updating column vector and each external log-likelihood ratio updating column vector, configuring an external confidence coefficient updating array and an external log-likelihood ratio updating array in the storage and calculation integrated device; and driving the external confidence updating array and the external log-likelihood ratio updating array to respectively perform operation and updating of the external confidence and the external log-likelihood ratio until Turbo decoding is completed so as to obtain original bit information corresponding to the Turbo to be decoded. According to the method, the excellent error correction capability of the Turbo code is reserved, and meanwhile, the hardware resource consumption and the power consumption of the Turbo code are remarkably reduced.

The invention relates to the technical field of communication, and discloses a Turbo code probability domain decoding method and device based on a storage and calculation all-in-one device, which are applied to a decoding end. According to the method, an expansion check matrix and a probability graph model can be constructed, and a storage and calculation all-in-one device sub-array and a driving vector corresponding to each undirected edge are configured according to the expansion check matrix, the probability graph model and a probability domain operation mode; and interpreting the Turbo code to be interpreted based on the storage and calculation integrator sub-array corresponding to each undirected edge, the driving vector and the confidence coefficient of each variable node transmitting the own state value to each check node connected through the undirected edge to obtain corresponding original bit information. According to the invention, part of static variables involved in Turbo decoding can be stored in the storage and calculation all-in-one device based on the probability field, part of digital operation is transferred to the storage and calculation all-in-one device, operation is carried out by using the storage and calculation performance of the storage and calculation all-in-one device, and the hardware resource consumption and power consumption of the Turbo code are remarkably reduced while the excellent error correction capability of the Turbo code is reserved.

The invention provides a tail-biting Turbo decoding method and device based on two-stage iteration, and relates to the technical field of data stream channel coding and decoding, and the method comprises the steps: receiving a to-be-decoded sequence, and obtaining the initial state of a tail-biting Turbo code register through iterative decoding, so as to determine an initial metric value; wherein each state initial value in a forward metric matrix and a backward metric matrix in the iterative decoding process is set as an equal probability value; and performing iterative decoding on the to-be-decoded sequence again based on the initial metric value, and outputting a final decoding result. The problem of bit error rate deterioration of the tail-biting Turbo code at the decoding end due to the unknown initial state of the register is solved, so that high-reliability and high-efficiency tail-biting Turbo decoding is realized.

The invention provides a forward measurement normalization method and system for CCSDS131.0-B-3 standard Turbo decoding, electronic equipment and a storage medium, and the method and system are used for carrying out the systematic simulation analysis of the value change behavior of forward measurement Alpha of each state in the decoding process of a CCSDS131.0-B-3 standard Turbo code frame. Obtaining statistical characteristics of each state which becomes a forward measurement Alpha maximum value state in a forward recursion process; the method comprises the following steps: based on statistical characteristics, screening out a fixed state from all states of a CCSDS131.0-B-3 standard Turbo code grid diagram as a reference state for forward measurement Alpha normalization in the whole decoding process; when recursive calculation of forward measurement Alpha is carried out by a Log-MAP algorithm, for each moment t of a decoding process, a measurement value of a reference state at the current moment t is subtracted from non-normalized forward measurement values of all states at the current moment, so that normalization operation of the forward measurement Alpha of all states at the moment is completed.

The application belongs to the technical field of wireless communication, and specifically discloses a light-weight channel coding blind identification method and system based on multi-modal feature fusion. First, the signal-to-noise ratio of the collected signal is detected. If the signal-to-noise ratio is less than a signal-to-noise ratio threshold, the collected signal is subjected to LDPC code identification, Polar code identification, Turbo code identification, convolution code identification and linear block code identification based on the theory of mathematical statistics. Otherwise, the collected signal is input into a channel coding identification model for blind identification of channel coding. The method of the application adaptively selects signal statistical features and signal depth features for blind identification based on the signal-to-noise ratio of the collected signal, and combines the high efficiency of mathematical statistics identification and the high precision of deep learning identification, thereby achieving a dynamic balance between the calculation efficiency and identification precision of signal blind identification.

The application relates to a Turbo code decoding method, system, device and medium based on a memory-computing integrated device, which comprises the following steps: constructing an extended check matrix and a probability graph model of the Turbo code; configuring a node blocking state of a memory-computing integrated device array; obtaining initial log-likelihood ratios of each variable node as initial input; performing hard decision check on output corresponding to the initial input, outputting a decoding result if a termination condition is met, otherwise, using the memory-computing integrated device array to respectively complete variable node to check node transmission of confidence and calculation of a posteriori log-likelihood ratio of the variable node, and equivalent calculation of check node to variable node transmission of confidence; performing hard decision check on the a posteriori log-likelihood ratio of each variable node after each round of iteration until the iteration is stopped when the termination condition is met, and the decoding result is output. The application can be widely applied in the technical field of signal decoding.

A data processing method and apparatus, relating to the technical field of communications. In the method, when a code length is short, a sending end performs encoding in a Polar code encoding mode. Compared with using Turbo code encoding, encoding performance is improved, thereby facilitating the improvement of subsequent communication performance.

The present application relates to the technical field of decoding, and discloses a log domain three-code-in-one interpretation method and device based on a memory-computing integrated device, which can be based on target probability graph models corresponding to three to-be-interpreted error correction codes, configure a three-code-in-one decoding array including an LDPC decoding array, a Polar decoding array and a Turbo decoding array on the memory-computing integrated device, determine initial log likelihood ratios of each variable node in each target probability graph model according to a log domain operation mode, use the initial log likelihood ratios of each variable node in each target probability graph model and the three-code-in-one decoding array to uniformly interpret the three to-be-interpreted error correction codes, realize unified interpretation of to-be-interpreted LDPC codes, Polar codes and Turbo codes, and effectively reduce the unified decoding power consumption of the to-be-interpreted LDPC codes, Polar codes and Turbo codes.

The application belongs to the technical field of atmospheric laser communication, and particularly relates to a Turbo code variable interleaving depth coding method for atmospheric laser communication, which comprises an encoder, channel estimation, a decoder and a variable depth interleaver, and comprises the following steps: S1, inputting a to-be-encoded sequence into a Turbo encoder, and encoding the sequence through a component encoder, an interleaver and a punctured multiplexer; S2, adding a pilot sequence to the encoded sequence, and sending the sequence into an atmospheric channel through an optical antenna; and S3, performing channel estimation through the known pilot sequence in the received sequence, and feeding back the channel estimation value to the variable depth interleaver. The application adds a channel estimation technology to estimate the channel state in real time according to the time-varying characteristics of the atmospheric channel, provides data reference for the interleaving depth switching of the interleaver in Turbo code encoding, and guarantees the reliability of the communication system under poor channel conditions. The decoder adopts a pipeline parallel decoding structure, effectively reduces the hardware resource consumption, and effectively balances the error correction performance and decoding delay.