67 results about "Turbo coded" patented technology

The invention provides a dual-binary Turbo decoding method based on deep learning, and belongs to the technical field of wireless communication. Comprising the following steps: generating a binary random bit stream as original information, and generating a Turbo code sequence through two recursive system convolutional code component encoders; pre-processing the Turbo code sequence, and inputting the pre-processed Turbo code sequence into a bidirectional PNN model for processing to obtain an output feature vector; based on the output feature vector, standardization is carried out through a batch normalization layer, and a decoding result probability value is output by using a full connection layer and a Sigmoid activation function; and on the basis of the decoding result probability value, a Max-Log-MAP algorithm is cascaded with a component decoder of the bidirectional RNN to obtain a decoding result.

The invention relates to a dynamic wireless key frequency hopping communication anti-interference system and a method thereof. The system comprises a transmitting end and a receiving end, the transmitting end comprises an information source scrambling module, a Turbo coding module, a spread spectrum module, a framing module, a frequency hopping pattern generation module and a forming filtering module; and the receiving end comprises a digital front-end processing module, a frequency hopping synchronization module, a signal synchronization module and a demodulation module. The frequency hopping pattern based on the chaotic system has high randomness and predictability, and tracking interference and eavesdropping are effectively resisted.

The invention discloses a multi-node concurrent transmission signal superposition diversity method. The method comprises the following steps: S1, generating a Turbo coding sequence by adopting a Turbo encoder; s2, applying phase disturbance to each Turbo coding sequence; s3, performing non-orthogonal superposition in an air channel to form a complex baseband signal; s4, constructing an equivalent observation model; s5, modeling the sending symbol matrix into a sparse matrix to obtain a symbol estimation matrix; s6, inputting the symbol estimation matrix into a Turbo decoder, executing iterative decoding by adopting an improved Max-Log-MAP algorithm, and outputting a bit estimation sequence; s7, completing initial phase estimation by using a Zadoff-Chu lead code, and outputting an estimated phase sequence through a Kalman filter; and S8, dynamically updating the equivalent observation model based on the estimated phase sequence, and completing parallel computing and scheduling. According to the method, Turbo coding, sparse reconstruction and phase disturbance modeling are fused, and multi-node non-orthogonal concurrent transmission is achieved.

The invention relates to high anti-interference wireless communication for a battery management system. Techniques for improving the interference immunity of wireless battery systems by transmitting recoded signals, for example, using a plurality of chips of a sequence for each information bit, in response to interference or interference immunity in data rate exchange upon identification of a noisy environment. These techniques provide the system with an anti-noise mode of operation (or a highly anti-interference transmit and receive mode), which may improve resilience to interference or interference by reducing the data rate. One choice for reducing the data rate is to reduce the transmission bit rate so as to reduce the occupied transmission bandwidth, so that the probability of collision with interference signals is reduced to the greatest extent. Another choice is a digital coding method using forward error correction, such as convolutional coding, Reed-Solomon coding and Turbo coding. The third choice is to use a radio frequency spread spectrum technique, such as direct sequence spread spectrum (DSSS) or frequency hopping spread spectrum (FHSS).

The invention relates to the technical field of spacecraft satellite-ground communication, and provides a low-earth-orbit satellite communication time delay optimization method and system aiming at the defects that a traditional low-earth-orbit satellite communication satellite system and a satellite communication frame have high time delay and poor real-time communication function. The core of the invention comprises three parts: firstly, an efficient receiving and transmitting end coding and decoding technology: a transmitting end adopts a subblock coding technology of a Turbo code; and a receiving end uses an MAX-Log-MAP algorithm to carry out rapid iterative decoding on the word block code of the Turbo code. And secondly, compressing the user data: carrying out lossless compression on the user data and a satellite communication frame header by using Huffman coding, reducing the transmission data volume, improving the data processing speed, and thus reducing the processing time delay. And finally, simplifying the frame header design: optimizing the frame header of the communication frame so as to reduce the total length of each frame. The method is particularly suitable for communication satellites (the orbit height is less than or equal to 1500km) in a low earth orbit.

A method and a device for wireless communication are described. The method comprising segmenting a payload (305) into a plurality of code blocks, generating, for each code block, a cyclic redundancy check, CRC, associating the CRC generated for each code block with each respective code block, performing low density parity check code, LDPCC, encoding of each code block and associated CRC to generate one or more codewords of a plurality of codewords and transmitting the codewords generated by performing the LDPCC encoding.

The invention discloses an efficient method for realizing Turbo coding by an FPGA (Field Programmable Gate Array), which comprises the following steps of: before data enters a Turbo coding module, firstly introducing a dual-port RAM (Random Access Memory) and a rate grouping processing module, preprocessing and reasonably segmenting the data, saving time delay, reducing hardware resource consumption, better adapting to the Turbo coding module, and greatly compressing the processing and queuing time of the data in a Turbo coder; after Turbo coding is completed, serial-to-parallel processing is carried out on coded data, and it is ensured that the coded data can be continuously and stably output in a serial mode. According to the method, the problems that a traditional Turbo encoder is large in encoding delay and large in resource consumption are solved, the operation complexity is low, and the Turbo code can be applied to a new wireless communication system.

Various embodiments of the present technology provide a novel deep learning-based error correction coding scheme for AWGN channels under the constraint of moderate to low bit quantization (e.g., one-bit quantization) in the receiver. Some embodiments of the error correction code minimize the probability of bit error can be obtained by perfectly training a special autoencoder, in which “perfectly” refers to finding the global minima of its cost function. However, perfect training is not possible in most cases. To approach the performance of a perfectly trained autoencoder with a suboptimum training, some embodiments utilize turbo codes as an implicit regularization, i.e., using a concatenation of a turbo code and an autoencoder.

The invention discloses a data processing method and device and relates to the technical field of communication. In the method, under the condition that the code length is relatively short, the transmitting end adopts a Polar code encoding mode to encode, and compared with Turbo code encoding, the encoding performance is improved, so that the subsequent communication performance is improved.

The invention relates to a system and a method for optimizing Turbo coding and decoding by a neural network, and belongs to the technical field of crossing of communication technology and artificial intelligence. The system comprises a PL end which adopts a Turbo decoding IP core, supports dynamic configuration of iteration times and LLR scaling factors, and realizes data throughput through an AXI-Stream interface; at the PS end, a Transform model is deployed, and channel feature extraction is realized; the collaboration layer is used for realizing zero-copy data transmission between the PS and the PL; according to the method, a closed-loop optimization mechanism is formed through an end-to-end process of data input, feature extraction, parameter configuration, decoding execution, result verification and performance circulation; the objective of the invention is to realize jumping of decoding performance by dynamically adjusting decoding parameters for channel parameters, realize efficient interaction of decoding at a PS end and a PL end, improve Turbo decoding throughput and significantly improve system BER performance according to adaptive parameter adjustment.

The invention provides a dual-binary turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; determining a processing module according to the length of the processing data; wherein the processing module uniquely corresponds to one storage unit; and performing multi-round parallel processing on the processing data based on the DVB-RCS2 standard through the determined processing module. According to the method, a processing module is determined according to the length of processing data; wherein the processing module uniquely corresponds to one storage unit; through the determined processing module, multi-round parallel processing is performed on the processing data based on the DVB-RCS2 standard, parallel processing of the processing data is realized, the processing time is reduced, and the processing efficiency is improved.

The component decoding method of the TURBO code, the decoding method of the TURBO code and the related equipment provided by the embodiment of the invention comprise the following steps: receiving and demodulating data to be decoded according to scheduling configuration to obtain decoding input data; calculating a code rate and a modulation order of the decoding input data; calculating an adjustment value of the decoding input data and a bit width shift value of a posterior probability branch metric parameter in a decoder according to the modulation order and the code rate of the decoding input data; adjusting the numerical value of the decoding input data through the adjustment value to obtain first decoding input data; performing component decoding on the first decoding input data to obtain a calculation result of a posterior probability branch metric in the decoder; performing shift processing on a calculation result of the posterior probability branch measurement in the decoder through the bit width shift value to obtain a component decoding output value; the method has the beneficial effect of improving the decoding performance, and is suitable for the technical field of TURBO code decoding.

An embodiment of the present application provides a component decoding method for a TURBO code, a decoding method for a TURBO code, and related equipment, including: receiving and demodulating data to be decoded according to a scheduling configuration to obtain decoding input data; and calculating the code rate and modulation order of the decoding input data; calculating an adjustment value for the decoding input data and a bit width shift value of a decoder internal posterior probability branch metric parameter according to the modulation order and code rate of the decoding input data; adjusting the numerical value of the decoding input data by the adjustment value to obtain first decoding input data; component decoding the first decoding input data to obtain a calculation result of the decoder internal posterior probability branch metric; and shifting the calculation result of the decoder internal posterior probability branch metric by the bit width shift value to obtain a component decoding output value. The method has the beneficial effect of improving decoding performance and is applicable to the technical field of TURBO code decoding.

The invention relates to the technical field of decoding, and discloses a three-code-in-one interpretation method and device of a probability domain based on a storage and calculation integrated device, which can configure a three-code-in-one decoding array comprising an LDPC (Low Density Parity Check) decoding array, a Polar decoding array and a Turbo decoding array on the storage and calculation integrated device based on a target probability graph model corresponding to three error correction codes to be interpreted. According to a probability domain operation mode, determining a state value initial probability of each variable node in each target probability graph model, and using the state value initial probability of each variable node in each target probability graph model and the three-code-in-one decoding array to perform unified interpretation on three to-be-interpreted error correction codes so as to obtain an error correction code interpretation result; according to the invention, unified interpretation of the to-be-interpreted LDPC code, the Polar code and the Turbo code is realized, and unified decoding power consumption of the to-be-interpreted LDPC code, the Polar code and the Turbo code can be effectively reduced.

This invention belongs to the field of wireless communication technology and discloses a selection method for a high-spectrum-efficiency R16QAM (Rateless 16QAM) structured bit selector. First, N information bits are encoded using a 1 / 3 code rate Turbo code to obtain a 3N-length coded bit block to be transmitted. Then, the coded bit block is progressively selected in a structured manner according to the symbol transmission order, and finally transmitted and received in a rateless manner. Specifically, bits are extracted from multiple candidate sub-blocks and recombined to generate structured bit sub-blocks. Multiple bit sub-blocks constitute a single bit block, and different bit blocks are progressively generated. This structured "bit sub-block-bit block-progressive bit block" construction method reintegrates the entire coded bit block to be transmitted into a hierarchical structured block, providing the receiver with iteratively demodulated and decoded multi-dimensional correlation observation information.

The invention provides a turbo code processing method and electronic hardware. The method comprises the following steps: acquiring processing data; partitioning the processed data into blocks; wherein the blocks correspond to different storage units; performing multi-path processing on each block based on each storage unit; wherein the processing is interleaving or de-interleaving. According to the method provided by the invention, the parallel processing of the processing data is realized by partitioning the processing data and then performing multi-path processing on each block, so that the processing time is shortened, and the processing efficiency is improved.

Communication systems and methods are disclosed that utilize Probability Amplitude Shaping (PAS) and Trellis Coded Modulation (TCM) to transmit short block-length messages. While capacity-approaching codes, such as Low Density Parity Check (LDPC) codes, Turbo codes, and Polar codes, can achieve data rates approaching the Shannon limit at large block-lengths, the performance of these codes can deteriorate dramatically at short block-lengths. Communication systems configured in accordance with various embodiments of the invention can utilize classical codes to encode short block-length messages to achieve communication rates exceeding Polyanskiy's Random Coding Union bound. In several embodiments, message bits are transmitted using a TCM system in which message bits that have been previously encoded by an error detection code are encoded using a convolutional code (CC). In a number of embodiments, the error detection code and the CC are obtained via a joint optimization with respect to a Frame Error Rate bound.

The invention provides a soft demodulation algorithm based on bit interleaving Turbo coding frequency shift chirp keying modulation, and relates to the technical field of communication. The method comprises the following steps: carrying out Turbo coding on a signal at a sending end, interleaving coded bits, carrying out LoRa modulation mapping on the interleaved coded bits to obtain a corresponding periodic frequency shift chirp signal, obtaining a frequency domain waveform of a despread signal at a receiving end by utilizing an original LoRa demodulation scheme, and obtaining a frequency shift chirp signal according to probability distribution of values of frequency domain sampling points. And calculating a log-likelihood ratio on each bit, sending the obtained log-likelihood ratios to a corresponding de-interleaver, and inputting and transmitting the de-interleaved log-likelihood ratios as soft information to a Turbo decoder for Turbo decoding. The problem of information loss during information transmission between the LoRa demodulator and the Turbo soft input soft output decoder is solved. After Turbo coding is added, the bit error rate performance of the system is obviously improved, and along with the increase of the signal-to-noise ratio, the decline rate of the bit error rate is obviously improved.

The invention relates to the technical field of decoding, and discloses a three-code-in-one interpretation method and device of a logarithm domain based on a storage and calculation integrated device, which can configure a three-code-in-one decoding array comprising an LDPC (Low Density Parity Check) decoding array, a Polar decoding array and a Turbo decoding array on the storage and calculation integrated device based on a target probability graph model corresponding to three error correction codes to be interpreted. According to a logarithm domain operation mode, determining an initial logarithm likelihood ratio of each variable node in each target probability graph model, and using the initial logarithm likelihood ratio of each variable node in each target probability graph model and the three-code-in-one decoding array to perform unified interpretation on three to-be-interpreted error correction codes so as to obtain an error correction code interpretation result; according to the invention, unified interpretation of the to-be-interpreted LDPC code, the Polar code and the Turbo code is realized, and unified decoding power consumption of the to-be-interpreted LDPC code, the Polar code and the Turbo code can be effectively reduced.

The application provides a search method and device for secondary permutation polynomial interleaving parameters, and belongs to the technical field of communication. The method comprises the following steps: receiving the data block length N of a communication system as an interleaving length; reducing redundancy candidates by equivalent class parameter compression; generating two candidate sets of parameters; performing permutation combination on the two candidate sets to obtain all parameter candidate pairs, and sequentially performing algebraic metric preliminary screening and S distance fine screening on the candidate parameter pairs to output high-performance interleaving parameters; and configuring the screened optimal QPP interleaving parameters into a Turbo code interleaver of the communication system to perform interleaving processing on actual signals. The application can be used in various communication systems, solves the problems of low search efficiency, large candidate set scale and insufficient local burst error suppression capability of existing QPP interleaving parameters, and effectively reduces the complexity of parameter search and simulation workload.

This application provides a low-storage decoding method, apparatus, electronic device, and storage medium for dual-binary Turbo codes based on damped posterior propagation, belonging to the field of channel data decoding technology. The method includes: receiving an external information channel output sequence and calculating the channel log-likelihood ratio based on the external information channel output sequence; assigning the channel log-likelihood ratio as an initial posterior log-likelihood ratio; iteratively performing decoding operations based on the initial posterior log-likelihood ratio, a first decoder, and a second decoder until the maximum number of iterations is reached to obtain a target posterior log-likelihood ratio; performing symbol and decision operations on the target posterior log-likelihood ratio, and outputting a decoded bit sequence. This application can reduce the storage space occupied during the decoding process.

Techniques to improve the immunity of wireless battery systems by transmitting heavily-coded signals, e.g., using multiple chips of a sequence for each bit of information, to trade data rate for interference or jamming immunity as a response once a noisy environment is identified. The techniques provide the system with a noise immunity operating mode (or high-immunity transmit and receive mode) that can improve resilience to interference or jamming by reducing the data rate. One option for reducing the data rate is by slowing down the transmission bit rate to reduce the occupied transmit bandwidth to minimize the probability of collisions with interfering signals. Another option is though digital coding methods using Forward Error Correction such as Convolutional Coding, Reed-Solomon Coding and Turbo coding. A third option is with RF spread spectrum techniques such as Direct Sequence Spread Spectrum (DSSS) or Frequency Hopped Spread Spectrum (FHSS).

The invention provides an OFDM (Orthogonal Frequency Division Multiplexing) waveform design method suitable for covered wire transmission, which comprises the steps of CRC (Cyclic Redundancy Check) check, Turbo coding / rate matching, serial-to-parallel conversion, constellation mapping, OFDM modulation and framing, and utilizes a mode of combining an OFDM transmission technology with high spectrum utilization rate with 16QAM (Quadrature Amplitude Modulation) and 4QAM modulation technologies with high information transmission rate. Compared with a traditional single-carrier frequency domain equalization technology and a PAM constellation mapping mode of covered line transmission, the frequency spectrum utilization rate and the data transmission rate are improved; meanwhile, compared with the traditional grid coding, the Turbo coding further improves the coding gain; the insertion of the CP-UW pilot signals can reduce the difficulty of subsequent receiving end signal processing and improve the channel estimation precision, so that distortion and attenuation signals introduced by covered wire long-distance transmission can be recovered more accurately, large-bandwidth and long-distance communication in a covered wire communication environment is realized, and audio and video transmission services can be supported.

The invention provides a Turbo code decoding iteration termination method, a Turbo code decoding method, a related device and equipment, and the method comprises the steps: in a Turbo code decoding process, when each iteration is executed, decoding information outputted by a second decoder is obtained, and decoding is carried out; obtaining a maximum initial state index and a maximum termination state index respectively corresponding to the maximum backward probability value of the initial state and the maximum forward probability value of the termination state output by the second decoder; judging whether the maximum initial state index is consistent with the maximum termination state index or not; if yes, decoding information output by the second decoder is verified, and then decoding is ended or next iterative decoding continues to be executed according to a verification result; if not, directly continuing to execute next iterative decoding; according to the method, under the condition that the decoding performance is not influenced, the number of iterations is effectively reduced, meanwhile, the number of times of verification is reduced, hardware resources are saved, and decoding time delay is reduced; the method is suitable for communication technology.

The invention provides a Turbo code design method, which is used for designing a Turbo code using a high-performance interleaver. The Turbo encoder comprises a first convolution encoder, an interleaver and a second convolution encoder. A first convolutional encoder generates a first parity stream of input data using a predetermined recursive systematic convolutional RSC code. And an interleaver that rearranges the order of the internal sequence of the input data on the basis of a first rule and generates permutation data. And a second convolutional encoder that generates a second parity stream of the permutation data using the RSC code. A Turbo code design method includes selecting a polynomial representing an RSC code from a Galois field of the polynomial, and designing a first rule of an interleaver based on the RSC code.

The invention discloses a vehicle-mounted information terminal loading integration design method, belongs to the technical field of vehicle-mounted communication systems, and aims to solve the problems of equipment redundancy, protocol splitting, low operation efficiency, resource waste and the like of a traditional communication vehicle. Through physical architecture reconstruction and protocol deep fusion, the following innovative schemes are provided: in the aspect of physical layer optimization, a single vehicle-mounted information terminal is connected with an Ethernet switch, heterogeneous equipment such as satellites, microwaves, scattering and radio stations are uniformly accessed, and the number of hardware is greatly reduced; in the aspect of innovation of a protocol layer, an improved SIP (Session Initiation Protocol) newly adds an equipment fingerprint code and a dynamic QoS (Quality of Service) parameter, so that multi-equipment dynamic binding of service voice is realized; the layered encapsulation protocol supports dynamic switching of Turbo codes / LDPC codes, and the video transmission bandwidth is greatly reduced; and in the aspect of intelligent resource management, based on a mixed priority arbitration algorithm, the high-priority resource preemption success rate is greatly improved.

The invention belongs to the technical field of wireless communication, and discloses a selection method of a high-spectrum-efficiency R16QAM (Radio 16QAM) structured bit selector, which comprises the following steps of: firstly, coding an information bit with the length of N through a Turbo code with a 1 / 3 code rate to obtain a to-be-transmitted coded bit block with the length of 3N, and then, carrying out structured progressive selection on the coded bit block according to a symbol transmission sequence to obtain a coded bit block with the length of 3N; and then sending and receiving in a rateless manner. Specifically, bits are extracted from a plurality of candidate sub-blocks and recombined to generate structured bit sub-blocks, a plurality of bit sub-blocks form a bit block, and then different bit blocks are generated progressively. According to the construction method of the structured'bit sub-block-bit block-progressive bit block ', the whole coding bit block to be transmitted is re-integrated into a hierarchical structured block, and multi-dimensional related observation information capable of iteratively demodulating and decoding is provided for a receiving end.

The invention relates to blind identification of Turbo codes in a non-cooperative communication environment, and provides a random interleaving mode identification method based on interleaving Turbo codes. The method comprises the following steps: firstly, realizing interleaving mode identification of an outer interleaver and an inner interleaver on the basis of a Turbo code coding system added with the outer interleaver; secondly, an LD-based identification scheme is proposed for the first time in the scene, and a KL divergence-based scheme is further proposed to identify the interleaver in the system, so that compared with the LD-based scheme, the influence of variance is considered, and the performance is further improved; moreover, aiming at the condition that only one RSC code is successfully recovered, a scheme of secondary identification after forward updating is adopted, so that the identification accuracy is further improved. The random interleaving mode identification of the interleaved Turbo code under the low signal-to-noise ratio is realized.

The application relates to the technical field of communication, and discloses a Turbo code log domain decoding method and device based on a memory-computing integrated device, which can create a unified driving vector, an external confidence updating column vector corresponding to each undirected edge and an external log-likelihood ratio updating column vector corresponding to each variable node according to a probability graph model corresponding to Turbo code to be decoded, and configure an external confidence updating array and an external log-likelihood ratio updating array in the memory-computing integrated device according to each external confidence updating column vector and the external log-likelihood ratio updating column vector, drive the external confidence updating array and the external log-likelihood ratio updating array to respectively perform external confidence and external log-likelihood ratio operation and updating based on the unified driving vector until Turbo decoding is completed, so that original bit information corresponding to the Turbo code to be decoded is obtained. The application can significantly reduce hardware resource consumption and power consumption while retaining excellent error correction capability of the Turbo code.

The invention relates to a Turbo code decoder adopting a new architecture, a Turbo code decoding method and a Beidou receiver. The decoder comprises a first interleaver, a second interleaver, a third interleaver and a fourth interleaver, wherein the first interleaver carries out interleaving processing on input system bit soft information and outputs the system bit soft information; the second interleaver performs interleaving processing on the L12 information output by the first decoder and outputs the L12 information; the de-interleaver is used for carrying out de-interleaving processing on the L21 information output by the second decoder and outputting the L21 information; the second decoder calculates L21 information and LLR information according to the system bit soft information, the L12 information and the check bit 2 soft information; the first decoder calculates L12 information according to the input soft information of the check bit 1, the soft information of the system bit and the de-interleaved L21 information; and the judgment module judges the LLR information meeting the iteration stopping condition and outputs a Turbo code decoding result. According to the invention, a new decoder architecture is adopted, the operation time is shortened, and the decoding efficiency is improved.