8 results about "Turbo decoder" patented technology

The invention discloses a multi-node concurrent transmission signal superposition diversity method. The method comprises the following steps: S1, generating a Turbo coding sequence by adopting a Turbo encoder; s2, applying phase disturbance to each Turbo coding sequence; s3, performing non-orthogonal superposition in an air channel to form a complex baseband signal; s4, constructing an equivalent observation model; s5, modeling the sending symbol matrix into a sparse matrix to obtain a symbol estimation matrix; s6, inputting the symbol estimation matrix into a Turbo decoder, executing iterative decoding by adopting an improved Max-Log-MAP algorithm, and outputting a bit estimation sequence; s7, completing initial phase estimation by using a Zadoff-Chu lead code, and outputting an estimated phase sequence through a Kalman filter; and S8, dynamically updating the equivalent observation model based on the estimated phase sequence, and completing parallel computing and scheduling. According to the method, Turbo coding, sparse reconstruction and phase disturbance modeling are fused, and multi-node non-orthogonal concurrent transmission is achieved.

A modem chip may include a turbo decoding circuit configured to receive a plurality of channel log likelihood ratios respectively corresponding to a plurality of bits included in a symbol, generate a plurality of first posteriori log likelihood ratios respectively corresponding to the plurality of bits in an Nth iterative loop based on the plurality of channel log likelihood ratios, wherein N is greater than or equals to 1, and generate a first input / output counting value by counting a number of first posteriori log likelihood ratios, among the plurality of first posteriori log likelihood ratios, that differ in sign from the corresponding channel log-likelihood ratios, and a decoding control circuit configured to stop decoding for the plurality of bits in the turbo decoding circuit based on the first input / output counting value being greater than or equal to a first threshold.

A turbo decoder includes a first soft input soft output (SISO) decoder configured to receive systematic information, first parity information, and a first pre-log likelihood ratio (LLR), and to output a first parity LLR obtained by calculating an LLR for the first parity information, a first interleaver configured to interleave the systematic information, a second SISO decoder configured to receive an output of the first interleaver, second parity information, and a second pre-LLR, and to output a second parity LLR obtained by calculating an LLR for the second parity information, and an interference canceller configured to receive the first parity LLR from the first SISO decoder, receive the second parity LLR from the second SISO decoder, and calculate a first update parity LLR and a second update parity LLR.

The invention discloses a Turbo decoder, a Turbo decoding method, a communication chip and terminal equipment, and the Turbo decoder comprises a first component decoder which is used for obtaining first extrinsic information through calculation according to an information sequence and first prior information; the interleaving gating unit is used for gating a corresponding interleaver according to a current communication protocol, performing interleaving processing on the first extrinsic information, and transmitting the interleaved first extrinsic information as second prior information to the second component decoder; the second component decoder is used for calculating to obtain posterior probability information and second extrinsic information according to the interleaved information sequence and the second prior information; the de-interleaving gating unit is used for gating a corresponding de-interleaver according to the current communication protocol, performing de-interleaving processing on the second extrinsic information, and transmitting the de-interleaved second extrinsic information as first prior information to the first component decoder; and the output unit is used for judging to output a decoding bit sequence according to the output posterior probability information when an iteration stopping condition is met.

The invention discloses a modem chip and an operation method of a turbo decoder. The modem chip may include: a turbo decoding circuit configured to: receive a plurality of channel log-likelihood ratios respectively corresponding to a plurality of bits included in a symbol; based on the plurality of channel log-likelihood ratios, generating a plurality of first posterior log-likelihood ratios respectively corresponding to the plurality of bits in the Nth iterative loop, where N is greater than or equal to 1; and generate a first input / output count value by counting a number of first posterior log-likelihood ratios different in sign from a corresponding channel log-likelihood ratio among the plurality of first posterior log-likelihood ratios; and a decoding control circuit configured to stop decoding of the plurality of bits in the turbo decoding circuit based on a first input / output count value being greater than or equal to a first threshold value.

This invention discloses a low-consumption Turbo decoder and decoding method based on block and variable length, aiming to solve the problems of excessive resource consumption and limited compatibility code length parameters of existing decoders. It includes: a rate matching module, a data storage module, a decoding control module, a forward metric calculation module, a backward metric calculation module, an external information calculation module, and a SISO control module. Its key feature is that it also includes an internal interleaving address calculation module, which includes two multipliers, a divider, a ROM storing the basic sequence S, a register storing the permutation pattern T, and a register storing the prime number sequence r. This module is used to generate row and column positions according to the order of data transmission. The row positions are mapped to the original row positions using the permutation pattern. The column positions are multiplied and divided to obtain the address of the prime number sequence S. The original column positions are obtained through a lookup table. The original row positions are then multiplied by the total number of columns and added back to the original column positions. Values ​​exceeding the information length are removed to obtain the interleaving address.

The present invention discloses a multi-node concurrent transmission signal superposition diversity method, comprising the following steps: S1, using a Turbo encoder to generate a Turbo code sequence; S2, applying phase perturbation to each Turbo code sequence; S3, performing non-orthogonal superposition in an air channel to form a complex baseband signal; S4, constructing an equivalent observation model; S5, modeling the transmission symbol matrix as a sparse matrix to obtain a symbol estimation matrix; S6, inputting the symbol estimation matrix into a Turbo decoder, performing iterative decoding using an improved Max-Log-MAP algorithm, and outputting a bit estimation sequence; S7, using a Zadoff-Chu preamble to complete initial phase estimation, and outputting an estimated phase sequence through a Kalman filter; S8, dynamically updating the equivalent observation model based on the estimated phase sequence to complete parallel computing and scheduling. The present invention integrates Turbo coding, sparse reconstruction, and phase perturbation modeling to achieve multi-node non-orthogonal concurrent transmission.