3 results about "Turbo decoder" patented technology

The invention discloses a Turbo decoder, a Turbo decoding method, a communication chip and terminal equipment, and the Turbo decoder comprises a first component decoder which is used for obtaining first extrinsic information through calculation according to an information sequence and first prior information; the interleaving gating unit is used for gating a corresponding interleaver according to a current communication protocol, performing interleaving processing on the first extrinsic information, and transmitting the interleaved first extrinsic information as second prior information to the second component decoder; the second component decoder is used for calculating to obtain posterior probability information and second extrinsic information according to the interleaved information sequence and the second prior information; the de-interleaving gating unit is used for gating a corresponding de-interleaver according to the current communication protocol, performing de-interleaving processing on the second extrinsic information, and transmitting the de-interleaved second extrinsic information as first prior information to the first component decoder; and the output unit is used for judging to output a decoding bit sequence according to the output posterior probability information when an iteration stopping condition is met.

This invention discloses a low-consumption Turbo decoder and decoding method based on block and variable length, aiming to solve the problems of excessive resource consumption and limited compatibility code length parameters of existing decoders. It includes: a rate matching module, a data storage module, a decoding control module, a forward metric calculation module, a backward metric calculation module, an external information calculation module, and a SISO control module. Its key feature is that it also includes an internal interleaving address calculation module, which includes two multipliers, a divider, a ROM storing the basic sequence S, a register storing the permutation pattern T, and a register storing the prime number sequence r. This module is used to generate row and column positions according to the order of data transmission. The row positions are mapped to the original row positions using the permutation pattern. The column positions are multiplied and divided to obtain the address of the prime number sequence S. The original column positions are obtained through a lookup table. The original row positions are then multiplied by the total number of columns and added back to the original column positions. Values ​​exceeding the information length are removed to obtain the interleaving address.