144 results about "Correctness" patented technology

The invention discloses an information sharing and safe multi-party computing protocol based on a block chain, mainly solves the problem that the existing secure multi-party computation is easy to cause the user to be unable to control the data independently that is easy to get the data by the third party. The technical solutions are as follows: 1) constructing the storage model, and storing the index table information on the chain and the database under the chain in the way. 2) constructing a data sharing model,wherein users can access their data by authorizing a third party or revoke their privileges at any time. 3) using the consensus mechanism of the block chain to ensure the consistency among nodes; 4) Based on the correctness of nodes, using MapReduce programming model, the model isdivided into two phases: Map and Reduce, and the master node assigns the tasks of Map and Reduce to the nodes; 5) Map node uses the improved homomorphic encryption algorithm for encryption calculation; 6) Reduce node integrates the encrypted data to output data files.

A metadata validation process that allows for deferring object model validation until after the objects are created. The process also allows for multi-threaded processing of the validation rules, thus increasing overall performance. Validation is performed by enforcing a series of validation rules on an appropriate subject. Rules are specified according to the subject that they are validating (i.e., attribute level, association level, object level or collection level). The metadata driven validation process implements several validation types on different validation units. Correctness validation rule types ensure that a validation unit satisfies all semantic rules defined for it. Completeness validation rule types ensure that a validation unit contains all the necessary data and is ready for further use. At design time, only correctness type validation is performed. Thus, the present invention advantageously allows for incomplete objects to be created at design time. The developer, however, in this case may opt to perform completeness validation at any time. In general, a developer may opt to perform completeness and/or correctness validation at any time independent of deployment processing. In another aspect, full validation (e.g., completeness and correctness) is automatically performed on the objects during the process of creating a configuration prior to deployment.

The invention relates to a malicious code detection method and system. The method comprises the steps that A, extracting corresponding features from binary data of a single PE file in a training dataset; b, performing dimension reduction processing on the features; c, extracting the features of the binary data as the front half part of the deep learning model through a gated convolutional network; d, combining the features after dimension reduction with the feature vectors obtained in the step C, inputting the combined features into a full-connection neural network serving as the rear half part of the deep learning model, and generating final feature vectors to be classified; e, generating corresponding to-be-classified feature vectors for all PE files; and F, classifying all the to-be-classified feature vectors, comparing the classified feature vectors with known categories in the test data set to verify the correctness of the deep learning model, and obtaining an optimal deep learning model by adjusting parameters. According to the method, the influence of malicious code instruction transformation can be avoided, whether the unknown software contains the malicious code or not can be accurately detected, and the detection efficiency is also improved.

The invention discloses a verifiable fully homomorphic encryption method based on matrix operation. The method comprises the following steps: preprocessing and converting plaintext data into vectors to obtain a vector set; Then selecting a non-zero random real number and each vector to construct a triangular matrix, and encrypting each triangular matrix to obtain an encrypted matrix set; Generating verification evidences by utilizing the triangular matrix set according to the calculation function type; Performing matrix operation on each encryption matrix according to a certain rule to obtainan encrypted operation result; And finally, decrypting the encrypted operation result to obtain a plaintext of the result, and verifying the correctness of the result by comparing whether the verification evidence is equal to the value of the calculation result. The method has privacy security and result verifiability; Simulation experiment results show that the method has high efficiency in the stages of secret key generation, decryption and verifiability, and the effectiveness and feasibility of the scheme are shown.

The invention discloses a theorem proving-based formal verification method. The method is applied to the field of secure operating systems. The invention aims to solve the security problem of an existing operating system. The theorem proving-based formal verification method comprises the following steps that: source codes are reconstructed; formal modeling is conducted on a function; theorem description is conducted on the function; and finally, formal certification is conducted. According to the method of the invention, the semi-automatic proving of human-computer interaction is adopted; by means of an isomorphic relationship between a type system and logic, a proof constructing process is converted into a program writing process; proof correctness check is changed into a type check problem; although a large amount of manual labor is needed to construct the proof, the method provided by the invention does not need to sacrifice the expression ability of protocols and codes, particularly logic with very strong expression ability can be used in a program to realize representation; the proof itself has display representation in a machine; the correctness of the proof itself can be automatically checked; and a verified conclusion is more credible.

The invention discloses a sample format protection method and device for a gray box fuzzy test. The sample format protection method comprises the steps of training a machine learning model to enable the model to recognize the correctness of the format of a testing corpus; when the fuzzy test is conducted on a program, obtaining an initial corpus from a corpus set and mutating the initial corpus toobtain the testing corpus; using the testing corpus to conduct the fuzzy test on the program, and in the process of the fuzzy test, determining whether the format of the testing corpus is correct ornot through the model. When the format of the testing corpus is correct and the testing corpus covers a program code uncovered by an existing testing corpus, the testing corpus is added into the corpus set, and the process is repeated. In this way, the corpuses, with the correct format, determined in each fuzzy test is added into the corpus set, the correctness of the formats of the corpuses in the corpus set is guaranteed to the greatest extent, and the efficiency of the fuzzy test is improved. Moreover, through a position set, the mutation of the initial corpus is guided, an invalid mutationoperation is avoided, and the testing efficiency is further improved.

It is an assembler program automatic fault-finding method, which comprises the following steps: to read and analyze the assembler program Y and to get the said whole variables of the said program according to the grammar and orders of the special chip and to generate the relation form A between the variable and the web address; to pre-process the assembler program and standardize the program to form one assembler program easy to be identified and inspected; to test the web page accuracy of the program and to fine the error of the report page.

The invention discloses a dynamic graph execution method and device for neural network calculation. The method comprises the following steps: S1, constructing and distributing operators and tensors; s2, deriving an operator execution process by an operator interpreter; s3, the operator interpreter constructs an instruction of the virtual machine during operation; s4, the operator interpreter sends the instruction to the runtime virtual machine; s5, a virtual machine dispatch instruction; and S6, releasing the executed instruction by the virtual machine. According to the dynamic graph execution method and device for neural network calculation provided by the invention, the runtime is abstracted as the virtual machine, and the virtual machine obtains the sub-graph scheduling of each step established by the user through the interpreter in real time and issues and executes each sub-graph, so that the instant debugging requirement of the user is met, local adjustment and optimization can be realized, and the user experience is improved. And obtaining an optimal local model. And the requirements of algorithm researchers for instantly verifying the algorithm correctness and the local performance of the model in the model development process are met.

The invention discloses a front-end code generation method and device and computer equipment, relates to the technical field of computers, and can solve the technical problems that the code generation efficiency is low and the workload is large due to the fact that an existing front-end code generation mode has a repeated labor part. The method comprises the following steps: acquiring a UI design draft file, analyzing the UI design draft file according to a preset file analysis rule, and acquiring first front-end data of each component element in a UI interface; based on a depth-first algorithm and according to the first front-end data, generating first component structured data of each component element; and performing correctness verification on the first component structured data according to a preset verification rule, and if it is judged that the first component structured data passes the correctness verification, converting the first component structured data into a front-end code corresponding to the UI design draft file based on a preset code conversion rule. The invention is suitable for automatic generation of front-end codes.

The invention discloses an efficient and safe two-party computing system and method based on cooperation, and the system comprises: a function-independent preprocessing module which is used for pre-generating verifiable random bit sharing shares and a label pair set of an input line, which are needed by safe computing, for two communication parties; a function correlation preprocessing module, wherein participants serve as confusion parties respectively, and verifiable confusion circuit sharing shares are generated for the first half circuit and the second half circuit respectively; an input preprocessing module, wherein a calculation side obtains a label set corresponding to a true value masking value form of each input line of the circuit; a circuit analysis module, wherein participants serve as calculation parties in sequence, confusion circuits of a front half circuit and a rear half circuit are recovered and analyzed respectively, and the correctness of circuit calculation is verified; and an output module, wherein the two communication parties obtain the corresponding masking values from the output line labels and recover the output true values. According to the system, circuit calculation correctness and input privacy can be ensured, communication complexity is low, both parties share calculation pressure, safety calculation efficiency is high, and malicious opponents can be resisted.

The invention discloses a processor based on a semi-custom register file, which comprises a five-stage assembly line, an error detecting-and-correcting module, a crossover network register file and a check code generation module, wherein a processor fault-tolerant method comprises following steps: when an error that can be corrected occurs in datum of the register file, the assembly line is restarted to correct the error and related instructions are re-performed; when an error that can't not be corrected occurs in the datum of the register file, the assembly line is restarted to detect the backup datum of the error datum of the register file; if the backup datum are right, the subsequent processor processing is performed with the backup datum; if an error that can't be corrected also occurs in the backup datum, the processor will enter trap processing program; and the error is recovered by software. By a plurality of rollbacks and restarts of the assembly line, and the scheduling to an operand access address, the error that can be corrected is refreshed and the backup datum are polled correctly; and a data backup in rebundant hardware is dug out, thus the data reliability of the register file is improved.

Based on weight coefficients calculated for corresponding nodes of first flow, nodes of multiple flows and nodes of second flow, the method compares the weight coefficients. Then, the method validates whether weight coefficients of nodes of second flow are equal to weight coefficients of nodes of first flow so as to obtain validity and correctness. Through the above inspection in advance, the invention prevents problem in execution in future caused by design error of workflow. The invention provides validation method for projector of workflow to build collect workflow. The invention is also applicable to workflow includes program in cascaded sign and sign jointly. Thus, diversified workflow can be designed to be suitable to practical need.

The invention discloses a method and a device for debugging parallel programs based on application logical orders. The method for debugging parallel programs includes defining data chains and abstractly describing semantic logics of complex parallel programs, wherein the data chains comprise application logical orders, logic fragment assembles and a correctness verification algorithm, and the application logical orders are iteration step orders or data flow orders; data of program variables during parallel program operation are tracked according to definitions of the data chains, and the data of the program variables are verified by the correctness verification algorithm and verification results are recorded; and the recorded verification results are reset when the parallel program stops operation or is exited abnormally. The method and the device are based on a reset debugging plan of parallel application system semantic logics, error locating of parallel programs is facilitated, and storage and analysis expenditures are saved.

The subject matter discloses a system for enforcing correctness of a derivation key, comprising multiple computerized nodes, comprising a storage module configured to store a share of a key used as an input of a function generating the derivation key, a communication module configured to exchange information between the multiple computerized nodes, and a processing module configured to receiving a request to create the derivation key, performing an MPC process between the multiple computerized nodes, said MPC process is performed multiple times, in each time the MPC process comprises receiving the key shares as input, randomly selecting a function, outputting the outputs of the selected function to the multiple computerized nodes, the multiple computerized nodes lack access to the selected function, the multiple computerized nodes perform computations on the received outputs and exchange outputs of the computations to estimate correction of the key shares inputted into the MPC process.

The invention discloses a method for verifying an error correction and detection function of a regfile of a SPARC V8 processor. The method includes generating and injecting error into a register of the regfile by a software programming method, simulating error of the regfile, reading the error injected into the regfile, triggering the error correction and detection function of the regfile, and judging accuracy of the error correction and detection function of the regfile according to executing results of the software program. By the method, accurate error injection into data bits and check bits of the regfile of the highly reliable SPARC V8 processor can be realized, and the error correction and detection function of the regfile can be verified. The method completed by software is convenient, low in cost and high in speed and can be combined with applications to verify the error processing program function of the regfile in the applications.

The invention belongs to the technical field of computer science informatization, and discloses an extensible universal code generation system and method, and the method comprises the steps that a code object registration center manages all object type information needing to be coded; the coding rule definition device defines a coding rule; a code generator obtains a corresponding attribute valuefrom an object to be coded according to the definition of a coding rule, obtains a new code value through attribute calculation, code conversion and fragment combination, and distributes the new codevalue to a code applicant, wherein the coding object type library stores all registered object types; the encoding rule base stores all encoding rule definitions; the code library stores the code andgenerates an object attribute value of the code. According to the invention, a new coding object type can be dynamically registered according to business requirements, a coding generation rule is customized, a new code is generated, the management of the coding object type, the coding rule and the code is provided, and the correctness, uniqueness and consistency of the code are ensured.

The invention discloses a method for judging correctness of parasitic parameter results. The method comprises the following steps of: 1) appointing a test case library, an operation directory and a report generation directory of a test; 2) setting an extraction mode and a threshold value of parasitic parameters; 3) performing extraction operation on the layout data according to a set extraction mode; 4) writing the extracted parasitic parameters of all the test cases into a test table, and 5) judging the correctness of parasitic parameter results to generate a summary report. the method for judging the correctness of the parasitic parameter results has the advantages that calculation of complex data types and automatic analysis of mass data are supported, and the correctness and efficiencyof design are greatly improved.

The invention relates to a federated learning method for privacy protection and verifiable privacy based on zero knowledge proof, which belongs to the technical field of artificial intelligence machine learning and comprises the steps of training task release, local training, proof generation, training result submission, training process verification and training parameter aggregation. According to the method, the correctness of the training process is proved to the publisher under the condition that the privacy data of the trainer is not leaked by utilizing a zero-knowledge proving technology in the federation learning process. According to the method, a training algorithm used in federated learning is not limited and required, and the proving of any training process is supported, so that the federated learning has the properties of verifiability and privacy protection, and the safety of the federated learning is improved. Meanwhile, a method for converting a decimal machine learning process into an integer machine learning process is adopted, the complex machine learning process is expressed through a series of simple operation combinations related to addition, subtraction, multiplication and division, and the machine learning process and cryptography are organically connected and combined.

The invention can be applied to the technical field of big data, and provides a code conversion method and device. The method comprises the steps: filtering a pre-received to-be-converted code; analyzing the filtered to-be-converted code to obtain an AST abstract syntax structure tree corresponding to the to-be-converted code; and generating a target code according to the AST abstract syntax structure tree. According to the method, corresponding codes of applications can be automatically pulled, modified and submitted. The modification efficiency, the correctness of a modification result and the normalization are greatly improved compared with those of pure manual operation.

The invention relates to a text proofreading method and device, a computer readable storage medium and electronic equipment. The method comprises the steps of determining error correction informationof each sentence in a to-be-proofreading text, wherein the error correction information comprises an error word and at least one error correction word corresponding to the error word; for each error word, respectively determining a first co-occurrence frequency and a second co-occurrence frequency of the error word and front and back words of the error word in a preset corpus; for each error correction word corresponding to the error word, obtaining semantic features; and judging whether the error correction word is correct or not at least according to the first co-occurrence frequency, the second co-occurrence frequency and the semantic features. The correctness of the error correction words is judged, and the text proofreading accuracy can be improved. When the correctness of the error correction words is judged, the matching of front and back words and context semantic features are comprehensively considered, so that the accuracy of judging the correctness of the error correction words can be ensured, and the text proofreading accuracy is further improved. Moreover, the calibration work is intelligent and automatic, the pressure of manual calibration is reduced, the working efficiency is improved, and the labor cost is reduced.

The invention discloses a processing method for a DigRF retransmission failure. The processing method comprises the following steps. S10, when the receiver finds that the frame transmitted through theDigRF protocol fails to be retransmitted, the receiver sends the NACK frame of the retransmitted frame to the sender, wherein the frame with the retransmission failure is called as a lost frame; S20,the sender receives the NACK frame of the retransmission frame, and informs the receiver of the ID and/or retransmission sequence of the data logic channel in the lost frame; and S30, the receiver receives the ID and/or retransmission sequence of the data logic channel in the lost frame, acquires the length of the lost frame and the attribution of the lost frame data, and fills compensation datagenerated locally at the position of the lost frame. According to the method and the device, after retransmission failure of the DigRF interface occurs, the correctness of the data time sequence afterframe loss can be ensured, performance loss or call drop and the like caused by a traditional method are avoided, and the overall robustness of a system is improved.